The device private pointer (dev_private) is of type void *
therefore no cast is necessary in C.
Cc: stable@dpdk.org
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Add 'rte_' prefix to structures:
- rename struct ether_addr as struct rte_ether_addr.
- rename struct ether_hdr as struct rte_ether_hdr.
- rename struct vlan_hdr as struct rte_vlan_hdr.
- rename struct vxlan_hdr as struct rte_vxlan_hdr.
- rename struct vxlan_gpe_hdr as struct rte_vxlan_gpe_hdr.
Do not update the command line library to avoid adding a dependency to
librte_net.
Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Reviewed-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
All Rx packet handling is done in process_responses() and hence
t4_ethrx_handler() never gets called. So, remove it.
Signed-off-by: Vishal Kulkarni <vishal@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Shifting signed 32-bit values by 31-bits has the potential for
unexpected outcomes as compiler can overwrite a bit.
Specified that values are unsigned.
Errors are observed from running cppcheck.
Bugzilla ID: 58
Fixes: 69e209be54 ("net/axgbe: add register map and related macros")
Fixes: b5bf771922 ("bnx2x: driver support routines")
Fixes: ed2ced6fe9 ("net/bnxt: check initialization before accessing stats")
Fixes: 6fda3f0ddd ("net/cxgbe: add API to program hardware MPS table")
Fixes: bdb244b969 ("e1000: whitespace changes")
Fixes: 5a32a257f9 ("e1000: more NICs in base driver")
Fixes: 2fe669f4bc ("net/nfp: support MAC address change")
Fixes: defb9a5dd1 ("nfp: introduce driver initialization")
Fixes: ec94dbc573 ("qede: add base driver")
Fixes: d2e7d931d0 ("net/qede/base: formatting changes")
Fixes: cdc07e83bb ("net/tap: add eBPF program file")
Cc: stable@dpdk.org
Signed-off-by: Andrius Sirvys <andrius.sirvys@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Fix following build errors reported by Intel C++ compiler in Windows
build.
C:\> t4_hw.c(5105): warning #147: declaration is incompatible with
"int t4_bar2_sge_qregs(struct adapter *, unsigned int, unsigned int,
u64={uint64_t={unsigned __int64}} *, unsigned int *)"
(declared at line 524 of "..\..\..\..\drivers\net\cxgbe\base\common.h")
int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
^
C:\> cxgbe_filter.c(42): error : expected an expression
n_user_filters = mult_frac(adap->tids.nftids,
^
C:\> sge.c(400): error : expression must be a pointer to a complete
object type
(uint16_t)(RTE_PTR_ALIGN((char *)mbuf->buf_addr +
^
Build Environment:
1. Target OS: Microsoft Windows Server 2016
2. Compiler: Intel C++ Compiler from Intel Parallel Studio XE 2019 [1]
3. Development Tools:
3.1 Microsoft Visual Studio 2017 Professional
3.2 Windows Software Development Kit (SDK) v10.0.17763
3.3 Windows Driver Kit (WDK) v10.0.17763
[1] https://software.intel.com/en-us/parallel-studio-xe
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Define symbols only when they are not available.
This fixes following types of issues reported by Intel C++ compiler
in Windows build.
C:\> cxgbe_compat.h(154): warning #47: incompatible redefinition of
macro "min"
#define min(a, b) RTE_MIN(a, b)
^
C:\> t4_hw.c(338): warning #266: function "bzero" declared implicitly
bzero(p, 0, size);
^
C:\> t4_hw.c(5337): warning #266: function "htonl" declared implicitly
rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
^
C:\> sge.c(361): error : expected an expression
struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, fl);
^
C:\> sge.c(1350): error : identifier "caddr_t" is undefined
static void inline_tx_mbuf(const struct sge_txq *q, caddr_t from,
^
[...]
Build Environment:
1. Target OS: Microsoft Windows Server 2016
2. Compiler: Intel C++ Compiler from Intel Parallel Studio XE 2019 [1]
3. Development Tools:
3.1 Microsoft Visual Studio 2017 Professional
3.2 Windows Software Development Kit (SDK) v10.0.17763
3.3 Windows Driver Kit (WDK) v10.0.17763
[1] https://software.intel.com/en-us/parallel-studio-xe
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
The Intel C++ compiler is not able to locate the header files without
relative paths in Windows build. Following errors are seen for these
header files.
C:\> base\common.h(9): error : cannot open source file "cxgbe_compat.h"
#include "cxgbe_compat.h"
^
[...]
Fix by explicitly stating header file location using relative paths.
Also, remove automatically including header files for Linux, to keep
it consistent across both OS.
Build Environment:
1. Target OS: Microsoft Windows Server 2016
2. Compiler: Intel C++ Compiler from Intel Parallel Studio XE 2019 [1]
3. Development Tools:
3.1 Microsoft Visual Studio 2017 Professional
3.2 Windows Software Development Kit (SDK) v10.0.17763
3.3 Windows Driver Kit (WDK) v10.0.17763
[1] https://software.intel.com/en-us/parallel-studio-xe
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Implement RTE_FLOW_ACTION_TYPE_MAC_SWAP to offload flows with
action to swap the source and destination MAC addresses in the
outermost Ethernet header.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Query firmware for the new filter work request to offload flows with
actions to modify IP and TCP/UDP port addresses. When available,
translate IP and TCP/UDP port address modify actions to internal
hardware specification and offload the flow to hardware.
Original work by Shagun Agrawal
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add flow operations to match packets based on destination MAC address.
Allocate and program hardware MPS table with the destination MAC
address to be matched against. The returned MPS index is then used while
offloading flows to LETCAM (maskfull) and HASH (maskless) filter regions.
Also update existing mac_addr_set() to use the new MPS table API.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add API to program and manage hardware Multi Port Switch table. MPS
holds destination MAC addresses to be matched against incoming packets
for further rule processing. Packets not matching any entry in MPS table
will be dropped by default, unless the underlying port is in promiscuous
mode.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add flow API operations to offload vlan push, pop, and rewrite actions.
For vlan push or rewrite actions, allocate and program an entry from
L2T table. Use the L2T index to program vlan actions for LETCAM
(maskfull) and HASH (maskless) filters.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add API to program and manage hardware Layer 2 Table. L2T holds
information necessary to rewrite specific fields in packet, such
as destination MAC address and vlan id.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add decode logic for new flash parts shipped with new Chelsio NICs
to fix initialization failure on these NICs.
Cc: stable@dpdk.org
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Set the Rx channel map and ingress queue type properly to allow firmware
to manage the internal mapping correctly.
Fixes: 6c2809628c ("net/cxgbe: improve latency for slow traffic")
Cc: stable@dpdk.org
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Query firmware for max Tx and Rx queues that can be allocated.
Move the code to determine max queues to common place for both
PF and VF.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add action to redirect matched packets to specified egress physical
port without sending them to host.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add interface to enable hit counters for flows offloaded in HASH
region.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add interface to delete offloaded flows in HASH region. Use the
hash index saved during insertion to delete the corresponding flow.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add interface to offload flows to HASH region. Translate internal
filter specification to requests to offload flows to HASH region.
Save the returned hash index of the offloaded flow for deletion later.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
CLIP region holds destination IPv6 addresses to be matched for
corresponding flows. Query firmware for CLIP resources and allocate
table to manage them. Also update LE-TCAM to use CLIP to reduce
number of slots needed to offload IPv6 flows.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Fetch supported match items in HASH region. Ensure the mask
is all set for all the supported match items to be offloaded
to HASH region. Otherwise, offload them to LE-TCAM region.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Fetch available HASH filter resources and allocate table for managing
them. Currently only supported on Chelsio T6 family of NICs.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add API to query filter hit and byte counts from hardware.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Define filter work request API used to construct filter operations
to be communicated with firmware. These requests are sent via
control queue and completions come asynchronously in firmware event
queue.
Implement flow create operation to create filters in LE-TCAM
(maskfull) region at specified index.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add control queue to communicate filter creation/deletion requests
with firmware. This API will be used by subsequent patches.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Introduce rte_flow skeleton and implement validate operation.
Parse and convert <item>, <action>, <attributes> into hardware
specification. Perform validation, including basic sanity tests
and underlying device's supported filter capability checks.
Currently add support for:
<item>: IPv4, IPv6, TCP, and UDP.
<action>: Drop, Queue, and Count.
Also add sanity checks to ensure filters are created at specified
index in LE-TCAM region. The index in LE-TCAM region indicates
the filter rule's priority with index 0 having the highest priority.
If no index is specified, filters are created at closest available
free index.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Fetch available filter resources from firmware and allocate table for
book-keeping and managing filters in hardware. Also define the hardware
filter specification (ch_filter_specification) used to describe each
filter rule.
Signed-off-by: Shagun Agrawal <shaguna@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
On TX path, add fw_eth_tx_pkt_vm_wr to transmit packets over VF.
Use is_pf4() to correctly calculate the work request size and
offsets within the work request. On RX path, use pktshift to adjust
data offset within the mbuf.
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add probe to initialize VF devices. Separate init/de-init paths
for PF and VF. Do firmware state initialization wrt VF and retrieve
various operational parameters by querying firmware. Finally configure
and initialize ports.
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add firmware mailbox communication support for VF. Add is_pf4()
to check if driver is attached to PF4. Use is_pf4() to determine
whether to use PF or VF mailbox communication.
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
The new code uses the new 32-bit Port Capabilities exclusively and
only translates to/from the old 16-bit Port Capabilities at the last
point possible when talking to older Firmware.
For the old versus new Firmware issue, we use the new FW_PARAMS_CMD[PFVF,
CAPS32] command to tell the Firmware that we want Asynchronous Port Status
updates to use the new 32-bit version of the Port Information message. If
we get an error, we know we're dealing with older Firmware, and if not,
we'll start getting th new 32-bit Port Capability message formats.
Also, refactor t4_handle_fw_rpl() to handle new 32-bit Port Capability
replies from firmware in t4_handle_get_port_info().
Original work by Surendra Mobiya <surendra@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Update link configuration API to prepare for 32-bit port capability
support. Continue using 16-bit port capability for older firmware.
Original work by Surendra Mobiya <surendra@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Normally, firmware reads various Forward Error Correction parameters
from a Transceiver Module i2c EPROM and uses a couple of IEEE Standards
(802.3bj for 100Gb/s and 802.3by for 25Gb/s) to interpret those
parameters and come up with supported and default FEC settings.
Firmware then sends these FEC parameters to the Host Driver which gives
the Host Administrator an opportunity to change them if necessary in
order to establish a Link with a Switch which may have made a
non-standard FEC decision.
This commit recognizes "auto" as a discrete FEC mode which can be
used to explicitly select the IEEE 802.3 standard based FEC selection.
Original work by Surendra Mobiya <surendra@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Original work by Surendra Mobiya <surendra@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Add firmware API for updating RSS hash configuration and key. Move
RSS hash configuration from cxgb4_write_rss() to a separate function
cxgbe_write_rss_conf().
Also, rename cxgb4_write_rss() to cxgbe_write_rss() for consistency.
Original work by Surendra Mobiya <surendra@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Attach to rte_eth_dev devices allocated by Primary process for
Ports other than Port-0 in the secondary process.
Save the Primary rte_eth_dev device eth_dev_data as part of txq
structure needed for tx path.
Fixes: 8318984927 ("cxgbe: add pmd skeleton")
Cc: stable@dpdk.org
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Rework rte_eth_dev allocation for other ports under same PF.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Create a rte_ethdev_driver.h file and move PMD specific APIs here.
Drivers updated to include this new header file.
There is no update in header content and since ethdev.h included by
ethdev_driver.h, nothing changed from driver point of view, only
logically grouping of APIs. From applications point of view they can't
access to driver specific APIs anymore and they shouldn't.
More PMD specific data structures still remain in ethdev.h because of
inline functions in header use them. Those will be handled separately.
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Shreyansh Jain <shreyansh.jain@nxp.com>
Acked-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
The memzone header is often included without good reason.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
