Add support to below TCP segmentation offloads for
96XX A1 onwards and 95xx B0 onwards.
- TCPv4, TCPv6
- VXLAN[v4 | v6][v4 | v6]
- GENEVE[v4 | v6][v4 | v6]
This patch also modifies a fastpath function to be forced
inline due to performance reasons for multi-seg mode.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Update LB ltypes and use the updated ones so as replace
LB_STAG and LB_QINQ by single LB_STAG_QINQ ltype.
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
NPC errors were incorrectly translated to ol_flag as
error code enum was not in sync with NPC profile.
Fixes: 371d3212cb ("common/octeontx2: add build infrastructure and HW definition")
Cc: stable@dpdk.org
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
'cpt_logtype' & 'otx_cryptodev_driver_id' global variables are defined
in a header file which was causing multiple definitions of the
variables. Fixed it by moving the required vars to the .c file and
introducing a new macro so the CPT_LOG macros in common/cpt would use
the associated PMD log var.
Issue has been detected by '-fno-common' gcc flag.
Fixes: bfe2ae495e ("crypto/octeontx: add PMD skeleton")
Cc: stable@dpdk.org
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Reported-by: Ferruh Yigit <ferruh.yigit@intel.com>
This patch adds few definitions specific to GEN3 QAT.
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
With the latest firmware, there are few changes for zuc and snow3g.
1. The iv_source is present in bitfield 7 of minor opcode. In the
old firmware this was present in bitfield 6.
2. Algorithm type is a 2 bit field in new firmware. In the old
firmware it was named as cipher type and it was a 1 bit field.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
This patch adds QAT RAM bank definitions and related macros.
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Octeontx2 PMD's mailbox client uses device memory to send messages
to mailbox server in the admin function Linux kernel driver.
The device memory used for the mailbox communication needs to
be qualified as volatile memory type to avoid unaligned device
memory accesses because of compiler's memory access coalescing.
This patch modifies the mailbox request and responses as volatile
type which were non-volatile earlier and accessed from unaligned
memory addresses which resulted in bus errors on Fedora 30 with
gcc 9.1.1.
Fixes: 2b71657c86 ("common/octeontx2: add mbox request and response definition")
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Update workaround changes for erratas that are fixed on 96xx A1.
This patch also enables cq drop for all the passes for
maintaining performance along with updating a default
Rx ring size in dev_info.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
OTX2 AP core can sometimes fissure STP instructions when it is more
optimal to send such writes into the pipeline as 2 separate
instructions. However registers should be excluded from such
optimization. This commit ensures that no CSR write is ever fissured
by introducing zero cost workaround by setting STP pre-index by zero to
make sure OTX2 AP core prevent fissure.
Fixes: 8a4f835971 ("common/octeontx2: add IO handling APIs")
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
This patch implements read clock api whose purpose is to return
raw clock ticks. Using this API real time ticks spent in
processing a packet can be known:
<read_clock val at any time> - mbuf->timestamp
Calling mbox for reading raw clock ticks in fastpath is very
expensive so its value is derived from time stamp counter(tsc)
using freq multiplier (ratio of raw clock ticks and tsc) and clock
delta (by how much tsc is lagging from raw clock value).
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This patch fixes fail status returned from compression PMD
in case destination buffer size is not enough to store
all data.
Fixes: 3dc9ef2d23 ("compress/qat: fix returned status on overflow")
Cc: stable@dpdk.org
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
This patch changes the key pointer data types in cipher, auth,
and aead xforms from "uint8_t *" to "const uint8_t *" for a
more intuitive and safe sessionn creation.
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Acked-by: Liron Himi <lironh@marvell.com>
Putting color escape sequences in the log look pretty for the
developer but fails in real world DPDK usage. A real application
will put DPDK log to syslog, and syslog does not handle escape
sequences.
Fixes: dd543124cd ("common/octeontx2: add runtime log infra")
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Update platform support of CNF95xx in documentation and
also, update the HW cap based on PCI subsystem id and revision id.
This patch also changes HW capability handling to be based on
PCI Revision ID. PCI Revision ID contains a unique identifier
to identify chip, major and minor revisions.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
mbox_unregister_vf_irq and mbox_unregister_pf_irq returns void value.
mbox_unregister_irq also returns void.
Clang with flags '-Wall -Wextra -pedantic' complains about:
void function should not return void expression
Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
Fix the following ICC specific compilation issue with i686 build.
dpdk/drivers/common/octeontx2/otx2_mbox.c(47): error #2259:
non-pointer conversion from "unsigned long long" to "struct mbox_hdr *"
may lose significant bits
(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->tx_start);
Fixes: 732377a679 ("mempool/octeontx2: add build infra and device probe")
Fixes: 371d3212cb ("common/octeontx2: add build infrastructure and HW definition")
Signed-off-by: Amit Gupta <agupta3@marvell.com>
For each driver where we optionally disable it, add in the reason why it's
being disabled, so the user knows how to fix it.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Luca Boccassi <bluca@debian.org>
NPA object needs to initialize memory for queue interrupts context,
pool resource management, etc. This patch adds support for initializing
and finalizing the NPA object.
This patch also updates the otx2_npa_lf definition to meet the init/fini
requirements.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Add the make and meson based build infrastructure along
with the mempool(NPA) device probe.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Upon receiving FLR request from VF, It is PF responsibly
forward to AF and enable FLR for VFs.
This patch adds support for VF FLR support in PF.
This patch also add otx2_dev_active_vfs() API to find
the number of active VF for given PF.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
The events like PHY link status change by AF or PHY configuration
change by PF would call for the uplink message.
The AF initiated uplink would land it in PF and PF would further
forward to VF(if it is intended for that specific VF)
The PF initiated uplink would be distributed to all active VFs.
This patch adds support for the same.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
PF has additional responsibility being server for VF messages
and forward to AF and once AF process it then forward
the response back to VF.
otx2_vf_pf_mbox_irq() will process the VF mailbox request and
af_pf_wait_msg() will until getting a response back from AF.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
This patch adds support for AF to PF mailbox interrupt and message
handling. PF writes the message on mapped mailbox region
followed by writing the mailbox doorbell register. Upon receiving,
the mailbox request in AF(In Linux kernel), It processes the messages
and update the counter memory and update the AF mbox doorbell
register. That would trigger a VFIO interrupt to userspace and
otx2_process_msgs() will handle it.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
The mempool device(NPA) may be provisioned as a standalone device or
it can be part of ethdev/eventdev device. In order to address
mempool as standalone or integrated with ethdev/eventdev device,
An intra device structure being introduced.
When the _first_ ethdev/eventdev PCIe device or standalone mempool(NPA)
devices get probed by the eal PCI subsystem,
The NPA object(struct otx2_npa_lf) stored in otx2_dev base class.
Once it is accomplished, the other consumer drivers like
ethdev driver or eventdev driver use otx2_npa_* API to operate on
shared NPA object.
The similar concept followed for SSO object, Which needs to share between
PCIe devices.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
All PCIe drivers(ethdev, mempool, cryptodev and eventdev) in octeontx2,
needs to handle interrupt for mailbox and error handling.
Create a helper function over rte interrupt API to register,
unregister, disable interrupts.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
Introduce otx2_dev class to hold octeontx2 PCIe device specific
information and operations.
All PCIe drivers(ethdev, mempool, cryptodev and eventdev) in octeontx2,
inherits this base object to avail the common functionalities such
as mailbox creation, interrupt registration, etc of the PCIe device.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Each RVU device has a dedicated 64KB mailbox region
shared with its peer for communication. RVU AF has
a separate mailbox region shared with each of RVU PFs
and an RVU PF has a separate region shared with each of
it's VF.
This patch add use 64KB memory and implemented mailbox
send and receive support.
These set of APIs are used by this driver (RVU AF) and
other RVU PF/VF drivers eg ethdev, cryptodev e.t.c.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
This patch adds mailbox init and fini support.
Each RVU device has a dedicated 64KB mailbox region
shared with its peer for communication. RVU AF has
a separate mailbox region shared with each of RVU PFs
and an RVU PF has a separate region shared with
each of it's VF.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
The admin function driver sits in Linux kernel as mailbox
server. The DPDK AF mailbox client, send the message to mailbox
server to complete the administrative task such as get mac
address.
This patch adds mailbox request and response definition of
existing mailbox defined between AF driver and DPDK driver.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
Signed-off-by: Zyta Szpak <zyta@marvell.com>
Various octeontx2 drivers use IO handling API, added octeontx2
specific IO handling routines in the common code.
Since some of those implementations are based on arm64 instructions
added the stub to compile the code on non arm64 ISA.
The non arm64 ISA stub is possible due to the fact that
it is an integrated controller i.e runs only on Marvell HW.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Add the make and meson based build infrastructure along with
HW definition header file.
This patch adds skeleton otx2_mbox.c file to make sure
all header files are intact, subsequent patches add content
to otx2_mbox.c
This patch also updates CONFIG_RTE_MAX_VFIO_GROUPS
value to 128 as the system can have up to 128 PFs/VFs.
For octeontx2 meson build target, CONFIG_RTE_MAX_VFIO_GROUPS
defined as 128 so no additional changes required.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
By default on 32-bit systems, file offsets are given as 32-bit values
which prevents support for large files. While this is unlikely to be
a problem, enabling large file support globally makes "make" and
"meson" builds consistent, since meson always enables large file
support, and without this change, the size of "struct stat" fields
will be different between the two builds.
The only location where this appears to be significant is in the
dpaax common code, where a printf needs to be updated for 32-bit
builds.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Acked-by: Shreyansh Jain <shreyansh.jain@nxp.com>
The metabuf pool is shared across all queue pairs belonging to the
PMD. In order to prevent one queue pair from starving another,
use a distinct mempool for each queue pair.
Fixes: 273487f7b3 ("crypto/octeontx: add global resource init")
Cc: stable@dpdk.org
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Shally Verma <shallyv@marvell.com>
Define variables for "is_linux", "is_freebsd" and "is_windows"
to make the code shorter for comparisons and more readable.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Luca Boccassi <bluca@debian.org>
This patch assigns QAT queue pair resources to the correct NUMA nodes.
Any DMA'able memory should use NUMA node of QAT device
rather than socket_id of the initializing process.
Fixes: 98c4a35c73 ("crypto/qat: move common qat files to common dir")
Fixes: a795248d74 ("compress/qat: add configure and clear functions")
Cc: stable@dpdk.org
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This commit adds modular multiplicative inverse to Intel
QuickAssist Technology driver. For capabilities or limitations
please refer to qat.rst or qat_asym_capabilities.h.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This commit adds modular exponentiation to Intel QuickAssist
Technology driver. For capabilities or limitations please refer to
qat.rst or qat_asym_capabilities.h.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This patch adds Poll Mode Driver for asymmetric crypto
functions of Intel QuickAssist Technology hardware.
It contains plain driver with no functions implemented, specific
algorithms will be introduced in separate patches.
This patch depends on a QAT PF driver for device initialization. See
the file docs/guides/cryptodevs/qat.rst for configuration details.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This commit adds headers to be used in conjunction with asymmetric
cryptography operations using Intel QuickAssist Technology driver
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Moving upper level enqueue/dequeue routines to driver. The h/w interface
used to submit request has enough differences to substantiate the need
for separate routines.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
The check for prep_req is good enough to flag error. The return var
passed around is redundant. Fixing this. Also making the functions
return correct error values in case of various failures.
In addition, adding unlikely flag for all error checks.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
