524 Commits

Author SHA1 Message Date
Hemant Agrawal
05b12700cd crypto/dpaa_sec: support null algos for protocol offload
NULL cipher and NULL auth support is added.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:18:38 +02:00
Hemant Agrawal
e117c18a1d crypto/dpaa2_sec: restructure session management
Code for session create is restructured to make scalable to
support different algorithms.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:18:38 +02:00
Hemant Agrawal
547a4d40e7 crypto/dpaa2_sec: support out of place protocol offload
OOP support for look aside protocol support is added.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:18:38 +02:00
Akhil Goyal
db60e550d5 crypto/dpaa2_sec: enable sequence no rollover
With this patch sequence number will be rolled over and
SEC block will ignore the sequence number overflow error.

Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:18:38 +02:00
Akhil Goyal
79fde9d00c crypto/dpaa_sec: enable sequence no rollover
With this patch sequence number will be rolled over and
SEC block will ignore the sequence number overflow error.

Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:18:38 +02:00
Hemant Agrawal
551a42a993 crypto/dpaa_sec: reduce number of qp per device
In dpaa_sec, there are unlimited queues, but in order
to match the DPDK handling of queue pairs, rx side queues
are still unlimited, but the application will see only limited
qp (tx queues) from dpaa_sec hw.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:18:38 +02:00
Akhil Goyal
9198b2c227 crypto/dpaa_sec: do not attach session for non-matching qp
if session->qp != qp to be enqueued, it should show an error and
not try to re-attach another qp.

Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:18:38 +02:00
Akhil Goyal
3b617ee775 crypto/dpaa_sec: add lock before Rx HW queue attach
This is to safeguard as the session config can be done from multi-threads.

Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:18:38 +02:00
Akhil Goyal
b0894102cb crypto/dpaa: reset session before init
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:20:26 +02:00
Hemant Agrawal
3373a36ba7 crypto/dpaa: update the flib RTA
hw flib code is updated as per the latest set of APIs and macros

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-09-26 13:18:38 +02:00
Pablo de Lara
ceb8639387 crypto/aesni_gcm: support all truncated digest sizes
The full digest size of GCM/GMAC algorithms is 16 bytes.
However, it is sometimes truncated to a smaller size (such as in IPSec).
This commit allows a user to generate a digest of any size
up to the full size.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Marko Kovacevic <marko.kovacevic@intel.com>
2018-09-26 12:43:57 +02:00
Pablo de Lara
c7c29f1058 crypto/aesni_gcm: remove unneeded J0 calculation
When IV size is 12, padding to 16 bytes is required
and the LSB must be set to 1, according to the spec.
However, the Multi-buffer library is already doing this,
so it is not necessary to do it in the PMD.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Marko Kovacevic <marko.kovacevic@intel.com>
2018-09-26 12:43:57 +02:00
Pablo de Lara
d0fe8c48a4 crypto/aesni_mb: support large HMAC key sizes
Add support for SHAx-HMAC key sizes larger than the block size.
For these sizes, the input key is digested with the non-HMAC
version of the algorithm and used as the key.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Marko Kovacevic <marko.kovacevic@intel.com>
2018-09-26 12:45:13 +02:00
Pablo de Lara
035ecca5ea crypto/aesni_mb: support all truncated CMAC digest sizes
The full digest size of CMAC algorithm is 16 bytes.
However, it is sometimes truncated to a smaller size (such as in IPSec).
This commit allows a user to generate a digest of any size
up to the full size.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Marko Kovacevic <marko.kovacevic@intel.com>
2018-09-26 12:45:05 +02:00
Pablo de Lara
16a3558e0b crypto/aesni_mb: fix truncated digest size for CMAC
The truncated digest size for AES-CMAC is 12 and not 16,
as the Multi-buffer library can output both 12 and 16 bytes.

Fixes: 6491dbbecebb ("crypto/aesni_mb: support AES CMAC")
Cc: stable@dpdk.org

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Marko Kovacevic <marko.kovacevic@intel.com>
2018-09-26 12:44:57 +02:00
Pablo de Lara
c4c0c312a8 crypto/aesni_mb: check for invalid digest size
When creating a crypto session, check if
ther requested digest size is supported for
AES-XCBC-MAC and AES-CCM.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Marko Kovacevic <marko.kovacevic@intel.com>
2018-09-26 12:44:51 +02:00
Pablo de Lara
763c24917d crypto/aesni_mb: support all truncated HMAC digest sizes
HMAC algorithms (MD5 and SHAx) have different full digest sizes.
However, they are often truncated to a smaller size (such as in IPSec).
This commit allows a user to generate a digest of any size
up to the full size.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Marko Kovacevic <marko.kovacevic@intel.com>
2018-09-26 12:43:57 +02:00
Pablo de Lara
95978a85a4 crypto/aesni_mb: fix possible array overrun
In order to process crypto operations in the AESNI MB PMD,
they need to be sent to the buffer manager of the Multi-buffer library,
through the "job" structure.

Currently, it is checked if there are outstanding operations to process
in the ring, before getting a new job. However, if there are no available
jobs in the manager, a flush operation needs to take place, freeing some
of the jobs, so it can be used for the outstanding operation.

In order to avoid leaving the dequeued operation without being processed,
the maximum number of operations that can be flushed is the remaining
operations to return, which is the maximum number of operations that can
be return minus the number of operations ready to be returned
(nb_ops - processed_jobs), minus 1 (for the new operation).

The problem comes when (nb_ops - processed_jobs) is 1 (last operation to
dequeue). In that case, flush_mb_mgr is called with maximum number of
operations equal to 0, which is wrong, causing a potential overrun in the
"ops" array.
Besides, the operation dequeued from the ring will be leaked, as no more
operations can be returned.

The solution is to first check if there are jobs available in the manager.
If there are not, flush operation gets called, and if enough operations
are returned from the manager, then no more outstanding operations get
dequeued from the ring, avoiding both the memory leak and the array
overrun.
If there are enough jobs, PMD tries to dequeue an operation from the ring.
If there are no operations in the ring, the new job pointer is not used,
and it will be used in the next get_next_job call, so no memory leak
happens.

Fixes: 0f548b50a160 ("crypto/aesni_mb: process crypto op on dequeue")
Cc: stable@dpdk.org

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2018-09-25 17:57:25 +02:00
Tomasz Duszynski
e04ec42af0 net/mvpp2: align with MUSDK 18.09
This patch introduces necessary changes required by MUSDK 18.09 library.

* As of MUSDK 18.09, pp2_cookie_t is no longer available. Now
  RX descriptor cookie is defined as plain u64 so existing cast
  is no longer valid.

* MUSDK 18.09 increased number of available bpools (buffer hw pools) by
  introducing dma regions support. Update mvpp2 driver accordingly.

* replace MV_NET_IP4_F_TOS with MV_NET_IP4_F_DSCP

  Before this patch, API allowed to configure a classification rule
  according to IPv4 TOS, which was not supported in classifier. This patch
  fixes this by using proper field.

* use 48 bit address mask

  We cannot get pointers exceeding 48 bits thus using 48 bit
  mask for extracting higher IOVA address bits is enough.

Signed-off-by: Natalie Samsonov <nsamsono@marvell.com>
Signed-off-by: Yuval Caduri <cyuval@marvell.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
Reviewed-by: Shlomi Gridish <sgridish@marvell.com>
Reviewed-by: Alan Winkowski <walan@marvell.com>
Reviewed-by: Liron Himi <lironh@marvell.com>
2018-09-28 01:41:03 +02:00
Shreyansh Jain
eb5a9a7639 drivers/crypto: remove double assignment of driver
Removing double copy of driver information. 04664e5c8346 has shifted
that from driver's probe to bus's probe.

Fixes: 04664e5c8346 ("drivers/bus: fill driver reference after NXP probing")

Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2018-09-28 18:02:58 +02:00
Luca Boccassi
cd2b6458a1 crypto/scheduler: add in meson build
Signed-off-by: Luca Boccassi <bluca@debian.org>
2018-09-18 22:53:35 +02:00
Ashish Gupta
0b5284ad57 crypto/openssl: replace macros by static inline functions
Replace macros by static inline functions in openssl version
compatibility layer

Signed-off-by: Sunila Sahu <sunila.sahu@caviumnetworks.com>
Signed-off-by: Shally Verma <shally.verma@caviumnetworks.com>
Signed-off-by: Ashish Gupta <ashish.gupta@caviumnetworks.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-08-30 05:10:50 +02:00
Fiona Trahe
6a3e44717d crypto/qat: fix typo
Fixes: f9a3d7f68f05 ("crypto/qat: move code into appropriate files")

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
2018-08-30 05:10:50 +02:00
Tomasz Jozwiak
b30aa8911c common/qat: fix offset greater than first segment
This patch fixes sgl filling to handle offset
greater than first sgl segment

Fixes: 1947bd18580b ("compress/qat: support scatter-gather buffers")

Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2018-08-03 09:14:24 +02:00
Sunila Sahu
ac42813a0a crypto/openssl: add DH and DSA asym operations
- Add dh key generation and shared compute
- Add dsa sign and verify operation

Signed-off-by: Sunila Sahu <sunila.sahu@caviumnetworks.com>
Signed-off-by: Shally Verma <shally.verma@caviumnetworks.com>
Signed-off-by: Ashish Gupta <ashish.gupta@caviumnetworks.com>
2018-07-25 08:22:14 +02:00
Sunila Sahu
3e9d6bd447 crypto/openssl: add RSA and mod asym operations
- Add compat.h to make pmd compatible to openssl-1.1.0 and
  backward version
- Add rsa sign/verify/encrypt/decrypt and modular operation
  support

Signed-off-by: Sunila Sahu <sunila.sahu@caviumnetworks.com>
Signed-off-by: Shally Verma <shally.verma@caviumnetworks.com>
Signed-off-by: Ashish Gupta <ashish.gupta@caviumnetworks.com>
2018-07-25 08:22:14 +02:00
Fan Zhang
6760463c9f crypto/scheduler: add mode-specific threshold parameter
This patch adds packet-size-distr mode specific parameter parser
to support different threshold packet size value other than default
128 bytes.

Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-07-25 08:19:54 +02:00
Fan Zhang
ee9586dd15 crypto/scheduler: add mode-specific parameter
This patch adds the mode parameter parsing to scheduler PMD.

Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
2018-07-25 08:19:54 +02:00
Fiona Trahe
944027acd4 common/qat: add scatter-gather header
This patch refactors the sgl struct so it includes a flexible
array of flat buffers as sym and compress PMDs can have
different size sgls.

Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
2018-07-25 08:19:54 +02:00
Pablo de Lara
4487cfa1fa crypto/virtio: fix memory leak
Put session private data back to mempool when clearing
a crypto session, which is expected to be done in the PMD.

Fixes: b7fa78c7d3b0 ("crypto/virtio: support session related ops")
Cc: stable@dpdk.org

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Reviewed-by: Jay Zhou <jianjay.zhou@huawei.com>
2018-07-24 01:48:10 +02:00
Fiona Trahe
e3d9988442 crypto/qat: support 8-byte 3DES
Added extra case to support 8 byte key size
for 3DES CBC. Also changed capabilities to reflect
the change.

Signed-off-by: Marko Kovacevic <marko.kovacevic@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2018-07-24 01:48:10 +02:00
Marko Kovacevic
9607e37e8c crypto/openssl: support 8-byte 3DES
Added extra case to support 8 byte key size
for 3DES CBC. Also changed capabilities to reflect
the change.

Signed-off-by: Marko Kovacevic <marko.kovacevic@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2018-07-24 01:48:10 +02:00
Marko Kovacevic
06c761d6fb crypto/aesni_mb: support 3DES
Added support for 3DES cipher algorithm which
will support 8, 16 and 24 byte keys, which also has been
added in the v0.50 of the IPSec Multi-buffer lib.

Signed-off-by: Marko Kovacevic <marko.kovacevic@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2018-07-24 01:48:10 +02:00
Pablo de Lara
58d3852ef5 crypto/aesni_mb: support IPsec Multi-buffer lib v0.50
Adds support for the v0.50 of the IPsec Multi-buffer lib.
The library now exposes its version, with the idea
of maintaining backwards compatibility in the future,
avoiding breaking the compilation of the PMD every time
there is a new version available.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2018-07-24 01:48:10 +02:00
Pablo de Lara
f961a887d7 crypto/aesni_gcm: support IPsec Multi-buffer lib v0.50
Adds support for the v0.50 of the IPsec Multi-buffer lib.
The library now exposes its version, with the idea
of maintaining backwards compatibility in the future,
avoiding breaking the compilation of the PMD every time
there is a new version available.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2018-07-24 01:48:10 +02:00
Pablo de Lara
862c0a9643 crypto/aesni_mb: call buffer manager allocation
Instead of having a static field for the buffer manager
MB_MGR in the queue pair structure, use the provided API
that allocates memory for it and store a pointer to it.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2018-07-24 01:48:10 +02:00
Fiona Trahe
64cb90f882 crypto/qat: fix checks for 3GPP algo bit params
QAT driver checks byte alignment for KASUMI/SNOW 3G/ZUC algorithms using
cipher/auth_param, which are not initialized at this moment yet. Use
operation params instead.

Fixes: 39e0bee48e81 ("crypto/qat: rework request builder for performance")
Cc: stable@dpdk.org

Reported-by: Dmitry Eremin-Solenikov <dmitry.ereminsolenikov@linaro.org>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2018-07-24 01:48:10 +02:00
Fiona Trahe
7a34c21557 compress/qat: add empty driver
Add Makefiles, meson files, and empty source files for compression PMD.
Handle cases for building either symmetric crypto PMD
or compression PMD or both and the common files both depend on.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
2018-07-24 01:48:10 +02:00
Hemant Agrawal
2aaffeee7b drivers: support function name in NXP logs
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Shreyansh Jain <shreyansh.jain@nxp.com>
2018-07-12 14:41:28 +02:00
Nipun Gupta
f40d5a53ec bus/dpaa: make vdqcr configurable
This patch add support for configurable vdqcr exact flag.
This boost the performance, however this can give
side effects for some extra packet fetch. Which has been
taken care in the patch as well.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Shreyansh Jain <shreyansh.jain@nxp.com>
2018-07-12 14:39:54 +02:00
Thomas Monjalon
f8e9989606 remove useless constructor headers
A constructor is usually declared with RTE_INIT* macros.
As it is a static function, no need to declare before its definition.
The macro is used directly in the function definition.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
2018-07-12 00:00:35 +02:00
Anoob Joseph
6c8e8dfe69 crypto/scheduler: add minimum head/tailroom requirement
Minimum head/tailroom requirement for each PMD has to be considered
while populating the dev_info.

Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2018-07-11 03:57:24 +02:00
Pablo de Lara
012c5076d4 cryptodev: rename PMD symmetric session API
The PMD specific API to configure, clear and
obtain session private size is renamed, including
the word _sym_ to clarify that it is API
for symmetric sessions, so there will not be any
conflicts for asymmetric and other type of sessions
in the future.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-07-11 03:57:24 +02:00
Pablo de Lara
9843546b8e cryptodev: remove attach/detach session API
As announced in the previous release,
The API to attach/dettach a session to a queue pair
is removed, as it was only used in DPAA, and it is not
actually needed.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-07-11 03:57:24 +02:00
Pablo de Lara
2717246ecd cryptodev: replace mbuf scatter gather flag
The current mbuf scatter gatter feature flag is
too ambiguous, as it is not clear if input and/or output
buffers can be scatter gather mbufs or not, plus
if in-place and/or out-of-place is supported.

Therefore, five new flags will replace this flag:
- RTE_CRYPTODEV_FF_IN_PLACE_SGL
- RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT
- RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT
- RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT
- RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-07-11 03:57:24 +02:00
Pablo de Lara
62303e435b cryptodev: remove queue start/stop functions
Removed cryptodev queue start/stop functions,
as they were marked deprecated in 18.05, since they
were not implemented by any driver.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-07-11 03:57:24 +02:00
Pablo de Lara
e1fc5b7690 cryptodev: remove max number of sessions parameter
Most crypto PMDs do not have a limitation
of the number of the sessions that can be handled
internally. The value that was set before was not
actually used at all, since the sessions are created
at the application level.
Therefore, this value is not parsed from the initial
crypto parameters anymore and it is set to 0,
meaning that there is no actual limit.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-07-11 03:57:24 +02:00
Pablo de Lara
25b05a1c80 crypto/mvsam: parse max number of sessions
The maximum number of sessions device argument will be removed,
as most PMDs do not have a limitation on this number.
Therefore, the MVSAM PMD needs to parse this value internally.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Tomasz Duszynski <tdu@semihalf.com>
2018-07-11 03:57:24 +02:00
Pablo de Lara
ee4a3aa404 cryptodev: remove max number of sessions per queue
The cryptodev info structure currently contains
the maximum number of sessions that can be used in a queue pair.
This is only set in DPAA_SEC PMD, and since it is calculated
based on the maximum number of sessions (which is not used
anymore), this field can be removed.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-07-11 00:57:51 +02:00
Pablo de Lara
a4493be5bd cryptodev: replace bus specific struct with generic dev
Structure rte_cryptodev_info has currently PCI device
information ("struct rte_pci_device") in it.

This information is not generic to all devices,
so this gets replaced with the generic "rte_device" structure,
compatible with all crypto devices.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2018-07-11 00:57:51 +02:00