Commit Graph

274 Commits

Author SHA1 Message Date
Warner Losh
421552a580 Provide a dummy NO_XBOX option that lives in opt_xbox.h for pc98.
This allows us to eliminate a three ifdef PC98 instances.
2005-11-14 00:43:44 +00:00
Yoshihiro Takahashi
1ba0023e33 Fix pc98 build. 2005-11-09 12:22:26 +00:00
Warner Losh
51ef421d92 Add support for XBOX to the FreeBSD port. The xbox architecture is
nearly identical to wintel/ia32, with a couple of tweaks.  Since it is
so similar to ia32, it is optionally added to a i386 kernel.  This
port is preliminary, but seems to work well.  Further improvements
will improve the interaction with syscons(4), port Linux nforce driver
and future versions of the xbox.

This supports the 64MB and 128MB boxes.  You'll need the most recent
CVS version of Cromwell (the Linux BIOS for the XBOX) to boot.

Rink will be maintaining this port, and is interested in feedback.
He's setup a website http://xbox-bsd.nl to report the latest
developments.

Any silly mistakes are my fault.

Submitted by: Rink P.W. Springer rink at stack dot nl and
	Ed Schouten ed at fxq dot nl
2005-11-09 03:55:40 +00:00
Peter Wemm
68a443c292 MFamd64: indent with tabs instead of spaces. 2005-11-04 22:53:44 +00:00
Bill Paul
8a3a26385c Undo the change to pci_cfgdisable() on i386 for now. It seems to fix
the amd64 case, but makes the i386 case fail even more often.
2005-10-25 05:32:44 +00:00
Bill Paul
ba3af76df7 Modify the pci_cfgdisable() routine to bring it more in line with
other OSes (Solaris, Linux, VxWorks). It's not necessary to write a 0
to the config address register when using config mechanism 1 to turn
off config access. In fact, it can be downright troublesome, since it
seems to confuse the PCI-PCI bridge in the AMD8111 chipset and cause
it to sporadically botch reads from some devices. This is the cause
of the missing USP ports problem I was experiencing with my Sun Opteron
system.

Also correct the case for mechanism 2: it's only necessary to write
a 0 to the ENABLE port.
2005-10-25 04:53:29 +00:00
Warner Losh
e429f92618 Expose legacy_pcib_alloc_resource, and use it in the mptable pci bus
implementation, like other routines in the legacy bus.

This should fix problems with resource allocation on MP systems without
ACPI enabled.
2005-09-17 23:57:53 +00:00
Warner Losh
dca2069084 Commit a workaround to a problem with resource allocation. This helps
with some Dell servers that booted w/o a problem[*] on 5.4, but failed
with 6.0-BETA.

On the PCI bus, when we do lazy resource allocation, we narrow the
range requested as we pass through bridges to reflect how the bridges
are programmed and what addresses they pass.  However, when we're
doing an allocation on a bus that's directly connected to a host
bridge, no such translation can take place.  We already had a fallback
range for memory requests, but none for ioports.  As such, provide a
fallback for I/O ports so we don't allocate location 0, which will
have undesired side effects when the resources are actually used.

This fixes a problem with booting a Dell server with usb in the
kernel.  However, it is an unsatisfying solution.  I don't like the
hard coded value, and I think we should start narrowing the resources
returned to not be in the so-called isa alias area (where the ranage &
0x0300 must be 0 iirc).  Doing such filtering will have to wait for
another day.

This may be a good 6 candidate, maybe after its had a chance to be
refined.

Tested by: glebius@
2005-09-16 07:02:29 +00:00
Warner Losh
b3ffa2ae22 Note that pc98 specific defines maybe would be better in a header file. 2005-09-08 17:07:12 +00:00
John Baldwin
11f3a4f069 - Ignore BIOS IRQs (that is, IRQ settings left by the BIOS or a previous OS
in the PCI config registers) that are > 15 as $PIR can only route PCI
  interrupts to ISA IRQs which are limited to the 0 to 15 range.
- Remove an extra word from a printf.

Reported by:	othermark atkin901 at yahoo dot com
MFC after:	3 days
2005-07-13 15:41:16 +00:00
John Baldwin
84c7fde72e Trust the settings programmed by the BIOS over what the $PIR says.
Specifically, if the BIOS has programmed an IRQ for a device that doesn't
match the list of valid IRQs for the link, use it anyway as some BIOSes
don't correctly list the valid IRQs in the $PIR.  Also, allow the user
to specify an IRQ that $PIR claims is invalid as an override, but emit a
warning in that case.
2005-04-14 18:25:09 +00:00
John Baldwin
5165a17df5 Add code to read the primary PCI bus number out of the Compaq/HP 6010
hotplug Host to PCI bridge.  This is only needed for the non-ACPI case
as the BIOS includes a proper _BBN method in ACPI.
2005-03-25 14:18:50 +00:00
Poul-Henning Kamp
c711aea6ca Make a bunch of malloc types static.
Found by:	src/tools/tools/kernxref
2005-02-10 12:02:37 +00:00
Warner Losh
86cb007f9f /* -> /*- for copyright notices, minor format tweaks as necessary 2005-01-06 22:18:23 +00:00
Scott Long
5662cf3c92 Remove a stray critical_exit().
Submitted by: johan
2004-12-13 07:08:44 +00:00
Scott Long
245e410ba7 Expand the scope of the critical section in the PCIe read and write methods
on the advice of Alan Cox.
2004-12-10 15:44:12 +00:00
Scott Long
568b7ee1b2 Due to a significant addition of code, add my copyright to this file. Also
note that the PCIe work was made possible due to hardware donations from
the FreeBSD Foundation and Intel.  Thanks!
2004-12-06 18:19:32 +00:00
Scott Long
aa2ea23220 Add support for the memory-mapped PCI Express configuration mechanism. This
actually is a property of the northbridge and applies to all PCI/PCI-X/PCIe
devices in the system, though only PCIe devices will respond to registers
higher than 256.  This uses per-CPU pools of temporary mappings so that
the whole 256MB of configuration space doesn't have to be mapped all at
once.  While the sf_buf API was considered for this, the fact that it
requires sleep locks and can return failure made it unsuitable for this use.

For now only the Intel Grantsdale and Lindenhurst (925 and 752x) chipsets are
supported.  Since there doesn't appear to be a compatible way to determine
northbridge support, new chipsets will have to be explicitely added in the
future.
2004-12-06 08:27:10 +00:00
Dag-Erling Smørgrav
b0e1e474f7 Add TUNABLE_LONG and TUNABLE_ULONG, and use the latter for the
hw.pci.host_mem_start tunable.  Add comments to TUNABLE_INT and
TUNABLE_QUAD recommending against their use.

MFC after:	3 weeks
2004-10-31 15:50:33 +00:00
Dag-Erling Smørgrav
38228f7221 Whitespace cleanup 2004-10-31 15:02:53 +00:00
Warner Losh
fd492ee0e6 Make the lower range of the memory area 0x80000000 again. Also
introduce hw.{pci,acpi}.host_mem_start tunable to change this.

MFC: ASAP
2004-10-11 21:10:23 +00:00
Warner Losh
e625cbacaf Add missing 'static' 2004-10-06 15:18:12 +00:00
Warner Losh
0b3a486f21 For legacy PCI bridges, limit memory allocation to the top 32MB of
RAM.  Many older, legacy bridges only allow allocation from this
range.  This only appies to devices who don't have their memory
assigned by the BIOS (since we allocate the ranges so assigned
exactly), so should have minimal impact.

Hoewver, for CardBus bridges (cbb), they rarely get the resources
allocated by the BIOS, and this patch helps them greatly.  Typically
the 'bad Vcc' messages are caused by this problem.
2004-10-06 07:22:58 +00:00
Stefan Farfeleder
5908d366fb Consistently use __inline instead of __inline__ as the former is an empty macro
in <sys/cdefs.h> for compilers without support for inline.
2004-07-04 16:11:03 +00:00
John Baldwin
39981fed82 Trim a few things from the dmesg output and stick them under bootverbose to
cut down on the clutter including PCI interrupt routing, MTRR, pcibios,
etc.

Discussed with:	USENIX Cabal
2004-07-01 07:46:29 +00:00
John Baldwin
092a5c4530 Remove atdevbase and replace it's remaining uses with direct references to
KERNBASE instead.
2004-06-10 20:31:00 +00:00
John Baldwin
4468ab0a61 Allow the pir0 device add to fail since pir0 may already exist. This should
fix the panics in device_set_ivars() that people were seeing on boxes with
multiple Host-PCI bridges but not using ACPI.
2004-06-01 19:51:29 +00:00
Poul-Henning Kamp
41ee9f1c69 Add some missing <sys/module.h> includes which are masked by the
one on death-row in <sys/kernel.h>
2004-05-30 17:57:46 +00:00
John Baldwin
7a64d8d74c - Create a pir0 psuedo device as a child of legacy0 if we attach a legacy
host-PCI bridge device and find a valid $PIR.
- Make pci_pir_parse() private to pci_pir.c and have pir0's attach routine
  call it instead of having legacy_pcib_attach() call it.
- Implement suspend/resume support for the $PIR by giving pir0 a resume
  method that calls the BIOS to reroute each link that was already routed
  before the machine was suspended.
- Dump the state of the routed flag in the links display code.
- If a link's IRQ is set by a tunable, then force that link to be re-routed
  the first time it is used.
- Move the 'Found $PIR' message under bootverbose as the pir0 description
  line lists the number of entries already.  The pir0 line also only shows
  up if we are actually using the $PIR which is a bonus.
- Use BUS_CONFIG_INTR() to ensure that any IRQs used by a PCI link are
  set to level/low trigger/polarity.
2004-05-04 21:17:52 +00:00
John Baldwin
be16306ad3 Make the legacy_pcib_attach() function static. 2004-05-03 14:49:43 +00:00
John Baldwin
86f4fd6f71 Don't call the BIOS to route a link that has already been routed by the
BIOS during POST as it apparently makes some machines unhappy.

Tested by:	mux
2004-04-16 18:54:05 +00:00
John Baldwin
ccab16610b Add back an include to fix the build for the CPU_ELAN case. 2004-02-19 18:34:26 +00:00
John Baldwin
77fa00fa7c Switch to using the new $PIR interrupt routing code and remove the old
code.  The pci_cfgreg.c file now just controls reading/writing PCI config
registers.
2004-02-18 22:41:53 +00:00
John Baldwin
2e41ba54d6 Rework the $PIR (aka PCIBIOS) PCI interrupt routing code and split it off
into its own file:
- All of the $PIR interrupt routing is now done in a link-centric fashion.
  When a host-PCI bridge that uses the $PIR attaches, it calls pir_parse()
  to parse the table.  This scans for link devices and merges all the masks
  for each link device from the table entries.  It then looks at the intline
  register of PCI devices connected to a link to figure out if the BIOS has
  routed this link and if so to which IRQ.
- The IRQ for any given link can be overridden via a hint like so:
  'hw.pci.link.0x62.irq=10'  Any IRQ set in this matter is treated as if it
  were set that way by the BIOS.
- We only call the BIOS to route each link device once.
- When a PCI device wants to route an interrupt, we look it up in the $PIR
  to find the associated link.  If the link is routed, we simply return the
  IRQ it is using.  If it is not routed, we have to pick one.  This uses a
  different algorithm from the old code.  First off, when we try to pick
  an interrupt from a mask of possible interrupts, we try to pick the one
  that is least loaded as far as PCI devices.  We maintain this weight based
  on the number of devices attached to each link device.  When choosing an
  IRQ, we first attempt to route using any PCI only interrupts (the old
  code did this as well).  If that doesn't work, we try to use the list of
  IRQs that the BIOS has used.  This is a new step that the new code didn't
  do and avoids using IRQ 3 or 4 for every virgin interrupt routing.  If
  none of the IRQs that the BIOS used worked, then we fall back to trying
  anything.
- The fallback mask for !PC98 was fixed to include IRQ 3 and not allow IRQ
  2.
- We don't use the $PIR to route interrupts on a PCI-PCI bridge unless it
  has already been used to route on at least one Host-PCI bridge.  This
  helps to avoid mixing and matching x86 firmware PCI interrupt routing
  methods (which is a Bad Thing(tm)).

Silence on:	current@
2004-02-18 22:40:23 +00:00
John Baldwin
21e25fa607 Replace an outb() during the test for configuration mechanism #1 with a
DELAY(1) instead.  After wading through old commit logs, I found that the
outb() was added not as part of the test but as an intentional delay. In
fact, according to Shanley's PCI book, the configuration 1 data and address
ports should only be accessed using aligned 32-bit accesses (i.e. inl()
and outl()).  Thus, using outb() to just the last byte of the port violates
the PCI spec it would seem.  On at least one box doing so broke the probe
for PCI, whereas changing it to a DELAY(1) fixed the probe.

Reported by:	Sean Welch <welchsm@earthlink.net>
MFC after:	1 week
2003-12-31 16:56:32 +00:00
John Baldwin
6f92bdd0c1 New APIC support code:
- The apic interrupt entry points have been rewritten so that each entry
  point can serve 32 different vectors.  When the entry is executed, it
  uses one of the 32-bit ISR registers to determine which vector in its
  assigned range was triggered.  Thus, the apic code can support 159
  different interrupt vectors with only 5 entry points.
- We now always to disable the local APIC to work around an errata in
  certain PPros and then re-enable it again if we decide to use the APICs
  to route interrupts.
- We no longer map IO APICs or local APICs using special page table
  entries.  Instead, we just use pmap_mapdev().  We also no longer
  export the virtual address of the local APIC as a global symbol to
  the rest of the system, but only in local_apic.c.  To aid this, the
  APIC ID of each CPU is exported as a per-CPU variable.
- Interrupt sources are provided for each intpin on each IO APIC.
  Currently, each source is given a unique interrupt vector meaning that
  PCI interrupts are not shared on most machines with an I/O APIC.
  That mapping for interrupt sources to interrupt vectors is up to the
  APIC enumerator driver however.
- We no longer probe to see if we need to use mixed mode to route IRQ 0,
  instead we always use mixed mode to route IRQ 0 for now.  This can be
  disabled via the 'NO_MIXED_MODE' kernel option.
- The npx(4) driver now always probes to see if a built-in FPU is present
  since this test can now be performed with the new APIC code.  However,
  an SMP kernel will panic if there is more than one CPU and a built-in
  FPU is not found.
- PCI interrupts are now properly routed when using APICs to route
  interrupts, so remove the hack to psuedo-route interrupts when the
  intpin register was read.
- The apic.h header was moved to apicreg.h and a new apicvar.h header
  that declares the APIs used by the new APIC code was added.
2003-11-03 21:53:38 +00:00
John Baldwin
221111f6f2 Lower the priority of the legacy host to pci bridge driver so that other
non-ACPI host-bridge drivers can preempt this driver.
2003-10-31 21:00:37 +00:00
Mike Silbersack
184dcdc7c8 Change all SYSCTLS which are readonly and have a related TUNABLE
from CTLFLAG_RD to CTLFLAG_RDTUN so that sysctl(8) can provide
more useful error messages.
2003-10-21 18:28:36 +00:00
John Baldwin
810cb9ef5e We represent PCI intpin's two different ways. One is the way that the
intpin register is expressed in hardware where 0 means none, 1 means INTA,
2 INTB, etc.  The other way is commonly used in loops where 0 means INTA,
1 means INTB, etc.  The matchpin argument to pci_cfgintr_search() is
supposed to be the first form, but we passsed in a loop index of the
second.  This fix adds one to the loop index to convert to the first form.

Reported by:	Pavlin Radoslavov <pavlin@icir.org>
2003-09-10 06:00:53 +00:00
John Baldwin
729d7ffbcf - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.
- Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds
  the header type.
- Replace several magic numbers with appropriate constants for the header
  type register and a couple of PCI_FUNCMAX.
- Merge to amd64 the fix to the i386 bridge code to skip devices with
  unknown header types.

Requested by:	imp (1, 2)
2003-08-28 21:22:25 +00:00
Warner Losh
19b7ffd1b8 Prefer new location of pci include files (which have only been in the
tree for two or more years now), except in a few places where there's
code to be compatible with older versions of FreeBSD.
2003-08-22 07:20:27 +00:00
Yoshihiro Takahashi
126ef7fcd6 PC98 uses different mask of IRQ. 2003-08-02 05:14:17 +00:00
Warner Losh
353adf7e7f The MI code was modified to filter the devices based on its header
type.  We know about header types 0, 1 and 2.  Ignore the rest in the
MD i386 code when we're looking for bridges.  You cannot look at the
vendor tag.  And if you don't you certainly can't look at function > 0
if the device isn't there.

The new soekris boards' GEODE cpu has issues with the old way.  This
is reported to have fixed it.

MFC After: 2 days
2003-08-01 21:50:09 +00:00
Warner Losh
e86bd39aab Add hw.pci.irq_override_mask, which is a mask of interrupts that are
considered to be good to try when it otherwise has no clue about which
interrupts to try.  This is a band-aide and we really should try to
balance the IRQs that we arbitrarily pick, but it should help some
people that would otherwise get bad IRQs.
2003-08-01 21:31:36 +00:00
John Baldwin
ba40a03417 - Rename nexus_pcib to legacy_pcib. I've been meaning to do this for a
while after the legacy device was added since this driver hangs from
  legacy and not nexus.
- Make several methods non-static so they can be reused in a mptable
  host -> pci bridge driver that will be added at a later date.
- Let legacy_pcib() use pcibios_pcib_route_interrupt() directly instead of
  wrapping it in a private function.  Originally, I thought I was going to
  have the nexus_pcib() driver make a runtime APIC vs. 8259A check and call
  the appropriate routing method (MPTable vs. PIR) that way, but it ended
  up being cleaner to make nexus_pcib() just work with PIR and have a
  separate host -> pci bridge driver for the mptable/apic case.
2003-06-06 17:56:30 +00:00
John Baldwin
cdd83b0ad1 Use the secondary bus number instead of the number of the bus the PCI-PCI
bridge lives on (i.e., the parent bus) when probing the PIR table for a
bus.  This could cause the PCIBIOS PCI-PCI bridge driver to bogusly attach
to bridges that weren't in the PIR but whose parent bus was in the PIR.
2003-06-06 17:27:18 +00:00
David E. O'Brien
71c5a90130 Use __FBSDID(). 2003-06-02 17:01:49 +00:00
Poul-Henning Kamp
d6b602d4b2 Remove unused variable.
Found by:       FlexeLint
2003-05-31 18:55:18 +00:00
Peter Wemm
af3d516f55 Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has been
#if'ed out for a while.  Complete the deed and tidy up some other bits.

We need to be able to call this stuff from outer edges of interrupt
handlers for devices that have the ISR bits in pci config space.  Making
the bios code mpsafe was just too hairy.  We had also stubbed it out some
time ago due to there simply being too much brokenness in too many systems.
This adds a leaf lock so that it is safe to use pci_read_config() and
pci_write_config() from interrupt handlers.  We still will use pcibios
to do interrupt routing if there is no acpi.. [yes, I tested this]

Briefly glanced at by:  imp
2003-02-18 03:36:49 +00:00
Poul-Henning Kamp
152e80d952 Outdent the string rather than use concatenation. 2002-12-23 22:12:17 +00:00
Warner Losh
a4bbd12ff1 MFp4:
o Fix small style nit.  This was supposed to be part of the last batch of
  style fixes, but somehow didn't get merged.
2002-11-14 05:22:37 +00:00
Peter Wemm
41f778bb99 Recognize the Serverworks CIOB30 host to pci bridge. 2002-11-13 21:30:44 +00:00
Warner Losh
ce494452fe MFp4:
o It turns out that we always need to try to route the interrupts for
  the case where the $PIR tells us there can be only one.  Some machines
  require this, while others fail when we try to do this (bogusly, imho).
  Since we have no apriori way of knowing which is which, we always try to
  do the routing and hope for the best if things fail.
o Add some additional comments that state the obvious, but amplify it in
  non-obvious ways (judging from the questions I've gotten).

This should un-break older laptops that still have to use PCIBIOS to route
interrupts.

Tested by: sam
2002-11-02 22:35:24 +00:00
Warner Losh
984de797ff Use 0xffffffff instead of -1 for id to compare against.
Use exact width types, since this is a MD file and won't be used elsewhere.
Fix a couple of resulting printf breakages

Bug found by: phk using Flexlint
2002-11-02 22:32:04 +00:00
Poul-Henning Kamp
7f30cdf366 Revert last commit, there actually was a -1 waaaaay down in pcireg_cfgread(). 2002-10-20 17:54:17 +00:00
Poul-Henning Kamp
a67ee49294 "id" is never going to be -1 when it is unsigned.
Spotted by:	FlexeLint
2002-10-20 17:21:43 +00:00
John Baldwin
a73f15c7a8 Use the global pcib devclass instead of our own static copy. 2002-10-16 18:38:35 +00:00
Warner Losh
ea5420299c o go ahead and route the interupt, even if it is supposedly unique.
there are some strange machines that seem to need this.
o delete bogus comment.
o don't use the the bios for read/writing config space.  They interact badly
  with SMP and being called from ISR.  This brings -current in line with
  -stable.

# make the latter #ifdef on USE_PCI_BIOS_FOR_READ_WRITE in case we
# need to go back in a hurry.
2002-10-07 05:15:05 +00:00
Mitsuru IWASAKI
2f00e60504 Add 2 Ids for new ServerWorks host to PCI bridge chipset.
These are still unknown name but these are working as well
as the other ServerWorks chipset.
Description strings should be corrected when the chipsets
are known.

MFC after:	1 week
2002-10-02 17:50:38 +00:00
Poul-Henning Kamp
cb8e433232 Don't call function in return() for a void function. 2002-09-28 17:36:29 +00:00
John Baldwin
b8581e0d56 Now that we only probe host-PCI bridges once, we no longer have to check to
see if we have been probed before by checking for a pciX bus device.
2002-09-23 18:14:31 +00:00
John Baldwin
8ff25e9763 Put verbose printf's in the PCI BIOS interrupt routing code under
if (bootverbose).
2002-09-23 18:13:42 +00:00
John Baldwin
2ab55f4392 Change the nexus_pcib driver (eventually to be renamed to legacy_pcib) to
hang off of the legacy driver instead of the nexus.
2002-09-23 15:52:30 +00:00
John Baldwin
fe4663379e Axe unused include. 2002-09-20 19:16:41 +00:00
John Baldwin
fefe985dc6 Make sure a $PIR table header has a valid length before accepting the table
as valid.

Submitted by:	Michal Mertl <mime@traveller.cz>
2002-09-09 18:24:35 +00:00
Poul-Henning Kamp
a0c422db00 #include "opt_bla.h" goes first says Bruce. 2002-09-09 08:44:52 +00:00
Poul-Henning Kamp
9339569236 Fix style(9) bugs.
Brucified by:	bde
2002-09-08 15:16:49 +00:00
John Baldwin
7bbb0b56e4 Add a subclass of the PCI-PCI bridge driver that uses the PCIBIOS to
route interrupts if the child bus is described in the PCIBIOS interrupt
routing table.  For child busses that are in the routing table, they do
not necessarily use a 'swizzle' on their pins on the parent bus to route
interrupts for child devices.  If the child bus is an embedded device then
the pins on the child devices can be (and usually are) directly connected
either to a PIC or to a Interrupt Router.  This fixes PCIBIOS interrupt
routing across PCI-PCI bridges for embedded devices.
2002-09-06 22:19:39 +00:00
John Baldwin
c3ba1376f5 Add a function pci_probe_route_table() that returns true if our PCI BIOS
supports interrupt routing and if the specified PCI bus is present in the
routing table.
2002-09-06 22:15:44 +00:00
John Baldwin
facfd6e8ed Dump the $PIR table if booting verbose. 2002-09-06 19:25:25 +00:00
John Baldwin
8ab96fd8d0 - Add a pci_cfgintr_valid() function to see if a given IRQ is a valid
IRQ for an entry in a PCIBIOS interrupt routing ($PIR) table.
- Change pci_cfgintr() to except the current IRQ of a device as a fourth
  argument and to use that IRQ for the device if it is valid.
- If an intpin entry in a $PIR entry has a link of 0, it means that that
  intpin isn't connected to anything that can trigger an interrupt.  Thus,
  test the link against 0 to find invalid entries in the table instead of
  implicitly relying on the irqs field to be zero.  In the machines I have
  looked at, intpin entries with a link of 0 often have the bits for all
  possible interrupts for PCI devices set.
2002-09-06 17:08:07 +00:00
John Baldwin
fbabd7bec2 Add support for printing out the contents of a PCI BIOS $PIR interrupt
routing table on the console.  Eventually it will be printed during
verbose boots.
2002-09-06 16:10:12 +00:00
John Baldwin
cea0a89545 Prefer the physical bus number of the PCI bus as the unit of the pciX
device created.
2002-09-06 16:09:07 +00:00
John Baldwin
5264a94f3f Test PCIbios.ventry against 0 to see if we found a PCIbios entry point,
not the 'entry' member.  The entry point is formed from both a base and
a relative entry point.  'entry' is that relative offset.  It is perfectly
valid to have an entry point with a relative offset of 0.  PCIbios.ventry
is the virtual address of the entry point that takes both 'base' and
'entry' into account, thus it is the proper variable to test to see if we
have an entry point or not.
2002-09-05 17:07:07 +00:00
Poul-Henning Kamp
bd8add3d61 Change the support for AMDs ElanSC520 CPU from being a device driver to
be
	options	CPU_ELAN
(NB: Soekris.com users!)

It is cleaner this way.  We still recognize the cpu on the host-pci bridge.
2002-09-04 19:43:22 +00:00
Poul-Henning Kamp
14a3a6ea0b Move a prototype to the least wrong place.
Suggested by:	bde
2002-08-02 18:45:43 +00:00
Warner Losh
e300f53ca2 style(9)ize the whole file
Approved in concept a long time ago by: msmith
2002-07-21 05:35:42 +00:00
Andrew Gallatin
f76ec8facd Add support for probing secondary buses on the ServerWorks Grand Champion
chipset used for P4-Xeon machines

PR: kern/38894
Tested-by: "Marc G. Fournier" <scrappy@hub.org>
Submitted-by: Mark Tinguely (partially)
2002-07-19 18:35:08 +00:00
Poul-Henning Kamp
61658cf6a1 Add initialization code for the AMD Elan sc520 which maps the MMCR
into KVM and sets the i8254 frequency to the correct value.
2002-07-18 12:56:54 +00:00
Poul-Henning Kamp
3ae87b7ec6 Add an entry for the AMD Elan SC520 hostbridge. I do not belive we can
identify this gadget on the CPUID result alone, so I intend to activate
the necessary magic (i8254 frequency for instance) for it based on the
precense of the on-chip host to PCI bridge.
2002-07-18 10:57:20 +00:00
Warner Losh
8ce1ab3a24 Use a common function to map the bogus intlines.
Don't require pin be non-zero before we map bogus intlines, always do it.
This fixes a number of problems on HP Omnibook computers.

Tested/Reviewed by: Brooks Davis
2002-06-01 05:14:11 +00:00
Brooks Davis
26722a1909 Restore the irq=0 => irq=255 hack to pci_cfgintr_search(). Just having
it in pci_cfgregread() wasn't sufficent on at least the HP Omnibook 500.

Reviewed by:	imp
2002-05-29 16:16:16 +00:00
Warner Losh
d5ccecfad7 o Work around bugs in the powerof2 macro: It thinks that 0 is a power of
2, but that's not the case.  This fixes the case where there were slots
  in the PIR table that had no bits set, but we assumed they did and used
  strange results as a result.
o Map invalid INTLINE registers to 255 in pci_cfgreg.c.  This should allow
  us to remove the bogus checks in MI code for non-255 values.

I put these changes out for review a while ago, but no one responded
to them, so into current they go.

This should help us work better on machines that don't route
interrupts in the traditional way.

MFC After: 4286 millifortnights
2002-04-24 15:30:11 +00:00
Warner Losh
e5d7e9c76c Fix a PNPID in a comment
Submitted by: David Xu
2002-04-24 15:22:53 +00:00
Nicolas Souchu
c17d43407f Major rework of the iicbus/smbus framework:
- VIA chipset SMBus controllers added
	- alpm driver updated
	- Support for dynamic modules added
	- bktr FreeBSD smbus updated but not tested
	- cleanup
2002-03-23 15:49:15 +00:00
Warner Losh
654d58ca24 Don't call the bios if the interrupt appaers to be already routed. Some
older PCI BIOSes hate this and this leads to panics when it is done.  Also,
assume that a uniquely routed interrupt is already routed.  This also
seems to help some older laptops with feable BIOSes cope.
2002-03-16 23:02:41 +00:00
Warner Losh
a8c18609ec The Libretto L series has no $PIR table, but does have a _PIR table.
This typo keeps us from properly routing an interrupt for CardBus
bridges on this machine.  So, now we look for $PIR and then _PIR to
cope.  With these changes, the Libretto L1 now works properly.
Evidentally, the idea comes from patch that the Japanese version of
RedHat (or against a Japanese version of Red Hat), but my Japanese
isn't good enough to to know for sure.

Reported by: Hiroyuki Aizu-san <eyes@navi.org>

# This may be an MFC candidate, but I'm not yet sure.
2002-01-20 03:28:29 +00:00
Murray Stokely
b0ae3ab3fe Add identification string for AMD-761 host to PCI bridge.
PR:	kern/32255
2001-12-10 09:27:00 +00:00
Warner Losh
1cf5f5552b MFS: I was confused. This code wasn't in -current after all.
Merge in the irq 0 detection.  Add comment about why.

If we have irq 0, ignore it like we do irq 255.  Some BIOS writers aren't
careful like they should be.
2001-11-26 21:25:03 +00:00
Warner Losh
d3b6477a19 It turns out that while Toshiba laptops don't want to route interrupts
multiple times, others do.  The last strategy, which was to assume
that already routed interrupts were good and just return them doesn't
work for some laptops.  So, instead, we have a new strategy: we notice
that we have an interrupt that's already routed.  We go ahead and try
to route it, none the less.  We will assume that it is correctly
routed, even if the route fails.  We still assume that other failures
in the bios32 call are because the interrupt is NOT routed.

Note: some laptops do not support the bios32 interface to PCI BIOS and
we need to call it via the INT 2A interface.  That is another windmill
to till at later.

Also correct a minor typo and minor whitespace nits.

Strong MFC candidate.
2001-08-28 16:35:01 +00:00
Warner Losh
d626906b0c MFS: IRQ ordering, PRVERB and more whining in pcibios_get_version on failure.
Check return value from bios32.

[[ Yes, I was bad and committed this to stable first.  I should have done
   the commit in the other order. ]]
2001-08-27 20:44:38 +00:00
Warner Losh
0b9427de88 The general conesnsus on irc was that pci bios for config registers
and such was just a bad idea and one that users should be forced to
enable if they want it.  This patch introduces a hw.pci.enable_pcibios
tunable for those people.  This does not impact the pcibios interrupt
routing at all.

Approved by: peter, msmith
2001-08-21 07:53:37 +00:00
Peter Wemm
573be82757 Detect a certain type of PCIBIOS brain damage. For some reason,
some bios vendors took it apon themselves to "censor" the
host->pci bridges from PCIBIOS callers, even when the caller
explicitly asks for them.  This includes certain Compaq machines
(eg: DL360) and some laptops.

If we detect this, shut down pcibios and revert to using IO
port bashing.

Under -current, apcica does a better job anyway.
2001-08-21 03:10:55 +00:00
Mike Smith
85fab96387 Un-swap irq/link byte values so that printf works. 2001-05-11 04:52:29 +00:00
Mike Smith
6c9eb5f3a6 Free the memory we get from devclass_get_devices and device_get_children.
Submitted by:	wpaul
2001-02-08 20:44:49 +00:00
Peter Wemm
47c6b72621 Fix a warning due to missing prototype. 2001-01-19 09:10:14 +00:00
Bosko Milekic
6a47d852b9 Remove declaration of airq variable from outer block. There were two
declarations of a variable of the same name. The one in the outer block
was unused and probably just slipped in at one point or another. This
silences a compiler warning.
2001-01-12 07:49:29 +00:00
Mike Smith
bb0d0a8efc Next phase in the PCI subsystem cleanup.
- Move PCI core code to dev/pci.
 - Split bridge code out into separate modules.
 - Remove the descriptive strings from the bridge drivers.  If you
   want to know what a device is, use pciconf.  Add support for
   broadly identifying devices based on class/subclass, and for
   parsing a preloaded device identification database so that if
   you want to waste the memory, you can identify *anything* we know
   about.
 - Remove machine-dependant code from the core PCI code.  APIC interrupt
   mapping is performed by shadowing the intline register in machine-
   dependant code.
 - Bring interrupt routing support to the Alpha
   (although many platforms don't yet support routing or mapping
   interrupts entirely correctly).  This resulted in spamming
   <sys/bus.h> into more places than it really should have gone.
 - Put sys/dev on the kernel/modules include path.  This avoids
   having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
Mike Smith
e9ca98b28f Hack to work around a probe which will lock up at least some i450GX-based
systems.

From the PR:

 When 'probe.slot' is PCI_SLOTMAX (== 31) and 'probe.func' is 7,
 call to 'pci_cfgread()' here and machine suddenly hangs up.
 I don't know why...  (or 450GX chipset's bug?)

PR:		i386/20379
Submitted by:	Masayuki FUKUI <fukui@sonic.nm.fujitsu.co.jp>
2000-11-08 11:25:15 +00:00
Mike Smith
099d058b54 Improve the PCI interrupt routing code. Now the process is as follows:
- Look for a hardwired interrupt in the routing table for this
   bus/device/pin (we already did this).
 - Look for another device with the same link byte which has a hardwired
   interrupt.
 - Look for a PCI device matching an entry with the same link byte
   which has already been assigned an interrupt, and use that.
 - Look for a routable interrupt listed in the "PCI only" interrupts
   field and use that.
 - Pick the first interrupt that's marked as routable and use that.
2000-11-02 00:37:45 +00:00