Commit Graph

986 Commits

Author SHA1 Message Date
Adrian Chadd
e875139a4f Fix ANI handling to work correctly when (trying) to receive radar errors.
* Teach the AR5212/AR5416 ANI code to use the RX filter methods, rather
  than calling the RX filter routines directly.

* Make HAL_ANI_PRESENT and HAL_ANI_MODE unconditionally available,
  regardless of whether ah_ani_function is masking it.

* (Mostly) fully disable ANI if interference mitigation is disabled.
  When disabled, the ANI code doesn't touch any ANI/PHY registers,
  leaving them the default value. This is in line with what the
  Atheros reference driver does.

* Correctly set the ANI parameters during ANI reset, rather than
  when ANI is enabled. In this way, if ANI is disabled or enabled
  whilst the NIC is not active (and there's no current channel),
  bogus parameters or a NULL pointer deference doesn't occur.

There's still some lingering issues - notably, the MIB events/interrupts
aren't fully disabled, so MIB interrupts still occur. I'll worry about
that later.

Approved by:	re (kib)
2011-07-30 13:30:24 +00:00
Adrian Chadd
f1ef788d6f Bring over AR5416 specific RX filter get/set routines.
This in particular fixes radar PHY handling - on the AR5212
NIC, one enables the AR_PHY_ERR_RADAR bit in AR_PHY_ERR;
the AR5416 and later also needs a bit set in AR_RX_FILTER.

A follow-up commit is needed to convert the AR5416 ANI code
to use this particular method, as it's currently using the
AR5212 methods directly.

Obtained from:	Atheros
Approved by:	re (kib)
2011-07-30 13:25:11 +00:00
Adrian Chadd
c86c3aa3d9 I noticed that the Merlin NICs I had (AR9220, AR9280) never completed
the ADC calibrations if the NIC is in 5ghz 11a or 5ghz HT/20 modes.
I've been told that the dual-ADC is only engaged in turbo/40mhz modes.

Since Sowl (AR9160) seems to return valid-looking calibration data
in 5ghz 20MHz modes, I'm only disabling it for Merlin for now.
It may turn out I can disable it for all chipsets and only enable
it for 40MHz modes.

Approved by:	re (kib)
2011-07-30 13:21:33 +00:00
Adrian Chadd
827660cf9a Fix the AR9280 initial AGC calibration code.
It looks like this was mixed up with the AR9285 calibration code.
This code is now more in line with what Linux ath9k and Atheros
reference drivers do.

Obtained from:	Atheros
Approved by:	re (kib)
2011-07-30 13:18:48 +00:00
Adrian Chadd
f9da901e77 Reset the NIC if ANI is enabled or disabled.
Although this may not be what the original sysctl was designed to do,
it feels a bit more "expected".

Before, if ANI is disabled, the initial ANI parameters are still written
to the hardware, even if they're not enabled. "ANI enabled" would then
adjust the noise immunity parameters dynamically. Disabling ANI would
simply leave the existing noise immunity parameters where they are,
and disable the dynamic part.

The problem is that disabling ANI doesn't leave the hardware in
a consistent, predictable state - so asking a user to disable ANI
wouldn't actually reset the NIC to a consistent set of PHY signal
detection parameters, resulting in an unpredictable/unreliable outcome.
This makes it difficult to get reliable debugging information from
the user.

Approved by:	re (kib)
2011-07-29 23:55:17 +00:00
Adrian Chadd
c5f2a23c79 Implement a basic radar parameter API in the dfs_null module.
Since no actual radar data is ever handled, this won't
do anything. It's mostly here as a reference for those who
wish to experiment with radar detection.

Approved by:	re (kib)
2011-07-22 09:39:49 +00:00
Adrian Chadd
f51c84eaf6 This links in the ath dfs ioctl into the driver and defines the
ioctl interface for DFS modules to use.

Since there's no open source dfs code yet, this doesn't introduce any
operational changes.

Approved by:	re (kib)
2011-07-21 14:25:12 +00:00
Adrian Chadd
09ac182ca5 Modify the radar API a little to be easier to "change" via run-time
tools.

* introduce pe_enabled, which (will) indicate whether the radar
  detection stuff is enabled or not. Right now it's incorrectly
  set, based on something previously written. I'll sort it out
  later.

* Don't set HAL_PHYERR_PARAM_ENABLE in pe_relstep to say whether
  radar detection is on.

* Return whether blockradar, fir128 and enmaxrssi is enabled.

* Change some of the phyerr params to be integers rather than
  HAL_BOOL so they can be set to the NOPARAM value when the
  setup function is called. This is in line with other radar
  parameters.

* Add new configuration parameters for fir128, blockradar and
  enmaxrssi, rather than defaulting to off, on and on respectively.

Approved by:	re (kib)
2011-07-21 14:16:42 +00:00
Adrian Chadd
64d6d2d3fc Break out the PLL setup into (mostly) per-chip methods, rather than
polluting the AR5416 code with later chipset support.

Note: ar9280InitPLL() supports Merlin (AR9280) and later (AR9285, AR9287.)

Submitted by:	ssgriffonuser@gmail.com
Approved by:	re (kib)
2011-07-21 08:35:10 +00:00
Adrian Chadd
e8e6035991 This re-enables HT40 channels for use when DFS is enabled.
These should be disabled for the AR5416 in hostap/mesh/ibss mode,
as the AR5416 doesn't have support for radar detection on the
ext channel of a HT40 setup. Later chips do.

Approved by:	re (kib)
2011-07-21 08:31:55 +00:00
Adrian Chadd
e2e849485f These two are ath_hal regulatory domain updates from the Atheros
reference driver.

* Australia should use FCC3_WORLD
* Add some new SKUs; these are just the EEPROM values and haven't been
  fully defined yet. As such they won't affect anything.

Obtained from:	Atheros
Approved by:	re (kib)
2011-07-20 12:46:58 +00:00
Adrian Chadd
1292e2e98a Add a missing check for the global ath_hal_debug.
This was removed accidentally when the per HAL instance
code was added, and not reverted when I added back the
global debug variable (for early chip setup debugging.)
2011-07-14 23:30:30 +00:00
Adrian Chadd
f52efb6d38 Fix a corner case in STA beacon processing when a CSA is received but
the AP doesn't transmit beacons.

If the AP requests a CSA (ie, a channel switch) and then enters CAC
(channel availability check) for 60 seconds, it doesn't send beacons
and it just listens for radar events (and other things which we don't
do yet.)

Now, ath_newstate() was not resetting the beacon timer config on
a transition to the RUN state when in STA mode - it was setting
sc_syncbeacon, which simply updates the beacon config from the
contents of the next received beacon.

This means the STA never generates beacon miss events.

If the AP goes into CAC for 60 seconds and recovers, the STA will
happily receive the first beacon and reconfigure timers.
But if it gets a radar event after that, it'll change channel
again, not notify the station that it's changed channel..
and since the station is happily waiting for the first beacon
to configure the beacon timer details from, it won't ever
generate a beacon miss interrupt and it'll sit there forever
(or until the AP appears on that channel once again.)

This change forces the last known beacon timer config to be
written to hardware on a transition from CSA->RUN in STA mode.
This forces bmiss events to occur and the STA will eventually
(after a handful of beacon miss events) begin scanning for
another access point.
2011-06-29 13:21:52 +00:00
Adrian Chadd
7d12b6e172 Make sure the extended regdomain word is initialised.
As with the AR9285, the AR9287 has a default word of 0x1F which means
all the various bits in that field are set on by default.
2011-06-28 00:01:55 +00:00
Adrian Chadd
2fd9aabb1b Fix beacon transmission after a channel set.
The DFS code was tickling the channel set directly whilst going
through the state RUN -> CSA -> RUN. This only changed the channel;
it didn't go via ath_reset(). However in this driver, a channel
change always causes a chip reset, which resets the beacon timer
configuration and interrupt setup. This meant that data would go
out but as the beacon timers never fired, beacons would never
be queued.

The confusing part is that sometimes the state transition was
RUN -> SCAN -> CAC -> RUN (with CSA being in there sometimes);
going via SCAN would clear sc_beacons and thus the transition
to RUN would reprogram beacon transmission.

In case someone tries debugging why suspending a device currently
beaconing (versus just RX'ing beacons which is what occurs in STA
mode), add a silly comment which should hopefully land them at
this commit message. The call to ath_hal_reset() will be clearing
the beacon config and it may not be always reset.
2011-06-26 13:53:24 +00:00
Adrian Chadd
10dc8de41b Add ATH_ENABLE_DFS which enables the DFS flag so the DFS code
can be tested.

This doesn't at all actually do radar detection! It's just
so developers who wish to test the net80211 DFS code can easily
do so. Without this flag, the DFS channels are never marked
DFS and thus the DFS stuff doesn't run.
2011-06-26 13:43:15 +00:00
Adrian Chadd
1a940429c7 Commit missing piece from a couple days ago - re-add ath_hal_debug. 2011-06-25 00:34:40 +00:00
Adrian Chadd
8fc0556a5e Small fix to bring the non-debug definitions of HALDEBUG/HALDEBUG_G in line
with the debug definitions.
2011-06-24 23:59:14 +00:00
Adrian Chadd
dc6ebb1bca add missing #define for the non-debug case. 2011-06-23 12:11:43 +00:00
Adrian Chadd
f6f1dfb66b Re-introduce a global ath_hal_debug again for now, whilst I figure out what
to do about the few cases where the HAL state isn't available (regdomain)
or isn't yet setup (probe/attach.)

The global ath_hal_debug now affects all instances of the HAL.

This also restores the ability for probe/attach debugging to work; as
the sysctl tree may not be attached at that point. Users can just set
the global "hw.ath.hal.debug" to a suitable value to enable probe/attach
related debugging.
2011-06-23 06:55:29 +00:00
Adrian Chadd
4c728c42f5 Fix indenting issues introduced by the previous commit. 2011-06-23 06:53:13 +00:00
Adrian Chadd
37931a3544 Break out most of the HAL related tweaks into a per-HAL instance,
rather than global variables.

This specifically allows for debugging to be enabled per-NIC, rather
than globally.

Since the ath driver doesn't know about AH_DEBUG, and to keep the ABI
consistent regardless of whether AH_DEBUG is enabled or not, enable the
debug parameter always but only conditionally compile in the debug
methods if needed.

The ALQ support is currently still global pending some brainstorming.

Submitted by:	ssgriffonuser@gmail.com
Reviewed by:	adrian, bschmidt
2011-06-23 02:38:36 +00:00
Adrian Chadd
76170c392d Fix ath_ahb(4) bus attach and eeprom error handling.
Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
2011-06-13 04:31:57 +00:00
Adrian Chadd
e484e92770 Since HAL_PHYERR_* is used in the radar code, always include ah_desc.h. 2011-06-07 14:00:47 +00:00
Adrian Chadd
3d423111f6 Flesh out a new HAL method to fetch the radar PHY error frame information.
For the AR5211/AR5212, this is apparently a one byte pulse duration
counter value. It is only coded up here for the AR5212 as I don't have
any AR5211-series hardware to test it on.

This information was extracted from the Madwifi DFS branch along with
some local additions.

Please note - all this does is extract out the radar event duration,
it in no way reflects the presence of a radar. Further code is needed
to take a set of radar events and filter them to extract out correct
radar pulse trains (and ignore other events.)

For further information, please see:

http://wiki.freebsd.org/dev/ath_hal%284%29/RadarDetection

This includes references to the relevant patents which describe what
is going on.

Obtained from:	Madwifi
2011-06-07 09:03:28 +00:00
Adrian Chadd
373815ef7b Add a missing call to sync the DMAed buffer before the radar event data is extracted. 2011-06-05 03:33:46 +00:00
Adrian Chadd
6025dd9f0a Commit radar detection changes missed by my previous commit. 2011-06-04 08:24:58 +00:00
Adrian Chadd
7e5eb44d14 A few changes to make radar detection implementable in a hal_dfs/
module.

* If sc->sc_dodfs is set to 1 by the ath_dfs_radar_enable(),
  set the relevant rx filter bit to begin receiving radar PHY
  errors. The HAL code already knows how to set the relevant
  error mask register to enable radar events.

* Add a missing call to ath_dfs_radar_enable() after ath_hal_reset()

* change ath_dfs_process_phyerr() to take a const char *buf for now,
  rather than a descriptor. This way it can get access to the packet
  buffer contents.
2011-06-04 04:14:59 +00:00
Adrian Chadd
04d172db03 Bring over the relevant registers to use when implementing the quiet time
portion of 802.11h.

The AR5212 code has been brought over as a reference, it's currently
untested.

Obtained from:	Atheros
2011-06-03 07:27:53 +00:00
Adrian Chadd
48237774e4 Flesh out the radar detection related operations for the ath driver.
This is in no way a complete DFS/radar detection implementation!
It merely creates an abstracted interface which allows for future
development of the DFS radar detection code.

Note: Net80211 already handles the bulk of the DFS machinery,
all we need to do here is figure out that a radar event has occured
and inform it as such. It then drives the DFS state engine for us.

The "null" DFS radar detection module is included by default;
it doesn't require a device line.

This commit:

* Adds a simple abstracted layer for radar detection state -
  sys/dev/ath/ath_dfs/;
* Implements a null DFS module which doesn't do anything;
  (ie, implements the exact behaviour at the moment);
* Adds hooks to the ath driver to process received radar events
  and gives the DFS module a chance to determine whether
  a radar has been detected.

Obtained from:	Atheros
2011-06-01 20:09:49 +00:00
Adrian Chadd
2cb5233b43 Add some missing DFS chipset functionality to the FreeBSD HAL.
Please note - this doesn't in any way constitute a full DFS
implementation, it merely adds the relevant capability bits and
radar detection threshold register access.

The particulars:

* Add new capability bits outlining what the DFS capabilities
  are of the various chipsets.
* Add HAL methods to set and get the radar related register values.
* Add AR5212 and AR5416+ DFS radar related register value
  routines.
* Add a missing HAL phy error code that's related to radar event
  processing.
* Add HAL_PHYERR_PARAM, a data type that encapsulates the radar
  register values.

The AR5212 routines are just for completeness. The AR5416 routines
are a super-set of those; I may later on do a drive-by pass to
tidy up duplicate code.

Obtained from:	Linux, Atheros
2011-06-01 20:01:02 +00:00
Adrian Chadd
6246be6e58 Enable setting the short-GI bit when TX'ing HT rates but only if the
hardware supports it.

Since ni->ni_htcap in hostap mode is what the remote end has advertised,
not what has been negotiated/decided, we need to check ourselves what
the current channel width is and what the hardware supports before
enabling short-GI.

It's important that short-GI isn't enabled when it isn't negotiated
and when the hardware doesn't support it (ie, short-gi for 20mhz channels
on any chip < AR9287.)

I've quickly verified this on the AR9285 in 11n mode.
2011-05-30 15:06:57 +00:00
Adrian Chadd
9be25f4a3a Set default A-MPDU density/size. 2011-05-30 14:57:00 +00:00
Adrian Chadd
76355edba5 Teach if_ath about devices which have short-GI in 20MHz channel modes.
This has been disabled until now because there hasn't been any supported
device which has this feature. Since the AR9287 is the first device to
support it, and since now the HAL has functional AR9287+11n support,
flip this on.
2011-05-29 00:17:13 +00:00
Adrian Chadd
133cf74b7e Fix AR9287 operation when >1 TX chain is enabled.
I didn't pick this up with the initial commit because I was only testing
with 11bg.
2011-05-28 15:43:56 +00:00
Adrian Chadd
8d01245e7e Fix a macro name - it's currently unused in this file however, but
keep it consistent with ar9280.c.
2011-05-26 20:22:10 +00:00
Adrian Chadd
a3906079d2 Revert this erroneous commit and re-disable the AR9285 combined antenna
diversity.
2011-05-26 20:17:59 +00:00
Adrian Chadd
0c50156f91 Remove the three-chain scaled power check for the AR9287 - it isn't
needed.
2011-05-26 16:59:42 +00:00
Adrian Chadd
1ecf8ddf5a Make sure only two chains are calibrated for the AR9287. 2011-05-26 16:55:44 +00:00
Adrian Chadd
fe5237edef Add some open-loop TX power debugging for AR9287. 2011-05-26 16:52:37 +00:00
Adrian Chadd
f1285519e2 Bring over the AR5416 per-rate TX power code, modified to use the
AR9287 EEPROM layout.

The AR9287 only supports 2ghz, so I've removed the 5ghz code (but left
the 5ghz edge flags in there for now) and hard-coded the 2ghz-only
path.

Whilst I'm there, fix a typo (ar9285->ar9287.)

This meets basic TX throughput testing - iperf TX tests == 27-28mbit in 11g,
matching the rest of my 11g kit.
2011-05-26 15:55:27 +00:00
Adrian Chadd
ea18ed263e Flesh out ar9287SetTransmitPower() based on the AR9285 routine.
Hard-code the per-rate TX power at 5dBm for now so testing can be done.

This passes initial TX testing in 11g mode (but, obviously, at 5dBm.)
2011-05-26 15:01:37 +00:00
Adrian Chadd
4551052dbe Flesh out the TX power calibration for the AR9287.
I'm assuming for now that the AR9287 is only open-loop TX power control
(as mine is) so I've hard-coded the attach path to fail if the NIC is
not open-loop.

This greatly simplifies the TX calibration path and the amount of code
which needs to be ported over.

This still isn't complete - the rate calculation code still needs to be
ported and it all needs to be glued together.

Obtained from:	Linux ath9k
2011-05-26 14:29:05 +00:00
Adrian Chadd
90759dbed6 Add the AR9287 chip identification string. 2011-05-26 09:27:58 +00:00
Adrian Chadd
8143e16401 Fix a bad merge from a previous commit. 2011-05-26 09:22:59 +00:00
Adrian Chadd
0293774898 Merlin -> Kiwi 2011-05-26 09:16:09 +00:00
Adrian Chadd
d8daa2e3f6 Bring over my AR9287 work in progress.
It isn't linked into the build because it's missing the TX power
and PDADC programming code.

This code is mostly based on the ath9k codebase, compared against
the Atheros codebase as appropriate.

What's implemented:

* probe/attach
* EEPROM board value programming
* RX initial calibration
* radio channel programming
* general MAC / baseband setup
* async fifo setup
* open-loop tx power calibration

What's missing before it can be enabled by default:

* TX power / calibration setting code
* closed-loop tx power calibration routines
* TSF2 handling
* generic timer support from ath9k

Obtained from:	Atheros, ath9k
2011-05-26 09:15:33 +00:00
Adrian Chadd
b3096aee0b AR9287 prep work:
* Add PCI/PCIE devids
* Add AR9287/Kiwi version check macros
* AR_SREV_9287 -> AR_SREV_KIWI

Obtained from:	Atheros, ath9k
2011-05-26 08:35:47 +00:00
Adrian Chadd
a1cf3a877a Add temp sense to the EEPROM variable list;
Export the temperature sense variables to ah_eeprom_9287.c
2011-05-26 08:20:14 +00:00
Adrian Chadd
727edca45b The current ANI capability information uses a different set of
values for the commands, compared to the internal command values
(HAL_ANI_CMD.)

My eventual aim is to make the HAL_ANI_CMD internal enum match
the public API and then remove all this messiness.

This now allows HAL_CAP_INTMIT users to use a public HAL_CAP_INTMIT_
enum rather than magic constants.

The only magic constants currently used by if_ath are "enable" and
"present". Some local tools of mine allow for direct, manual fiddling
of the ANI variables and I'll convert these to use the public enum API
before I commit them.
2011-05-25 07:34:49 +00:00
Adrian Chadd
241d9a3400 Tidy up the ANI API in preparation for looking to expose some more
of the ANI statistics and committing some tools which use these.

* Change HAL_ANI_* commands _back_ to be numerical, rather than a
  bitmap;
* modify access to the ANI control bitmap to convert a command to
  a bitmap;
* Fix the ANI noise immunity fiddling for CCK errors - it wasn't
  checking whether noise immunity was disabled or not.
2011-05-25 07:19:19 +00:00
Adrian Chadd
9f4563363b The ANI control for the AR5416 and later chips was calling ar5212AniControl(),
which did AR5212 specific initialisation. This would cause some slight
silliness when enabling/disabling ANI.

Just to be completely correct - and to ensure the phy error mask/RX filter
register isn't incorrectly played with - make the ANI control function a
method, have it set appropriately for AR5212/AR5416, and call that from the
ANI control interface.
2011-05-24 18:25:40 +00:00
Adrian Chadd
634be0a971 Use the new per-series antenna and TPC definitions when setting ctl8->11.
This should hopefully make it clearer to developers what is going on
and when TPC is being hacked on, make it obvious why it isn't working for
series 1, 2, 3.

I won't flip on setting TX power for TX series 1, 2, 3 until I've done
some further testing with Kite to ensure it doesn't break anything.
(Before people ask - yes, TPC is only needed for 5ghz regdomains and
yes, Kite is a 2.4ghz only chip, but there are potential use cases
for 2ghz TPC. I just need to sit down and ensure it's supported and
functional.)
2011-05-24 05:49:02 +00:00
Adrian Chadd
e808ca4454 Add in descriptions for TX descriptor fields ctl8-11 - these fields
control the antenna control bits for the four TX series and the
TPC settings for TX series 1, 2, 3.

The specifics:

* The TPC setting for TX series 0 is handled in ctl0.

* TPC is currently disabled, so the per-packet TX power is
  set via the global per-rate TX power register, not per packet.

* The antenna control bits don't matter for AR5416 and later
  so they should stay 0 (which they currently do); they may
  be set for Kite but as there's no TX diversity supported
  at the moment (it requires the NIC to be built with an
  external antenna switch, matching how antenna diversity
  is done on legacy NICs), so again keep them 0.

This is in preparation for supporting per-rate TPC on the
AR5416 and later. The Kite (and soon to come Kiwi) code
sets ctl8-11 to 0x0, which doesn't have any effect at
the moment. When TPC is enabled it would result in the
second, third and fourth TX series attmpts to be done with
a TX power of 0. This commit doesn't change that; it'll
be followed up with some commits to properly set the TPC
registers appropriately.
2011-05-24 05:34:45 +00:00
Adrian Chadd
cd50bf427a The Merlin analog register bank is from 0x7800 -> 0x78fc; fix the code
to reflect this.
2011-05-21 09:23:18 +00:00
Adrian Chadd
db18c342da This isn't needed any longer, it's defined in ah_internal.h. 2011-05-18 11:28:23 +00:00
Adrian Chadd
369589482c Modify the sample rate control algorithm to only select/sample HT
rates for HT nodes.
2011-05-18 07:20:30 +00:00
Adrian Chadd
6c63a20b49 Fix the debugging code path to correctly support HAL_DEBUG_UNMASKABLE. 2011-05-17 16:30:34 +00:00
Adrian Chadd
fdc2e66c57 Fix case, introduced in my previous commit.
Pointy hat goes to:	adrian, for having multiple build screens
			open and checking the wrong one.
2011-05-17 15:03:39 +00:00
Adrian Chadd
655a610236 Use the halMcastKeySrchSupport capability bit to selectively enable/disable
the multicast key search support for AR5212, AR5416 and later.

The general HAL routine ath_hal_getcapability() implement checking this
but it's overridden by a check in ar5212_misc:ar5212GetCapability().
This restores the later functionality in case it's found to be broken
in any of the 11n chipsets.
2011-05-17 11:56:50 +00:00
Adrian Chadd
90de864a5e Set this HAL capabilities flag correctly even though it isn't currently
being used.
2011-05-17 11:52:53 +00:00
Adrian Chadd
e9d1191f6a * Add some more TX descriptor error counters; this'll be helpful when
implementing TX aggregation
* Whilst I'm there, comment some RX error counters
2011-05-15 15:54:34 +00:00
Adrian Chadd
0148401a3f Fix NF calibration breakage introduced by me in a past commit.
Since the returned NF will be -ve, checking for <= 0 is not good
enough. For now, check whether it equals 0 or -1; a future commit
will tidy this mess up and have it return HAL_BOOL instead.
2011-05-15 07:59:33 +00:00
Adrian Chadd
acc8122719 Fix the Merlin 5ghz fast-clock EEPROM fetch to return the correct value.
The eeprom Get method should return HAL_OK if fastclock is enabled in the
EEPROM. It was returning the opposite of what it should have.

Submitted by:	Matthew Fleming <mdf356@gmail.com>
2011-05-14 15:24:15 +00:00
Adrian Chadd
92ffeb633d Fix the eeprom set API method to return HAL_STATUS.
The code assumed it could return HAL_OK, HAL_EINVAL and other
HAL_STATUS types; so it shouldn't be declared as returning HAL_BOOL.

This commit was brought to you by the Clang compiler.

Submitted by:	Matthew Fleming <mdf356@gmail.com>
2011-05-14 15:12:02 +00:00
Adrian Chadd
047d6827d0 Import initial EEPROM code for Kite (AR9287).
I've tested this locally and it does indeed read and attach to an AR9287
EEPROM. But a lot more code needs to be ported over to the HAL before
the AR9287 is functional.

I'm importing this separate from the rest of the codebase (and unlinked from
the build for now) in case someone wishes to begin fiddling with porting
the rest of the code over from Linux ath9k.

Obtained from:	Linux ath9k
2011-05-14 14:25:15 +00:00
Adrian Chadd
d6415a7cf6 When disabling RIFS for Sowl (AR9160) and Howl (AR9130), make sure RIFS
is totally disabled.

The Atheros HAL code does this for Sowl/Howl but not for Owl (AR5416) where
RIFS is disabled by default.

This seems to quieten the occasional baseband hang I've been seeing with
the AR9160 in STA mode under constant heavy traffic load.

Obtained from:	Atheros
2011-05-14 05:43:33 +00:00
Adrian Chadd
b357d5767b Major fix: when doing open-loop TX power calibration, adjust
the correct CCK rates rather than adjusting the first handful.
This may have affected some AR9280 based NICs.

Minor fix: merlin check update
2011-05-14 04:17:16 +00:00
Adrian Chadd
98cdd90425 Fixes from the Atheros HAL - formatting; update Merlin checks to be consistent.
Nothing functional should change with this commit.
2011-05-14 04:05:23 +00:00
Attilio Rao
4b547324c0 Disconnect sun4v architecture from the three.
Some files keep the SUN4V tags as a code reference, for the future,
if any rewamped sun4v support wants to be added again.

Reviewed by:	marius
Tested by:	sbruno
Approved by:	re
2011-05-14 01:53:38 +00:00
Adrian Chadd
307abf289d Even though initial calibrations aren't done (yet), add this so we're
consistent with the Atheros HAL.
2011-05-14 01:41:36 +00:00
Adrian Chadd
4342b6100b Only do open loop power control and temperature compensation
for the AR9280 based NICs if it's actually enabled.

Some of the OLC code was erroneously called during setup
and calibration. This may have caused some incorrect behaviour.
2011-05-13 14:33:45 +00:00
Adrian Chadd
2f399d37ee Remove duplicate code - add a function which calculates the ratesArray[]
table which contains the per-rate target TX power.

This code is shared between the v14 eeprom board setup (AR5416, AR9160,
AR9280) and will also be used by the upcoming Kite (AR9287) support.
2011-05-13 10:36:38 +00:00
Adrian Chadd
68b3f39d74 Some diversity changes relating to AR9285.
* grab the main, alt and selected LNA config
* add some optional / disabled logging code
* add a check to reject packets with an invalid main rssi too,
  in case the alt is the active receive chain and main is -ve.

Note: The software-controlled combined diversity code is still disabled.
2011-05-13 09:57:12 +00:00
Adrian Chadd
dce0bcca8a Now that the devices with functioning ps-poll hardware support have
been enumerated (merlin and later), flick this on.
2011-05-12 14:03:29 +00:00
Adrian Chadd
4b5404a9de Break out the AR9285 analog registers from ar5416/ar5416phy.h and put
them in a new header file, ar9002/ar9285_an.h.

Shuffle the AR9280 analog registers in ar5416/ar541phy.h into a contiguous
spot.
2011-05-12 10:11:24 +00:00
Adrian Chadd
003df2a90f Fix the half/quater rate PLL setup for AR5416, AR9160 and
(beta?) AR9280 chips.

Note: This doesn't "fix" half/quarter rate support for these
chips; it merely fixes an oversight.

Obtained from:	Atheros
2011-05-12 03:25:24 +00:00
Adrian Chadd
8a90965b83 Fixes from Atheros:
* If AR9130, give the chip extra time to reset
* If AR5416, don't shutdown the chip during reset
2011-05-12 03:15:21 +00:00
Adrian Chadd
6b00c928cb Make the NF calibration logic (hopefully!) more resistive to noisy
environments.

In setups where NF calibration can take a while, don't load the CCA
and kick off a new NF calibration if the previous one hasn't yet
completed. This shouldn't happen unless the environment is noisy but
those exist (hi phk!).

Here, if the previous NF hasn't completed when ar5416LoadNf() is run
(which reads the NF), it skips updating the history buffer, loading
the NF CCA array and kicking off the next NF cal. It's hoped it'll
occur in the next long calibration interval.

Obtained from:	Atheros, ath9k, my local HAL
2011-05-11 13:40:13 +00:00
Adrian Chadd
fd331bf9bb Always log if the NF CCA load fails; so users with debugging enabled
can see they're likely in a very noisy environment.
2011-05-11 13:25:43 +00:00
Adrian Chadd
7a8796d17d Make sure the chip is awake before writing to it to finally detach
it.

Obtained from:	Atheros
2011-05-11 13:24:17 +00:00
Adrian Chadd
46dde1e6fa Add a new flag - HAL_DEBUG_UNMASKABLE - which always logs a debug message
(when debug is enabled) no matter what.
2011-05-11 13:22:41 +00:00
Adrian Chadd
5645b9a093 Remove unused variable 2011-05-11 13:20:25 +00:00
Adrian Chadd
85191ae6e8 Remove the initial NF completion check.
This is taking quite a while for some people in some situations
(eg AR5418 in phk's Abusive Radio Environment).

Instead, the rest of the calibration related code should
ensure that a NF calibration has occured before reading NF
values and kicking off another NF calibration.

The channel should also likely be marked as "noisy" (CWINT)
if the NF calibration takes too long.
2011-05-11 11:02:20 +00:00
Adrian Chadd
37fb34b48b Remove a now unneeded comment.. 2011-05-11 10:30:31 +00:00
Adrian Chadd
c454afe290 Restore the RSSI threshold after writing the board values.
This would be overwritten by the board initvals written in ah->writeIni().
2011-05-11 09:47:48 +00:00
Adrian Chadd
12c5d1f2bf AR9285 (Kite) fixes.
* Correct some of the silicon revision checks to match what
  the Atheros HAL does. (See [1] below.)

* Move the PA cal and init cal method assignment to -after-
  the mac version/revision IDs are stored. The AR9285 init
  cal was never being called.

* Enable ANI.

Note Kite 1.0 and 1.1 were prototypes that shouldn't be seen
in the wild. Linux ath9k simply removed the prototype code from
their codebase. I'm going to leave it in there for now but
make it conditionally compilable in the future.

Obtained from:	Atheros
2011-05-10 04:32:27 +00:00
Adrian Chadd
352dbd822c Disable diversity combining support until I can get a firm answer
from Atheros as to what/when this is supposed to be enabled.

Using the default RX fast diversity settings seems to help quite
a bit.

Whilst I'm here, change the prototype to return HAL_BOOL rather than int.
2011-05-09 17:30:25 +00:00
Adrian Chadd
48d813ef34 Fix a regression I introduced - only swap analog chains if the RX chainmask
is 0x5.
2011-05-09 17:10:48 +00:00
Adrian Chadd
e8def8942a Disable TX STBC - it isn't used for now, but it isn't supported on Kite. 2011-05-09 16:49:40 +00:00
Adrian Chadd
60abf57fd5 Import some initial Kite fixed diversity code from Atheros.
For now, the diversity settings are controlled by 'txantenna',
-not- rxantenna. This is because the earlier chipsets had
controllable TX diversity; the RX antenna setting twiddles
the default antenna register. I'll try sort that stuff out at
some point.

Call the antenna switch function from the board setup function
so scans, channel changes, mode changes, etc don't set the
diversity back to a default state too far from what's intended.

Things to todo:

* Squirrel away the last antenna diversity/combining parameters
  and restore them during board setup if HAL_ANT_VARIABLE is
  defined. That way scans, etc don't reset the diversity settings.

* Add some more public facing statistics, rather than what's
  simply logged under HAL_DEBUG_DIVERSITY.

For now, the fixed antenna settings behave better than variable
settings for me. I have some further fiddling to do..

Obtained from:	Atheros
2011-05-09 15:19:49 +00:00
Adrian Chadd
b4d225808d Remove an un-needed PA cal call here. 2011-05-09 14:04:49 +00:00
Adrian Chadd
c9cd76313b Fix the 5ghz fast clock logic.
The macro which I incorrectly copied into ah_internal.h assumed
that it'd be called with an AR_SREV_MERLIN_20() check to ensure
it was only enabled for Merlin (AR9280) silicon revision 2.0 or
later.

Trouble is, the 5GHz fast clock EEPROM flag is only valid for
EEPROM revision 16 or greater; it's assumed to be enabled
by default for Merlin rev >= 2.0. This meant it'd be incorrectly
set for AR5416 and AR9160 in 5GHz mode.

This would have affected non-default clock timings such as SIFS,
ACK and slot time. The incorrect slot time was very likely wrong
for 5ghz mode.
2011-05-08 15:55:52 +00:00
Adrian Chadd
aa66982300 * Add AR_SREV_KITE macro for later use
* Modify AR_SREV_MERLIN_20() to match the Atheros/Linux ath9k behaviour -
  its supposed to match Merlin 2.0 and later Merlin chips.
  AR_SREV_MERLIN_20_OR_LATER() matches AR9280 2.0 and later chips
  (AR9285, AR9287, etc.)
2011-05-08 15:25:22 +00:00
Adrian Chadd
f678fb43eb These EEPROM bits actually defined whether HT/20 and HT/40 support
for the given channel is available.

It isn't used yet; ar5416GetWirelessModes() needs to be taught
about this rather than assuming HT20/HT40 is available.
2011-05-08 08:18:30 +00:00
Adrian Chadd
5c892e7497 Fiddle with the PLL initialisation order to match ath9k/Atheros HAL.
This seems to make the AR9160 behave better during heavy scanning,
where before it'd hang and require a hard reset to recover.

Obtained From:	Linux ath9k, Atheros
2011-05-08 07:21:09 +00:00
Adrian Chadd
351384c64f Properly indent the WAR code i pasted in from ath9k a few months
ago.
2011-05-08 05:45:06 +00:00
Adrian Chadd
60d3878423 * Add in a comment about ar5416InitUserSettings() potentially
modifying AR_DIAG_SW.

  There's a hardware workaround which sets disabling some errors
  early at startup and clears said bits before the PCU begins
  receiving - it does this to avoid RX descriptor status errors.

  It's possible these bits aren't being completely properly twiddled
  in all instances; but in particular if the diag_reg HAL variable
  is set it won't be setting these bits correctly. I'll review this
  at some point.

 * Disable multicast search on mac address and key id - the driver
   doesn't use it at the moment and thus adhoc may be broken for
   merlin and later.

* Change this to be for Merlin 1.0 (which from what I understand
  wasn't ever publicly released) to be more correct.
2011-05-08 05:25:42 +00:00
Adrian Chadd
5accb5fd53 Fiddle with the AR5416 1.0 chainmask setup.
Apparently all three RX chains need to be enabled before initial calibration
is done, even if only two are configured.

Reorder the alt chain swap bit to match what the Atheros HAL is doing.

Obtained From:	ath9k, Atheros
2011-05-08 03:24:17 +00:00
Adrian Chadd
af8223ba6d Fix the IS_5416 checks to actually work correctly.
I've verified that my AR5416 revision 2.2 (minor revision 0x0A) now
matches the correct checks.
2011-05-07 18:42:41 +00:00
Adrian Chadd
26e8415d1d Do a HAL capabilities sync pass based on the Atheros HAL.
* Shuffle some of the capability numbers around to match the
  Atheros HAL capability IDs, just for consistency.

* Add some new capabilities to FreeBSD from the Atheros
  HAL which will be be shortly used when new chipsets are added
  (HAL SGI-20 support is for Kiwi/AR9287 support); for
  TX aggregation (MBSSID aggregate support, WDS aggregation
  support); CST/GTT support for carrier sense/TX timeout.
2011-05-07 15:30:23 +00:00
Adrian Chadd
b657b11d8d Update the ext channel cycpwr threshold 1 register for the extension
channel when the channel is HT/40.

The new ANI code (primarily for the AR9300/AR9400) in ath9k sets this
register but the ANI code for the previous 11n chips didn't set this.

Unlike ath9k, only set this for HT/40 channels.

Obtained From:	ath9k
2011-05-07 13:08:48 +00:00
Adrian Chadd
f93ef5516b Read in the extended regulatory domain flags so future code can use them.
These describe FCC/Japan channel and DFS behaviour.

The AR9285 and later chips don't set these bits in the eeprom, the correct
behaviour is to just assume all five bits are enabled.
2011-05-07 11:05:16 +00:00
Adrian Chadd
001ac28926 Instead of returning an unknown mac/bb signature, just return 0. 2011-05-07 06:52:04 +00:00
Adrian Chadd
b810285f24 Add some comments about which HAL capabilities are currently FreeBSD
specific.

The Atheros HAL and FreeBSD HAL share the same capabilities up
until HAL_CAP_11D, where things begin to diverge.

I'll look at tidying these up soon.

Obtained from:	Atheros
2011-05-07 06:47:09 +00:00
Adrian Chadd
de1334e8d7 Some BB hang changes:
* Add Howl (ar9130) to the list of chips that have DFS/BB/MAC hangs
* Don't treat unknown BB hangs as fatal; ath9k/Atheros HAL don't
  treat it as such.
* Add HAL_DEBUG_DFS to the debug fields in ath_hal/ah_debug.h

The BB hang check simply loops over an observation register checking
for a stuck state engine, but it can happen under high traffic
conditions. Ath9k and the Atheros HAL simply log a debug message and
continue.

Private to FreeBSD:

* Add HAL_DEBUG_HANG to the debug fields
* Change the hang debugging to HAL_DEBUG_HANG rather than HAL_DEBUG_DFS
  like in the Atheros HAL.

Obtained from:	Atheros
2011-05-07 06:45:35 +00:00
Adrian Chadd
ef1901a3c9 Change AR_SREV_OWL_{X}_OR_LATER to AR_SREV_5416_{X}_OR_LATER.
For now, these are equivalent macros. AR_SREV_OWL{X}_OR_LATER
will later change to exclude Howl (AR9130) in line with what
the Atheros HAL does.

This should not functionally change anything.

Obtained from:	Atheros
2011-05-07 02:59:24 +00:00
Adrian Chadd
d1915e7308 Fix the OWL revision checks.
A quick story, which is partially documented in the commit.

The silicon revision in Linux ath9k and the Atheros HAL use an
AR_SREV_REVISION mask of 0x07.

FreeBSD's HAL uses the AR5212 AR_SREV_REVISION mask of 0x0F.

Thus the OWL silicon revisions were coming through as 0xA, 0xB,
0xC, rather than 0x0, 0x1 and 0x2.

My ath9k-sourced AR_SREV_OWL_<X> macros were thus using the wrong
silicon revision values and wouldn't correctly match.

This commit does a few things:

* Change the AR_SREV_OWL_<x> macros to use the AR_SREV_REVISION_OWL_*
  values, not AR_XSREV_REVISION_OWL macros;
* Disable AR_XSREV_REVISION_OWL_* values;
* Modify the IS_5416 to properly check the MAC is OWL, rather than
  potentially matching on non-OWL revisions (which shouldn't happen
  unless there's a silicon revision of higher than 0x9 in a later
  chip..)
* Add a couple more macros from the Atheros HAL for compatibility.

The main difference now is that the Atheros HAL defines
AR_SREV_OWL_{20,22}_OR_LATER subtly differently - it fails on all HOWL
silicon. The AR_SREV_5416_*_OR_LATER macros match on the relevant OWL
version -and- all HOWL versions, along with subsequent versions.

A subsequent commit is going to migrate the uses of AR_SREV_OWL_X_OR_LATER
to AR_SREV_5416_X_OR_LATER to match what's going on in the Atheros HAL.

There's only two uses of AR_SREV_OWL_X_OR_LATER which currently don't
apply to FreeBSD but it may do in the future.

Yes, it's all confusing!
2011-05-07 02:54:52 +00:00
Adrian Chadd
e7cb5d548d Add a function which enables or disables RX RIFS searching, and migrate
the code which does this into it.
2011-05-06 15:33:56 +00:00
Adrian Chadd
47ff47a858 Don't perform NF calibration for radio chains which aren't in use:
Quoting the ath9k commit message:

At present the noise floor calibration is processed in supported
control and extension chains rather than required chains.
Unnccesarily doing nfcal in all supported chains leads to
invalid nf readings on extn chains and these invalid values
got updated into history buffer. While loading those values
from history buffer is moving the chip to deaf state.

This issue was observed in AR9002/AR9003 chips while doing
associate/dissociate in HT40 mode and interface up/down
in iterative manner. After some iterations, the chip was moved
to deaf state. Somehow the pci devices are recovered by poll work
after chip reset. Raading the nf values in all supported extension chains
when the hw is not yet configured in HT40 mode results invalid values.

Reference:	https://patchwork.kernel.org/patch/753862/

Obtained from:	Linux ath9k
2011-05-05 08:11:22 +00:00
Adrian Chadd
ed8659ed69 Another Howl (AR9130) fix.
I haven't seen a 5ghz AR9130 based board yet though!

Obtained from:	Atheros
2011-05-05 04:43:05 +00:00
Adrian Chadd
d2615832bf Fix up the chipset checks for the AR5416 and later silicon.
The checks should function as follows:

* AR_SREV_<silicon> : check macVersion matches that version id
* AR_SREV_<silicon>_<revision> : check macVersion and macRevision match
    the version / revision respectively

* AR_SREV_<silicon>_<revision>_OR_LATER: check that
  + if the chip silicon version == macVersion, enforce revision >= macRevision
  + if the chip silicon version > macVersion, allow it.

For example, AR_SREV_MERLIN() only matches AR9280 (any revision),
AR_SREV_MERLIN_10() would only match AR9280 version 1.0, but
AR_SREV_MERLIN_20_OR_LATER() matches AR9280 version >= 2.0 _AND_
any subsequent MAC (So AR9285, AR9287, etc.)

The specific fixes which may impact users:

* if there is Merlin hardware > revision 2.0, it'll now be correctly
  matched by AR_SREV_MERLIN_20_OR_LATER() - the older code simply
  would match on either Merlin 2.0 or a subsequent MAC (AR9285, AR9287, etc.)

* Kite version 1.1/1.2 should now correctly match. As these macros
  are used in the AR9285 reset/attach path, and it's assumed that the
  hardware is kite anyway, the behaviour shouldn't change. It'll only
  change if these macros are used in other codepaths shared with
  older silicon.

Obtained from:	Linux ath9k, Atheros
2011-05-05 03:42:04 +00:00
Adrian Chadd
59298273a9 Import some HOWL (AR9130) related fixes from Atheros.
Obtained from:	Atheros
2011-05-05 02:59:31 +00:00
Adrian Chadd
5a04ce2fdf Remove this useless bit of code for Kite. The RIFS register value is overriden
by the initvals, so disabling RIFS before calling writeIni() effectively does
nothing.
2011-05-04 09:26:33 +00:00
Adrian Chadd
e57539af23 Cosmetic changes to fit 80 character screen width. 2011-04-29 16:43:30 +00:00
Adrian Chadd
1422779793 Remove some holdovers from the AR5212 origin of this code.
These aren't relevant here.
2011-04-29 12:52:18 +00:00
Adrian Chadd
9f25ad52ce Introduce AR9130 (HOWL) WMAC support to the FreeBSD HAL.
The AR9130 is an AR9160/AR5416 family WMAC which is glued directly
to the AR913x SoC peripheral bus (APB) rather than via a PCI/PCIe
bridge.

The specifics:

* A new build option is required to use the AR9130 - AH_SUPPORT_AR9130.
  This is needed due to the different location the RTC registers live
  with this chip; hopefully this will be undone in the future.
  This does currently mean that enabling this option will break non-AR9130
  builds, so don't enable it unless you're specifically building an image
  for the AR913x SoC.

* Add the new probe, attach, EEPROM and PLL methods specific to Howl.

* Add a work-around to ah_eeprom_v14.c which disables some of the checks
  for endian-ness and magic in the EEPROM image if an eepromdata block
  is provided. This'll be fixed at a later stage by porting the ath9k
  probe code and making sure it doesn't break in other setups (which
  my previous attempt at this did.)

* Sprinkle Howl modifications throughput the interrupt path - it doesn't
  implement the SYNC interrupt registers, so ignore those.

* Sprinkle Howl chip powerup/down throughout the reset path; the RTC methods
  were

* Sprinkle some other Howl workarounds in the reset path.

* Hard-code an alternative setup for the AR_CFG register for Howl, that
  sets up things suitable for Big-Endian MIPS (which is the only platform
  this chip is glued to.)

This has been tested on the AR913x based TP-Link WR-1043nd mode, in
legacy, HT/20 and HT/40 modes.

Caveats:

* 2ghz has only been tested. I've not seen any 5ghz radios glued to this
  chipset so I can't test it.

* AR5416_INTERRUPT_MITIGATION is not supported on the AR9130. At least,
  it isn't implemented in ath9k. Please don't enable this.

* This hasn't been tested in MBSS mode or in RX/TX block-aggregation mode.
2011-04-28 12:47:40 +00:00
Adrian Chadd
041df70857 Wrap the MIMO stuff in #ifdef AH_SUPPORT_AR5416, as the channel
state doesn't have MIMO stuff in it by default.
2011-04-25 15:51:49 +00:00
Adrian Chadd
c2442d279a Break out the PLL setup into an overridable method.
The only method right now is ar5416InitPLL() which handles multiple
chipsets; this can now be overridden by newer chipset HAL code.
2011-04-24 15:53:57 +00:00
Adrian Chadd
98ebd982c3 Use the refactored ar5416WriteTxPowerRateRegisters() call in the ar9285 code. 2011-04-24 15:48:07 +00:00
Adrian Chadd
b998ae6409 Eliminate code duplication between AR5416/AR9160/AR9280 and AR9285.
Writing the TX power registers is the same between all of these chips
and later NICs (AR9287, AR9271 USB, etc.) so this will reduce code
duplication when those NICs are added to the HAL.
2011-04-24 14:50:29 +00:00
Adrian Chadd
6f5fe81e02 Fix a corner-case of interrupt handling which resulted in potentially
spurious (and fatal) interrupt errors.

One user reported seeing this:

Apr 22 18:04:24 ceres kernel: ar5416GetPendingInterrupts: fatal error,
  ISR_RAC 0x0 SYNC_CAUSE 0x2000

SYNC_CAUSE of 0x2000 is AR_INTR_SYNC_LOCAL_TIMEOUT which is a bus timeout;
this shouldn't cause HAL_INT_FATAL to be set.

After checking out ath9k, ath9k_ar9002_hw_get_isr() clears (*masked)
before continuing, regardless of whether any bits in the ISR registers
are set. So if AR_INTR_SYNC_CAUSE is set to something that isn't
treated as fatal, and AR_ISR isn't read or is read and is 0, then
(*masked) wouldn't be cleared. Thus any of the existing bits set
that were passed in would be preserved in the output.

The caller in if_ath - ath_intr() - wasn't setting the masked value
to 0 before calling ath_hal_getisr(), so anything that was present
in that uninitialised variable would be preserved in the case above
of AR_ISR=0, AR_INTR_SYNC_CAUSE != 0; and if the HAL_INT_FATAL bit
was set, a fatal condition would be interpreted and the chip was
reset.

This patch does the following:

* ath_intr() - set masked to 0 before calling ath_hal_getisr();
* ar5416GetPendingInterrupts() - clear (*masked) before processing
  continues; so if the interrupt source is AR_INTR_SYNC_CAUSE
  and it isn't fatal, the hardware isn't reset via returning
  HAL_INT_FATAL.

This doesn't fix any underlying errors which trigger
AR_INTR_SYNC_LOCAL_TIMEOUT - which is a bus timeout of some
sort - so that likely should be further investigated.
2011-04-23 06:37:09 +00:00
Adrian Chadd
0d07bcba27 Fix the merlin LNA configuration code - these are bit flags, not raw values to be
written into the registers.
2011-04-22 17:57:13 +00:00
Adrian Chadd
635636ea69 The second regdomain word is a set of bitflags describing
regulatory domain behaviour. Document what the v14 EEPROM
flags are.
2011-04-22 10:59:20 +00:00
Adrian Chadd
0d2dd30cbd Bring over a pdadc calibration fix from ath9k - unused power detector
gain values should be 58, not the previous values.

Obtained From:	linux ath9k
2011-04-22 10:57:46 +00:00
Adrian Chadd
3788ebed54 For now, only enable GTT. CST is firing very frequently during local tests;
I'll figure out what's going on before re-enabling this as it does add
to the interrupt load.
2011-04-18 14:14:54 +00:00
Adrian Chadd
5594f5c066 Add TX carrier sense timeout statistics. 2011-04-18 14:06:18 +00:00
Adrian Chadd
abc8309448 Bump pad, I'm adding more statistics. 2011-04-18 14:03:37 +00:00
Adrian Chadd
d0a0ebc6c3 Rework the Global TX timeout handling to look more like ath9k.
It correctly now sets the AR_IMR BCNMISC register, along with
the GTT register in AR_IMR_S2.
2011-04-18 14:03:05 +00:00
Adrian Chadd
6ad02dbafe Add global TX timeout handling.
The global TX timeout counter increments whenever a frame is ready
to be transmitted and the medium is busy.
2011-04-18 12:15:43 +00:00
Adrian Chadd
d10f1cdc8c Mark the PHY as inactive before the chip is reset.
It's also marked inactive by the initvals, and enabled after
the baseband/PLL has been configured, but before the RF
registers have been programmed.

The origin and reason for this particular change is currently unknown.

Obtained from:	Linux ath9k
2011-04-17 13:46:13 +00:00
Adrian Chadd
b39c47d922 Don't do Kite antenna switch selection this way (for now); antenna
diversity is done elsewhere now.
2011-04-16 13:47:17 +00:00
Adrian Chadd
52d84465a2 Disable classic-style fast diversity on the AR5416 and later.
Antenna diversity on the >= AR5416 is implemented differently than the
AR5212 and previous chips. So for now, and not to confuse things, just
disable it for now.
2011-04-16 12:46:46 +00:00
Adrian Chadd
18a3a3309f Remove some duplicate code from the AR9285 TX power configuration path. 2011-04-16 11:59:37 +00:00
Adrian Chadd
235ab70e0a Add in the AR9285 (Kite) diversity to if_ath, enabling TX/RX antenna
diversity.

This is bit dirty and likely should be revised at a later date,
with an eye to unifying/tidying up the whole diversity setup
and allowing developers to do "tricky stuff" as they desire.
For now, this works.
2011-04-13 15:17:23 +00:00
Adrian Chadd
81484cdb07 Add in the last bit of the HAL support for Kite diversity.
* add a new method, specifically for doing per-RX packet
  antenna diversity
* set that HAL method only if it's Kite and a Kite chip that
  does diversity.
2011-04-13 15:12:48 +00:00
Adrian Chadd
1171c869d7 More kite diversity related changes.
* add a diversity flag to the HAL debugging section
* add a check to make sure the kite diversity code doesn't run
  on boards that don't require it, as not all Kite chips will
  implement it.
* add some debug statements when the diversity code makes
  changes to the antenna diversity/combining setup.
2011-04-13 15:08:51 +00:00
Adrian Chadd
ac27b8ff27 Change this to be less noisy. 2011-04-13 14:51:07 +00:00
Adrian Chadd
77823fbc2c Bring over the antenna diversity logic support for Kite.
Again, this is just the code ported from ath9k and included in the build,
it isn't yet enabled.
2011-04-13 11:32:15 +00:00
Adrian Chadd
c772d0204f Port over a TX gain fix from ath9k specific to the AR9285 (Kite) and AR9271.
Note: this HAL currently only supports the AR9285.

From Linux ath9k:

The problem is that when the attenuation is increased,
the rate will start to drop from MCS7 -> MCS6, and finally
will see MCS1 -> CCK_11Mbps. When the rate is changed b/w
CCK and OFDM, it will use register desired_scale to calculate
how much tx gain need to change.

The output power with the same tx gain for CCK and OFDM modulated
signals are different. This difference is constant for AR9280
but not AR9285/AR9271. It has different PA architecture
a constant. So it should be calibrated against this PA
characteristic.

The driver has to read the calibrated values from EEPROM and set
the tx power registers accordingly.
2011-04-13 04:40:59 +00:00
Adrian Chadd
6984989598 Add new fields to the v4k EEPROM modal header. 2011-04-13 03:05:42 +00:00
Adrian Chadd
132163b12f Add OS_REG_RMW, which mirrors ath9k's REG_RMW.
This macro does a read-modify-write pass with register bits to set and clear.
2011-04-13 03:05:15 +00:00
Adrian Chadd
1c554472de Add the initial AR9285 PHY glue for supporting antenna diversity.
This code isn't currently used anywhere; it's just linked into the build.
2011-04-13 02:40:45 +00:00
Adrian Chadd
a03467b1ba De-dup the ar5416 rates array definition. 2011-04-11 11:15:34 +00:00
Adrian Chadd
7ab2ab919c Fix the completely wrong types I used in the previous commit. 2011-04-08 08:49:50 +00:00
Adrian Chadd
82c30dc46e Begin fleshing out a public HAL routine to export the per-chain
ctl/ext noise floor values.

This routine doesn't check to see whether the radio is MIMO
capable - instead, it simply returns either the raw values,
the "nominal" values if the raw values aren't yet available
or are invalid, or '0' values if there's no valid channel/
no valid MIMO values.

Callers are expected to verify the radio is a MIMO radio
(which for now means it's an 11n chipset, there are non-11n
MIMO chipsets out there but I don't think we support them,
at least in MIMO mode) before exporting the MIMO values.
2011-04-08 07:44:00 +00:00
Adrian Chadd
f1ff114882 Export the per-chain ctl/ext noise floor values, raw and uncut, to the
upper-level HAL.

Right now the per-chain noise floor values aren't used anywhere in
the upper-level HAL, so the driver currently has no real reference
to compare the per-chain RSSI values to.

This is needed before per-chain RSSI values (for ctl and ext radios)
are can be thrown upstairs to the net80211 code.
2011-04-08 06:58:01 +00:00
Adrian Chadd
8cc7d3572f Extend the RX descriptor block to include two more EVM words.
This will be needed for later AR93xx/AR94xx 3-stream devices.
2011-04-08 06:29:41 +00:00
Adrian Chadd
5e7d0e6482 Add some more OS_MARK probes to the RX DMA setup/teardown code path.
I'm trying to debug the RX DMA path and help the ath9k guys with
"RX dma abort stuck" issue that both our drivers have.
2011-04-07 13:14:51 +00:00
Adrian Chadd
c5d5272355 Make the alq log path tunable 2011-04-05 16:14:54 +00:00
Adrian Chadd
74e3a02137 The xpaBiasLvlFreq[] fields in the modal header also need swapping
when the EEPROM contents are byte-swapped.
2011-04-05 13:14:17 +00:00
Adrian Chadd
9e9ae8e207 Commit missing bits from the last commit:
* add the hal capability flag
* make sure its disabled for the ar9280/ar9285.
2011-04-04 14:53:36 +00:00
Adrian Chadd
8a2a6beedb Add a HAL capability bit for supporting self-linked RX descriptors and disable it for the 11n chipsets.
From the ath9k source:

==

11N: we can no longer afford to self link the last descriptor.
MAC acknowledges BA status as long as it copies frames to host
buffer (or rx fifo). This can incorrectly acknowledge packets
to a sender if last desc is self-linked.

==

Since this is useful for pre-AR5416 chips that communicate PHY errors
via error frames rather than by on-chip counters, leave the support
in there, but disable it for AR5416 and later.
2011-04-04 14:52:31 +00:00
Adrian Chadd
efa7c2b36c At least set the coverage class value here; worry about populating the
register values at a later date.
2011-04-04 11:01:53 +00:00
Adrian Chadd
f90a170c46 I missed committing this last time - it's needed for the 5ghz fast clock calculation. 2011-04-03 20:15:41 +00:00
Adrian Chadd
97efbf40fc Add in the clock timing calculation when Merlin is using the 5ghz fast clock.
This is a 44mhz clock, not a 40mhz clock like normal for 5ghz operation.
2011-04-03 17:36:32 +00:00
Adrian Chadd
c55968698f Import a fix from the ath9k - reduce the TX FIFO size for Kite (AR9285.) 2011-04-03 12:02:49 +00:00
Adrian Chadd
3d45fa543f Add an explanation of the inivals 2011-04-03 11:59:52 +00:00
Adrian Chadd
634a6d0283 From ath9k - clear the RX descriptor status before recycling it. 2011-04-02 00:27:22 +00:00
Adrian Chadd
5d51c507d0 Add some more debugging 2011-04-02 00:24:13 +00:00
Adrian Chadd
b569f9f5df Introduce AH_AR5416_INTERRUPT_MITIGATION which enables interrupt mitigation for
the AR5416 and later. Rename the older HAL option to use this.
2011-03-31 08:48:05 +00:00
Adrian Chadd
dba9c85977 Break out the ath PCI logic into a separate device/module.
Introduce the AHB glue for Atheros embedded systems. Right now it's
hard-coded for the AR9130 chip whose support isn't yet in this HAL;
it'll be added in a subsequent commit.

Kernel configuration files now need both 'ath' and 'ath_pci' devices; both
modules need to be loaded for the ath device to work.
2011-03-31 08:07:13 +00:00
Adrian Chadd
f77057db08 According to ath9k recv.c, one shouldn't be doing self-linked descriptors
in the RX path when doing 11n and block-ack'ed frames. Apparently, the MAC
will loop over that self-linked descriptor and treat it as "good enough"
for (incorrectly!) ACKing the frames in the block-ack.

Until I figure out how to work around this issue in the future, this counter
will tell me if packet RX processing ever gets to the point where it's
touching the self-linked descriptor. If there's ever enough packets to get
to that point, BA's will be invalid and likely very unhappy.
2011-03-29 15:59:07 +00:00
Adrian Chadd
4f545a2c3d Add in HT protection but disable it by default.
I'll clear how it's supposed to work with Bernhard and then look
at enabling this in the correct situations.

But this -does- enable HT RTS protection (using the appropriate legacy
rates) if this bit of code is enabled.
2011-03-28 11:48:49 +00:00
Adrian Chadd
4aa18e9d93 Fix typo. 2011-03-27 10:35:39 +00:00
Adrian Chadd
8fd67f92b0 Rename AH_ENABLE_11N to ATH_ENABLE_11 - the HAL supports 11n by
default but the ath driver doesn't. This is a much more consistent
name.
2011-03-27 08:47:55 +00:00
Adrian Chadd
bb16aa8120 .. And another missed commit - add the PSPOLL capability. 2011-03-26 13:06:43 +00:00
Adrian Chadd
d2211b6a68 This was missing from the previous HAL commit - it fixes a typo and
introduces the PS-POLL hardware support.
2011-03-26 11:59:18 +00:00
Adrian Chadd
a74f5bf40c If 802.11n is enabled, bump the number of buffers used up to a larger
level.

This is important for AMPDU RX as each burst is multiple packets in a row.
2011-03-26 11:58:29 +00:00
Adrian Chadd
f378d4c804 Add in the hardware PS-POLL frame reception setting, but leave it disabled
by default.

Adventourous souls with an AR9220/AR9280 or later and who have a device
that sends PS-POLL frames may wish to try tinkering with this option and
get back to me.
2011-03-26 10:52:37 +00:00
Adrian Chadd
a0e1036046 Introduce hardware PS-POLL support in the HAL.
Linux ath9k only enables this for AR9280 and later NICs; so
create a capability for it so it isn't enabled for earlier
NICs.

Enabling hardware PS-POLL support will come in a later commit
and will be disabled by default.
2011-03-26 10:47:17 +00:00
Adrian Chadd
f95233b6f5 Put these two back to mirror what ath9k does.
Even though they map to setting the error filter register,
ath9k also writes them untouched to AR_RX_FILTER.

The Force-BSSID match bit can stay high, as it maps to a
misc mode register setting rather than an RX filter bit.
2011-03-26 07:29:48 +00:00
Adrian Chadd
8c98d9bae1 Shuffle around the HAL_RX_FILTER bits to be slightly more sensible.
The phyerr, radar and bssid-match bits aren't real bits, they map
to enabling bits in other registers. Move those out of the way of
valid RX filter bits.

Add a few new fields from ath9k - compba, ps-poll, mcast-bcast-all.
2011-03-26 07:15:35 +00:00
Adrian Chadd
532f24429c After discussing with Bernhard, the "right" way in net80211 to check
the channel width is ni->ni_chw, which is set to the negotiated channel
width. ni->ni_htflags is the capability, rather than the negotiated
value.

Teach both the TX path and the sample rate module about this.
2011-03-25 10:55:25 +00:00
Adrian Chadd
75f0fbfbbf I broke periodic adc calibrations - so restore them to working order. 2011-03-25 10:53:13 +00:00
Adrian Chadd
ab2e5836be Re-disable the setting of 2040/shortgi bits for now.
This seems to work fine for STA but not HT/20 AP mode.

Further discussion with net80211 people will need to take place
to ensure that the right flags are set based on the negotiated
capabilities of the remote peer, rather than whatever the local
parameters are.

Sending short-gi frames in 20mhz may work on some chips but
it certainly isn't supported on anything currently supported
by the HAL; and sending HT40 frames in HT20 mode just plain
won't work.
2011-03-25 04:15:30 +00:00
Adrian Chadd
7dd51df82f After discussion with Felix Fietkau (nbd) about the ath9k Merlin LNA bit
settings, it seems that our defines are backwards and don't match what
is in the EEPROM documentation or internal driver.

The ath9k code used to have a bitfield here, rather than a uint8_t, and
there were #defines used to swap the order based on the endian of the
platform - this wasn't because of nybble or bit ordering of the
underlying host but because of what the compiler was doing.

This may be the reason for the backwards field numbers, as ath9k had
similar issues.
2011-03-25 00:45:24 +00:00
Adrian Chadd
423c974c28 Flip ANI on for the AR5416 and later chips. I haven't verified it on
the AR9285 so I'll leave it off for that.

Ath9k sources indiciate that one of the ANI modes interferes with
RIFS detection, so match ath9k and disable that.
2011-03-25 00:40:08 +00:00
Adrian Chadd
24cfde2fc3 The right commit - add a couple more AR_PCU_MISC_MODE2 register bits -
SOWL specific.
2011-03-25 00:06:58 +00:00
Adrian Chadd
30fa312b45 oops, commited the wrong file change. 2011-03-25 00:06:19 +00:00
Adrian Chadd
c2a1d035e6 Add some more AR_PCU_MISC_MODE2 register settings - these are SOWL or later. 2011-03-25 00:05:26 +00:00
Adrian Chadd
6893df4146 Bring over interrupt mitigation changes from ath9k.
* The existing interrupt mitigation code didn't mitigate anything - the
  per-packet TX/RX interrupts are still occuring. It's possible this
  worked for the AR5416 but not any later chipsets; I'll investigate and
  update as needed.

* Set both the RX and TX threshold registers whilst I'm at it.

This is verified to work on the AR9220 and AR9160. I'm leaving it off
by default in case it's truely broken, but I need to have it enabled
when doing 11n testing or interrupt loads exceed 10,000 interrupts/sec.
2011-03-25 00:03:21 +00:00
Adrian Chadd
7b83029b7b Flip back HT/40 and Short-GI (for 40mhz operation). These are now verified to work. 2011-03-24 16:06:54 +00:00
Adrian Chadd
646640c5f4 Fix a completely wrong variable reference. 2011-03-24 04:57:35 +00:00
Adrian Chadd
ef58d1e0b8 Make the ar2133ForceBias() call controllable at runtime.
At least one AR5416 user has reported measurable throughput drops
with this option. For now, disable it and make it a run-time
twiddle. It won't take affect until the next radio programming
trip though (eg channel scan, channel change.)
2011-03-23 23:48:44 +00:00
Adrian Chadd
d4c081e362 The AR5416+ chips all have MIB counters (which the AR5416 ANI code assumes)
so there's no need to enable the RX of invalid frames just to do ANI.

The if_ath code and AR5212 ANI code setup the RX filter bits to enable
receiving OFDM/CCK errors if the device doesn't have the hardware
MIB counters. It isn't initialising it for the AR5416+ because all of
those chips have hardware MIB counters.

This fixes the odd (and performance affecting!) situation where if ani
is enabled (via sysctl dev.ath.X.intmit) then suddenly there's be a very
large volume of phy errors - which is good to track, but not what was
intended. Since each PHY error is a received (0 length) frame, it can
significantly tie up the RX side of things.
2011-03-23 03:58:55 +00:00
Adrian Chadd
6aa113fd36 Enable setting the MCS rate bit for ast_tx_rate.
This allows ath_stats to print the MCS rate when TX'ing.
2011-03-22 22:59:09 +00:00
Adrian Chadd
1198947acd Clean up setting the short preamble bit in the rate - this way it
is very obvious (and cleanly so) that it occurs for non-11n rates.
2011-03-22 13:39:00 +00:00
Adrian Chadd
27ab76d69c Flip this over to be a configurable option for people who wish to play with it.
It's still not ready for prime-time - there's some TX niggles with these 11n
cards that I'm still trying to wrap my head around, and AMPDU-TX is just not
implemented so things will come to a crashing halt if you're not careful.
2011-03-22 13:35:56 +00:00
Adrian Chadd
44a3316e1f This isn't actually needed any longer, A-MPDU frames work fine if only tagged for 11n nodes. 2011-03-22 13:20:11 +00:00
Adrian Chadd
f6f59583bf Bring over an XPA (external power amplifer) bias fix for the AR9160.
This fix modifies the const addac initval array, rather than modifying
a local copy. It means that running >1 AR9160 on a board may prove to
be unpredictable.

The AR5416 init path also does something similar, so supporting
>1 AR5416 of different revisions could cause problems.

The later fix will be to create a private copy of the Addac data
for the AR5416, AR9160 (and AR9100 when it's merged in) and then
modify that as needed.

Obtained From:	Linux ath9k
2011-03-22 10:29:36 +00:00
Adrian Chadd
507de8028f Fix OFDM ANI statistics gathering for the AR5416 and later chips.
I found this when trying to figure out why the RX PHY error count
didn't match the OFDM error count ANI was using. It turns out
there was two problems:

* What this commit addresses - using the wrong mask for OFDM errors,
  and
* The RX filter is set incorrectly after a channel scan (at least)
  even if interference mitigation is enabled by default.

ANI is still disabled by default for the AR5416 and later chips.
2011-03-22 07:19:49 +00:00
Adrian Chadd
fdb9c24c19 Set the "right" CCA register.
Obtained From:	ath9k
2011-03-22 05:47:48 +00:00
Adrian Chadd
6359b5731c Break out the RF mode setup into ar5416SetRfMode(), mirroring what ath9k does. 2011-03-22 00:52:44 +00:00
Adrian Chadd
b335ecffa2 Do a bit of spring cleaning in the board setup code, just to
bring it in line with the rest of the register initialisation.

I've verified that the 2/5ghz board values written to the
chip match what was previously written.
2011-03-22 00:43:58 +00:00
Adrian Chadd
dca968a2ce Bring over a few queue changes from ath9k:
* add pspoll/uapsd queue setup defaults;
* enable the exponential backoff window rather than the random
  backoff window when doing TX contention management.
2011-03-22 00:14:17 +00:00
Adrian Chadd
299bb4987b Even though it's very unlikely the misc mode register setting at -attach-
would be a problem, make sure it isn't overwritten by whatever is in
there at cold reset.

This brings the > ar5416 init path treatment of AR_MISC_MODE.
2011-03-22 00:12:26 +00:00
Adrian Chadd
fecc2a5eea Remove the merlin delay workaround here, it isn't appropriate for
the analog bank writes as Merlin never does them.
2011-03-22 00:11:04 +00:00
Adrian Chadd
1f0caefd53 Back that commit out - something's broken, and I need to figure out
what/why.
2011-03-21 17:44:52 +00:00
Adrian Chadd
020f937363 This CLKDRV workaround should only be for AR5416 v2.0/2.1;
the check was too strict and enabled it for all non AR5416-v2.2
chipsets - including later ones.
2011-03-21 17:12:03 +00:00
Adrian Chadd
c4ac32a897 Fix static ucastrate for ath_rate_sample.
* Pull out the static rix stuff into a different function
* I know this may slightly drop performance, but check if a static
  rix is needed before each packet TX.

* Whilst I'm at it, add a little extra debugging to the rate
  control stuff to make it easier to follow what's going on.
2011-03-21 12:51:13 +00:00
Adrian Chadd
d413a349e5 Disable a check I added a while ago to ensure the initial NF cal completed.
Give it a good go (32 attempts) and then print out a warning that's
going to occur whether HAL debugging is enabled or not. Then don't
abort the radio setup; just continue merrily along.

This should fix the issue that users were having where scanning would
occasionally fail on the active channel, causing traffic to cease
until the radio scanned again.
2011-03-20 15:46:05 +00:00
Adrian Chadd
baab333c80 Cave in and disable the ADC DC gain/offset calibrations if they're
not needed.

These calibrations are only applicable if the chip operating mode
engages both interleaved RX ADCs (ie, it's compensating for the
differences in DC gain and DC offset -between- the two ADCs.)
Otherwise the chip reads values of 0x0 for the secondary ADC
(as I guess it's not enabled here) and thus writes potentially
bogus info into the chip.

I've tested this on the AR9160 and AR9280; both behave themselves
in 11g mode with these calibrations disabled.
2011-03-20 09:08:45 +00:00
Adrian Chadd
d27f017997 * Remove a not-needed check in the AR5416+ case
* Restore the chip default of the DCU backoff threshold to 0x2,
  mirroring what ath9k does.
2011-03-20 08:47:59 +00:00
Adrian Chadd
4bc2f08fc0 Bring over a copy of the AR5212 TX queue reset and setup routines, in preparation
for fixing them based on the ath9k related TXQ fixes.

I've done this so people can go over the history of the diffs to the original
AR5212 routines (which AR5416 and later chips use) to see what's changed.
2011-03-20 08:42:56 +00:00
Adrian Chadd
3f9a52c30d Add a PSPOLL queue type, in preparation for (eventually) porting
over the TX queue setup code from ath9k for the AR5416 and later
chips.
2011-03-20 08:27:06 +00:00
Adrian Chadd
336cfe471e Add in the channel survey data structures. These will be filled out
by the HAL at some point in the future.
2011-03-19 14:38:28 +00:00
Adrian Chadd
f395957311 Reserve a new diagnostic code for the channel survey code I'll add soon. 2011-03-19 14:37:13 +00:00
Adrian Chadd
534f8ec8b2 Make sure that the AR_MISC_MODE value from the initvals are properly respected.
This commit really is "fix the OFDM duration calculation to match reality when
running in 802.11g mode."

The AR5212 init vals set AR_MISC_MODE to 0x0 and all the bits that can be set are
set through code.

The AR5416 and later initvals set AR_MISC_MODE to various other values (with
the AR5212 AR_MISC_MODE options cleared), which include AR_PCU_CCK_SIFS_MODE .
This adds 6uS to SIFS on non-CCK frames when transmitting.

This fixes the issue where _DATA_ 802.11g OFDM frames were being TX'ed with
the ACK duration set to 38uS, not 44uS as on the AR5212 (and other devices.)

The AR5212 TX pathway obeys the software-programmed duration field in the packet,
but the 11n TX pathway overrides that with a hardware-calculated duration. This
was getting it wrong because of the above AR_MISC_MODE setting. I've verified
that 11g data OFDM frames are now being TXed with the correct ACK+SIFS duration
programmed in.
2011-03-19 03:15:28 +00:00
Adrian Chadd
a85eaa7714 Use the HAL method rather than directly calling ar5212ResetTxQueue().
Since ath9k does some slightly different bit fiddling when setting up
the TX queues, it may that the TX queue setup/reset functions will need
overriding later on.
2011-03-19 03:09:21 +00:00
Adrian Chadd
9082beb051 Add debugging messages to the AR5416 ANI code that's found in the AR5212 ANI code. 2011-03-19 00:46:10 +00:00
Adrian Chadd
79e8a562ac Fix typo that snuck in. 2011-03-14 02:32:10 +00:00
Adrian Chadd
df20f67447 Bring over the AR9285 board update code from ath9k.
This does a few things in particular:

* Abstracts out the gain control settings into a separate function;
* Configure antenna diversity, LNA and antenna gain parameters;
* Configure ob/db entries - the later v4k EEPROM modal revisions have
  multiple OB/DB parameters which are used for some form of
  calibration. Although the radio does have defaults for each,
  the EEPROM can override them.

This resolves the AR2427 related issues I've been seeing and makes
it stable at all 11g rates for both TX and RX.
2011-03-14 00:42:48 +00:00
Adrian Chadd
77b9efed7b Fix the nfarray offsets for the ar2133/ar5133 radio - (AR5416, AR9160, etc.)
The offsets didn't match the assumption that nfarray[] is ordered by the
chainmask bits and programmed via the register order in ar5416_cca_regs[].
This repairs that damage and ensures that chain 1 is programmed correctly.
(And extension channels will now be programmed correctly also.)

This fixes some of the stuck beacons I've been seeing on my AR9160/AR5416
setups - because Chain 1 would be programmed -80 or -85 dBm, which is
higher than the actual noise floor and thus convincing the radio that
indeed it can't ever transmit.
2011-03-13 13:00:45 +00:00
Adrian Chadd
fce6d67665 The number of streams is not based on the interface stream count, but the
number of streams needed for that MCS rate.
2011-03-13 08:23:59 +00:00
Adrian Chadd
6ff1b2bda8 Move out some of the shared eeprom board value calculation routines into ah.c
rather than duplicating them for the v14 (ar5416+) and v4k (ar9285) codebases.

Further chipsets (eg the AR9287) have yet another EEPROM format which will use
these routines to calculate things.
2011-03-13 05:54:05 +00:00
Adrian Chadd
b90b8dd2b2 * Add in some board settings debugging to log what's being written
to the TX closed-loop power control registers.
* Modify a couple of functions to take the register chain number,
  rather than the regChainOffset value. This allows for the
  register chain to be logged.
2011-03-13 05:30:14 +00:00
Adrian Chadd
586b0ae5aa Port over the AR9285 PA calibration and initial calibration code from
Linux ath9k.

The ath9k ar9002_hw_init_cal() isn't entirely clear about what
is supposed to be called for what chipsets, so I'm ignoring the
rest of it and just porting the AR9285 init cal path as-is and
leaving the rest alone. Subsequent commits may also tidy up the
Merlin (AR9285) and other chipset support.

Obtained from:	Linux ath9k
2011-03-11 11:58:54 +00:00
Adrian Chadd
c0b9002dcb Introduce methods for the initial calibration and the new PA calibration
routines.

These are needed for the AR9285/AR2427 and AR9287 calibration routines
which will be introducecd in a later commit.
2011-03-11 11:35:36 +00:00
Adrian Chadd
e8a217e075 Remove the ar9285FillVpdTable() and just use ar5416FillVpdTable(). 2011-03-11 11:07:53 +00:00
Adrian Chadd
d2699f71b4 Bring over the same fix from the AR5416 PDADC calibration code.
The ath9k driver has a unified boundary/pdadc function, whereas
ours is split into two (one for each EEPROM type.) This is why
the AR9280 check is done here where we could safely assume it'll
always be AR9280 or later.
2011-03-11 04:31:00 +00:00
Adrian Chadd
9ec9578e01 Don't call ar5416SetTransmitPower() directly from ar5416SetTxPowerLimit();
this is incorrect for Kite (AR9285) and any future chipsets that
override the EEPROM related routines.

It meant that a direct call to set the TX power would call the v14 EEPROM
AR5416/AR9280 calibration routines, rather than the v4k EEPROM routines
for the AR9285. It thus read the incorrect values from the EEPROM and
programmed garbage PDADC and TX power values into the hardware.
2011-03-11 03:46:27 +00:00
Adrian Chadd
d6cfe61d68 Kite is a 1x1 stream device. 2011-03-10 11:23:43 +00:00
Adrian Chadd
0c89688b3b Now that the power curve adjustment code is in, disable the error check
I introduced earlier, and turn it into debugging output.
2011-03-10 06:09:55 +00:00
Adrian Chadd
cc5c884d02 Port over the v14 eeprom PDADC curve changes from ath9k.
It looks like these apply in both open and closed loop TX power control,
but the only merlin boards i have either have OL -or- a non-default power
offset, not both.
2011-03-10 06:08:24 +00:00
Adrian Chadd
b2b029190f Merlin fix - first pdadc gain index is 0 - minpwr/2 .
Obtained from:	Linux ath9k
2011-03-10 06:06:26 +00:00
Adrian Chadd
c48e24c122 Migrate the regulatory database definitions into separate header files
to both make things clearer, and to make it easier to write userland
code which pulls in these definitions without needing to pull in the
rest of the HAL.

This stuff should be deprecated at some point in the future once
the net80211 regulatory domain support encapsulates all of the
defintions here.
2011-03-10 03:13:56 +00:00
Adrian Chadd
c50678682f Introduce the Merlin PWDCLKIND workaround.
This is something bus clock related from what I can gather. It is needed for
the AR9220 based Ubiquiti SR71-12 and SR71-15 Mini-PCI NICs.

(Note: those NICs don't work right now because of earlier changes to handle
power table offset correctly. That'll be resolved in a follow-up commit.)
2011-03-10 02:09:06 +00:00
Adrian Chadd
beb4faf377 For chips that are full reset in ar5416ChipReset(), save and restore the TSF.
Merlin (ar9280) and later were full-reset if they're doing open-loop TX
power control but the TSF wasn't being saved/restored.

Add ar5212SetTsf64() which sets the 64 bit TSF appropriately.
2011-03-09 04:39:35 +00:00
Adrian Chadd
2836e2ae73 Break out the ath regulatory domain structures into a separate header file. 2011-03-08 07:42:09 +00:00
Adrian Chadd
48c1d36479 Implement open-loop TX power control (OLC) for Merlin (AR9280) and
generally tidy up the TX power programming code.

Enforce that the TX power offset for Merlin is -5 dBm, rather than
any other value programmable in the EEPROM. This requires some
further code to be ported over from ath9k, so until that is done
and tested, fail to attach NICs whose TX power offset isn't -5
dBm.

This improves both legacy and HT transmission on my merlin board.
It allows for stable MCS TX up to MCS15.

Specifics:

* Refactor out a bunch of the TX power calibration code -
  setting/obtaining the power detector / gain boundaries,
  programming the PDADC
* Take the -5 dBm TX power offset into account on Merlin -
  "0" in the per-rate TX power register means -5 dBm, not
  0 dBm
* When doing OLC
* Enforce min (0) and max (AR5416_MAX_RATE_POWER) when fiddling
  with the TX power, to avoid the TX power values from wrapping
  when low.
* Implement the 1 dBm cck power offset when doing OLC
* Implement temperature compensation for 2.4ghz mode when doing OLC
* Implement an AR9280 specific TX power calibration routine which
  includes the OLC twiddles, leaving the earlier chipset path
  (AR5416, AR9160) alone

Whilst here, use these refactored routines for the AR9285 TX power
calibration/programming code and enforce correct overflow/underflow
handling when fiddling with TX power values.

Obtained from:	linux ath9k
2011-03-08 06:59:59 +00:00
Adrian Chadd
8823714276 Add an EEPROM op that extracts out the power table offset.
It defaults to -5 dBm for eeproms earlier than v21.

This apparently only applies to Merlin (AR9280) or later,
earlier 11n chipsets have a power table offset of 0.
All the code in ath9k which checks the power table offset
and takes it into account first ensures the chip is
Merlin or later.
2011-03-06 00:30:43 +00:00
Adrian Chadd
f247e82033 Change HALDEBUG() to be a macro that conditionally calls the debug output routine.
The earlier way of doing debugging would evaluate the function parameters
before calling the HALDEBUG. In the case of detailed register debugging
would mean a -lot- of unneeded register IO and other stuff was going on.

This method evaluates the ath_hal_debug variable before the function
parameters are evaluated, drastically reducing the amount of overhead
enabling HAL debugging during compilation.
2011-03-05 21:20:18 +00:00
Adrian Chadd
5fb8c8d60c The sample rate module currently does the slightly wrong thing when
determining whether to use MRR or not.

It uses the 11g protection mode when calculating 11n related stuff, rather
than checking the 11n protection mode.

Furthermore, the 11n chipsets can quite happily handle multi-rate retry w/
protection; the TX path and rate control modules need to be taught about
that.
2011-03-03 20:41:59 +00:00
Adrian Chadd
9d6de76d8e Port over ar5416OverrideIni() from ath9k ar5008_hw_override_ini().
* change the BB gating logic to explicitly define which chips are covered;
  the ath9k method isn't as clear.
* don't disable the BB gating for now, the ar5416 initvals have it, and the
  ar9160 initval sets it to 0x0. Figure out why before re-enabling this.
* migrate the Merlin (ar9280) applicable WAR from the Kite (ar9285) code
  (which won't get called for Merlin!) and stuff it in here.
2011-03-03 08:38:31 +00:00
Adrian Chadd
ddbac71b7a * fix the ar5416 check macros to be slightly more correct;
* add some stubs for chipsets that we haven't yet obtained support for.
2011-03-03 08:30:28 +00:00
Adrian Chadd
ae0944b8f8 Modify the sample rate module output to be (slightly) easier to understand.
* add dot11rate_label() which returns Mb or MCS based on legacy or HT
* use it everywhere dot11rate() is used
* in the "current selection" part at the top of the debugging output,
  otuput what the rate itself is rather than the rix. The rate index
  (rix) has very little meaning to normal humans who don't know how
  to find the PHY settings for each of the chipsets; pointing out the
  rix rate and type is likely more useful.
2011-03-03 08:09:49 +00:00
Adrian Chadd
4c95757404 Disable trying to do HT/40 and short-GI TX.
These flags are just plain wrong - they're the node flags from negotiation,
not the configured flags. I'll jump in later on and figure out exactly
what should be done to properly set these two flags when in both STA mode
(ie, what the AP says is possible and what's configured) and AP mode
(ie, where the AP has a configuration, but then negotiates what's possible
with each node, so per-node configuration can and will differ.)

This allows the 11n 2.4ghz/ht20 mode to associate (but perform poorly still)
and exchange MCS rates with atheros reference APs and a Cisco/Linksys
E3000 AP.
2011-03-03 03:02:06 +00:00
Adrian Chadd
d2d7a00aa9 Break the keycache management functions out into if_ath_keycache.c . 2011-03-02 17:19:54 +00:00
Adrian Chadd
6079fdbede Migrate the sysctl related routines (statistics, debugging, etc) out of
if_ath.c and into if_ath_sysctl.c .
2011-03-02 16:03:19 +00:00
Adrian Chadd
2b5684a813 Don't set the RTS/CTS enable bit per-scenario if the global RTS/CTS
flags aren't set.
2011-02-22 04:41:04 +00:00
Adrian Chadd
e42b5dba51 Shuffle around the RTS/CTS rate/duration logic.
* Turn ath_tx_calc_ctsduration() into a function that
  returns the ctsduration, or -1 for HT rates;
* add a printf() to ath_tx_calc_ctsduration() which will be
  very loud if somehow that function is called with an MCS
  rate;
* Add ath_tx_get_rtscts_rate() which returns the RTS/CTS
  rate to use for the given data rate, incl. the short
  preamble flag;
* Only call ath_tx_calc_ctsduration() for non-11n chipsets;
  11n chipsets don't require the rtscts duration to be
  calculated.
2011-02-22 00:37:53 +00:00
Adrian Chadd
146b49d8cb * Don't setup the scenario if the try count is 0
* Comment what else is going on during rate scenario setup
2011-02-22 00:01:19 +00:00
Adrian Chadd
b28f46973d Fix formatting of new stat sysctls; add descriptions 2011-02-21 19:22:45 +00:00
Adrian Chadd
d6efa33001 Add a new counter which tracks frames TX'ed with HT protection. 2011-02-21 19:19:05 +00:00
Adrian Chadd
4a02016d6e Add a vocal warning to ath_hal_computetxtime() function is used for non-11n rates.
It's used to calculate:

* the initial per-rate entries for short/long preamble ACK durations;
* packet durations for TDMA slot decisions;
* RTS/CTS protection durations;
* updating the duration field in the 802.11 frame header

This way invalid durations will generate a warning, prompting for it to be
fixed.
2011-02-21 18:58:58 +00:00
Adrian Chadd
ade7b47061 Modify the AR5416 11na rate table to use 24mb OFDM 11a for control traffic,
rather than MCS 0.

Using MCS0 for protecting 11a rates seems a bit silly.
2011-02-21 05:10:34 +00:00
Adrian Chadd
9a97e25edf Implement setting the short preamble bit if it's needed for the current node.
Short preamble rates are only for legacy rates; MCS rate codes don't have a short
preamble code like this.
2011-02-21 03:52:51 +00:00
Adrian Chadd
7842451a3a Just be double-sure short-gi isn't being enabled in 20mhz mode. 2011-02-17 17:35:09 +00:00
Adrian Chadd
cf8d6b64e5 Disable short-GI in 20mhz mode - the hardware doesn't support this. 2011-02-17 17:31:36 +00:00