4690 Commits

Author SHA1 Message Date
alc
4cde6a5313 Add support for pmap_enter(..., psind=1) to the armv6 pmap. In other words,
add support for explicitly requesting that pmap_enter() create a 1 MB page
mapping.  (Essentially, this feature allows the machine-independent layer
to create superpage mappings preemptively, and not wait for automatic
promotion to occur.)

Export pmap_ps_enabled() to the machine-independent layer.

Add a flag to pmap_pv_insert_pte1() that specifies whether it should fail
or reclaim a PV entry when one is not available.

Refactor pmap_enter_pte1() into two functions, one by the same name, that
is a general-purpose function for creating pte1 mappings, and another,
pmap_enter_1mpage(), that is used to prefault 1 MB read- and/or execute-
only mappings for execve(2), mmap(2), and shmat(2).

In addition, as an optimization to pmap_enter(..., psind=0), eliminate the
use of pte2_is_managed() from pmap_enter().  Unlike the x86 pmap
implementations, armv6 does not have a managed bit defined within the PTE.
So, pte2_is_managed() is actually a call to PHYS_TO_VM_PAGE(), which is O(n)
in the number of vm_phys_segs[].  All but one call to PHYS_TO_VM_PAGE() in
pmap_enter() can be avoided.

Reviewed by:	kib, markj, mmel
Tested by:	mmel
MFC after:	6 weeks
Differential Revision:	https://reviews.freebsd.org/D16555
2018-08-08 16:55:01 +00:00
marius
4641f7c338 Implement atomic_swap_64(9). 2018-08-07 18:56:01 +00:00
andrew
70c2a80947 Default to armv5te in LINT on arm. This should fix building LINT there. 2018-08-06 14:40:45 +00:00
manu
a0332168f8 aw_thermal: Add nvmem and H5 support
Now that aw_sid expose nvmem interface, use that to read the calibration
data.
Add support for H5 SoC.
Fix the bindings, we used to have non-upstreamed bindings. Switch to the
one that have been sent upstream. They are not stable yet, so we switch
from custom, wrong, bindings to correct, proposed bindings
2018-08-06 05:36:00 +00:00
manu
5836e9a6b2 aw_sid: Add nvmem interface
Rework aw_sid so it can work with the nvmem interface.
Each SoC expose a set of fuses (for now rootkey/boardid and, if available,
the thermal calibration data). A fuse can be private or public, reading private
fuse needs to be done via some registers instead of reading directly.
Each fuse is exposed as a sysctl.
For now leave the possibility for a driver to read any fuse without using
the nvmem interface as the awg and emac driver use this to generate a mac
address.
2018-08-06 05:35:24 +00:00
manu
fb8aa544dd allwinner: a64: Add THS clock support
The clock for the thermal sensor controller was missing when this driver
was made.
2018-08-05 06:16:36 +00:00
manu
4eb0d738ef arm: allwinner: Disconnect A10/A20 HDMI driver
It doesn't work since 2 years when we stopped patching DTS.
The DTS now have the correct bindings but they are a lot different
from our hacked ones we used to have (and more representative of the
reality).
2018-08-05 06:10:13 +00:00
manu
0620da4aab arm: allwinner: Remove old unused clocks
Remove the old clocks for allwinner as now all the SoCs have been converted
to clkng.
The only old clock now is the gmac clock which still lives under the /clocks
dts node.
2018-08-05 06:08:23 +00:00
manu
11c3299ebf arm: Remove ALLWINNER_UP kernel config
This was needed when we GENERIC couldn't boot on UP system.
2018-08-03 22:15:58 +00:00
kib
3792b2b104 Add pmap_is_valid_memattr(9).
Discussed with:	alc
Sponsored by:	The FreeBSD Foundation, Mellanox Technologies
MFC after:	1 week
Differential revision:	https://reviews.freebsd.org/D15583
2018-08-01 18:45:51 +00:00
manu
730b0d8415 nvmem: Add nvmem interface and helpers
The nvmem interface helps provider of nvmem data to expose themselves to consumer.
NVMEM is generally present on some embedded board in a form of eeprom or fuses.
The nvmem api are helpers for consumer to read/write the cell data from a provider.

Differential Revision:	https://reviews.freebsd.org/D16419
2018-07-31 19:08:24 +00:00
andrew
548b8d203d Remove teh non-INTRNG code from the ARM GIC interrupt controller driver.
We don't build for the non-INTRNG case and it was makeing the code harder
to read.
2018-07-30 10:55:02 +00:00
andrew
6bf898c6a8 Require ARMv5 for arm. All current kernels are for ARMv5 or later, and it
will allow us to clean out old ARMv4 (and earlier) specific assembly.

Relnotes:	yes
2018-07-30 09:50:26 +00:00
alc
96b23bde06 Prepare for adding psind == 1 support to armv6's pmap_enter().
Precompute the new PTE before entering the critical section.

Eliminate duplication of the pmap and pv list unlock operations in
pmap_enter() by implementing a single return path.  Otherwise, the
duplication will only increase with the upcoming support for psind == 1.

Reviewed by:	mmel
Tested by:	mmel
Discussed with:	kib, markj
MFC after:	3 weeks
Differential Revision:	https://reviews.freebsd.org/D16443
2018-07-30 01:54:25 +00:00
andrew
ade951d0c6 Use the cp15 functions to read cp15 registers rather than using assembly
functions. The former are static inline functions so will compile to a
single instruction.
2018-07-28 17:21:34 +00:00
andrew
2ae3878a3d Remove an unneeded cpu_ident() prototype. 2018-07-28 16:56:46 +00:00
andrew
40e6d09fbd Remove some write only global values from the arm cpufunc code. 2018-07-28 12:53:10 +00:00
andrew
d2653b587a Remove an unused function from the arm ELF trampoline. It tries to find
properties about the CPU caches, however we never use these values.
2018-07-28 12:52:03 +00:00
andrew
1d90ddc6fd Only build the cache handling code we need when building the arm ELF
trampoline.
2018-07-28 12:50:09 +00:00
andrew
c935c49309 Make the arm cpu setup functions static. Any other place that needs these
functions will use the function pointer we create for them.
2018-07-28 12:20:42 +00:00
andrew
fbe226fb3a Remove an unneeded check for CPU_XSCALE_81342 2018-07-28 12:16:57 +00:00
andrew
b411b4b9dd Remove old CPU_ values from the arm cpufunc code. These have been removed. 2018-07-28 12:00:32 +00:00
andrew
0e1e3daecc Remove the old CPU_ values from the arm kernel trampoline. These options
are gone so we can remove them from the code.
2018-07-28 11:58:43 +00:00
andrew
c1273a09d6 Remove now the cow unused CPU_ARM9 and CPU_FA526 options. These are for
ARMv4 CPUs that are no longer supported.
2018-07-28 11:00:45 +00:00
andrew
58ca1b6730 The RT1310 is an ARM926EJ-S, fix the config to mark it as such. 2018-07-28 10:48:41 +00:00
andrew
388c937191 Only support INTRNG in the SMP code on arm. We already require INTRNG on
anything that could be multicore on arm.
2018-07-28 07:54:21 +00:00
andrew
e91597da47 Remove IPI_IRQ_START and IPI_IRQ_END from the arm kernel config files.
These are unneeded with INTRNG.
2018-07-28 06:46:10 +00:00
imp
86c4a1dbdb This builds now, so aadd it back to Universe. 2018-07-27 21:26:32 +00:00
imp
fba826ec00 Remove xscale support.
As discussed in arm@.  This is a scaled back version of the prior
commit because xscale is overlaoded in places to mean armv5 or
similar.  The OLD XSCALE stuff hasn't been useful in a while. The
original committer (cognet@) was the only one that had boards for
it. He's blessed this removal. Newer XSCALE (GUMSTIX) is for hardware
that's quite old. After discussion on arm@, it was clear there was no
support for keeping it.

Noticed by: andrew@
2018-07-27 21:25:07 +00:00
imp
de47afa9bf Revert r336773: it removed too much.
r336773 removed all things xscale. However, some things xscale are
really armv5. Revert that entirely. A more modest removal will follow.

Noticed by: andrew@
2018-07-27 21:25:01 +00:00
imp
0a4723bbc5 Remove xscale support
The OLD XSCALE stuff hasn't been useful in a while. The original
committer (cognet@) was the only one that had boards for it. He's
blessed this removal. Newer XSCALE (GUMSTIX) is for hardware that's
quite old. After discussion on arm@, it was clear there was no support
for keeping it.

Differential Review: https://reviews.freebsd.org/D16313
2018-07-27 18:33:09 +00:00
imp
63398019f7 Make ralink compile again.
Add std.ralink to define common things across all ralink configs.
Add cpu, machine and options INTRNG to this file.
Remove RT1310.hints file reference: that file isn't in our tree.
2018-07-27 18:31:30 +00:00
imp
e572e5e488 Remove Cavium/Econa CNS11xx support.
This port hasn't been updated since it was committed, apart from
housekeeping. There's no known users, and the known hardware for
this port is too thin to run FreeBSD/arm these days well.

This also removes the last armv4 port. We've had no reports of armv4
systems working since FreeBSD 8. All the kernel support for armv4 has
not been removed since it's too intertwined with armv5 support (which
remains in the tree).

RelNotes: Yes
No objection from: arm@
2018-07-27 18:30:01 +00:00
imp
a6cf0e2f77 Remove Atmel AT91RM9200 and AT91SAM9 support.
The last known robust version of this code base was FreeBSD 8.2. There
are no users of this on current, and all users of it have abandoned
this platform or are in legacy mode with a prior version of FreeBSD.

All known users on arm@ approved this removal, and there were no
objections.

Differential Revision: https://reviews.freebsd.org/D16312
2018-07-27 18:28:22 +00:00
jhb
fbdea4b3c3 Raise a proper SIGTRAP / TRAP_TRACE signal for a PT_STEP step on arm.
Previously, a step by PT_STEP resulted in no signal being raised to
the debugger so that a step was silently completed with the program
continuing to execute after the step.  Fix by raising a SIGTRAP
signal with TRAP_TRACE as the signal code.

To simplify the error handling cases (if ptrace_clear_single_step()
fails, etc.) move the handling of PTRACE_BREAKPOINT into the
gdb_trapper() function.  If ptrace_clear_single_step() fails,
gdb_trapper() won't claim the fault, and the default case of
SIGILL / ILL_OPC will be used.

Differential Revision:	https://reviews.freebsd.org/D16100
2018-07-25 18:11:37 +00:00
avg
1638b2c929 follow-up to r336635, update TAILQ to CK_SLIST for ie_handlers
arm, mips and sparc64 were affected.
2018-07-23 15:36:55 +00:00
ian
ad018a1eaf Add option MAC to armv6 and armv7 kernels by default, it needs to be
compiled-in to allow loading policy modules at runtime.
2018-07-21 18:54:24 +00:00
manu
2e0566a9ef arm: Implement cpu_est_clockrate for armv[67] 2018-07-19 11:27:11 +00:00
mmel
19d66463c0 Remove the dead code from ARM cpufunc_* files.
The elf trampoline was never been supported for ARMv6 and ARMv7 and was
disconnected from kernel build many months ago.

MFC after:	2 weeks
2018-07-18 10:33:07 +00:00
andrew
f4bf04615a Also check if __ARM_ARCH_6KZ__ is defined when detecting when to use ARMv6
instructions. There is some code that still uses the _ARM_ARCH_* macros.

Sponsored by:	DARPA, AFRL
2018-07-18 09:17:37 +00:00
imp
000ad38a32 Remove kernel support for armeb
Remove all the big-endian arm architectures (ixp425 and ixp435)
support in the kernel and associated drivers.

Differential Revision:  https://reviews.freebsd.org/D16257
2018-07-17 23:23:45 +00:00
manu
4b4713aad9 allwinner: a83t: Fix PLL_CPU clocks
The PLL_CPU clocks formula is 24Mhz * N and not 24Mhz / N
Fix it by using a NKMP clock with fixed factor values for the one
unused.
2018-07-16 13:38:16 +00:00
gonzo
25ee80c97b Remove two checks that are always false
Outer loop condition contradicts inner check so code under inner condition
is not reachable. Remove it.

PR:		229722
Reported by:	David Binderman
2018-07-16 01:07:28 +00:00
ian
c4fc8612bf Eliminate an unused var warning-error; the var is used only when parsing
linux-style boot args, so wrap it in the appropriate ifdef.
2018-07-14 16:33:11 +00:00
imp
98bb0af37d Fix machdep_boot.c
A last minute change made this no longer compile. Pass the right arg
and eliminate now-unused variables from the code.
2018-07-13 20:33:10 +00:00
mw
3d41e80ced Enable UART support for Xilinx Ultrascale+ SoCs
Xilinx Ultrascale+ are based on Cortex-A53 and use existing
UART driver (uart_dev_cdnc). Enable it in arm64 GENERIC config.

Submitted by: Michal Stanek <mst@semihalf.com>
Obtained from: Semihalf
2018-07-13 19:54:22 +00:00
imp
9b7d97ffbe Create helper functions for parsing boot args.
boot_parse_arg		to parse a single arg
boot_parse_cmdline	to parse a command line string
boot_parse_args		to parse all the args in a vector
boot_howto_to_env	Convert howto bits to env vars
boot_env_to_howto	Return howto mask mased on what's set in the environment.

All these routines return an int that's the bitmask of the args
translated to RB_* flags. As a special case, the 'S' flag sets the
comconsole_speed env var. Any arg that looks like a=b will set the env
key 'a' to value 'b'. If =b is omitted, 'a' is set to '1'.  This
should help us reduce the number of redundant copies of these routines
in the tree.  It should also give a more uniform experience between
platforms.

Also, invent a new flag RB_PROBE that's set when 'P' is parsed.  On
x86 + BIOS, this means 'probe for the keyboard, and if it's not there
set both RB_MULTIPLE and RB_SERIAL (which means show the output on
both video and serial consoles, but make serial primary).  Others it
may be some similar concept of probing, but it's loader dependent
what, exactly, it means.

These routines are suitable for /boot/loader and/or the kernel,
though they may not be suitable for the tightly hand-rolled-for-space
environments like boot2.

Sponsored by: Netflix
Differential Revision: https://reviews.freebsd.org/D16205
2018-07-13 16:43:05 +00:00
ian
b09e68cf4e Add pnp info to the imx_spi driver. 2018-07-09 19:00:39 +00:00
ian
c5133fcee3 Oops, fix a typo: imx_snvs should be imx6_snvs. 2018-07-08 21:14:43 +00:00
ian
d3561f8c4c Move device statements out of std.imx* and into kernel config files.
In the armv4/5 world device statements in these files were common, but in
the v6/7 world, other socs don't put device statements into those files, so
this just brings imx5 and imx6 into line with the current conventions.
2018-07-08 21:09:52 +00:00