Commit Graph

26390 Commits

Author SHA1 Message Date
Michael Baum
74e918604a net/mlx5: move Tx SQ creation to common
Using common function for Tx SQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
71011bd56b net/mlx5: move rearm and clock queue SQ creation to common
Using common function for DevX SQ creation for rearm and clock queue.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
9de7b16015 regex/mlx5: move DevX SQ creation to common
Using common function for DevX SQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
38f537635c common/mlx5: share DevX SQ creation
The SQ object in DevX is created in several places and in several
different drivers.
In all places almost all the details are the same, and in particular the
allocations of the required resources.

Add a structure that contains all the resources, and provide creation
and release functions for it.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
f002358cef common/mlx5: enhance page size configuration
The PRM calculates page size in 4K, so need to reduce the log_wq_pg_sz
attribute.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
5cd33796dd net/mlx5: move Rx CQ creation to common
Using common function for Rx CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
5f04f70ccf net/mlx5: move Tx CQ creation to common
Using common function for Tx CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
c7d41d98a7 net/mlx5: move ASO CQ creation to common
Use common function for ASO CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
a7787bb0b7 net/mlx5: move rearm and clock queue CQ creation to common
Using common function for CQ creation at rearm queue and clock queue.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
0e41abd198 vdpa/mlx5: move DevX CQ creation to common
Using common function for DevX CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
3ddf57069b regex/mlx5: move DevX CQ creation to common
Using common function for DevX CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
9dab4d62b4 common/mlx5: share DevX CQ creation
The CQ object in DevX is created in several places and in several
different drivers.
In all places almost all the details are the same, and in particular the
allocations of the required resources.

Add a structure that contains all the resources, and provide creation
and release functions for it.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
0e8273176e net/mlx5: fix leak on ASO SQ creation failure
In ASO SQ creation, the PMD allocates umem buffer for SQ.

When umem buffer allocation fails, the MR and CQ memory are not freed
what caused a memory leak.

Free it.

Fixes: f935ed4b64 ("net/mlx5: support flow hit action for aging")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
4a7f979af2 net/mlx5: remove CQE padding device argument
The data-path code doesn't take care on 'rxq_cqe_pad_en' and use padded
CQE for any case when the system cache-line size is 128B.

This makes the argument redundant.

Remove it.

Fixes: bc91e8db12 ("net/mlx5: add 128B padding of Rx completion entry")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Michael Baum
a2521c8f98 common/mlx5: fix completion queue entry size configuration
According to the current data-path implementation in the PMD the CQE
size must follow the cache-line size.
So, the configuration of the CQE size should be depended in
RTE_CACHE_LINE_SIZE.

Wrongly, part of the CQE creations didn't follow it exactly what caused
an incompatibility between HW and SW in the data-path when working in
128B cache-line size systems.

Adjust the rule for any CQE creation.
Remove the cqe_size attribute from the DevX CQ creation command and set
it inside the command translation according to the cache-line size.

Fixes: 79a7e409a2 ("common/mlx5: prepare support of packet pacing")
Fixes: 5cd0a83f41 ("common/mlx5: support more fields in DevX CQ create")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-14 10:12:36 +01:00
Dekel Peled
19e13263ed net/mlx5: fix hairpin flow split decision
Previously, the identification of hairpin queue was done using
mlx5_rxq_get_type() function.
Recent patch replaced it with use of mlx5_rxq_get_hairpin_conf(),
and check of the return value conf != NULL.
The case of return value is NULL (queue is not hairpin) was not handled.
As result, non-hairpin flows were wrongly handled.
This patch adds the required check for return value is NULL.

Fixes: 509f8470de ("net/mlx5: do not split hairpin flow in explicit mode")
Cc: stable@dpdk.org

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-01-13 19:45:30 +01:00
Tal Shnaiderman
5d55a494f4 net/mlx5: split multi-thread flow handling per OS
multi-threaded flows feature uses pthread function pthread_key_create
but for Windows the destruction option in the function is unimplemented.

To resolve it, Windows will implement destruction mechanism to cleanup
mlx5_flow_workspace object for each terminated thread.

Linux flow will keep the current behavior.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Khoa To <khot@microsoft.com>
2021-01-13 19:45:30 +01:00
Kiran Kumar K
fc4a83e6b8 net/octeontx2: support 24B custom L2 header parsing
Adding support to parse 24B custom L2 header. Added devargs support to
configure the PKIND, and removed the restriction to support custom
headers on non SDP interface.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-01-13 19:39:08 +01:00
Sunil Kumar Kori
54b79ac220 net/octeontx2: fix corruption in segments list
On Tx, lastseg->next is not being reset to null for multi segmented
packet and same mbuf can be used on Rx which has a stale mbuf entry into
mbuf->next.

On Rx, application receives mbuf with mbuf->next uninitialized though
mbuf->nb_segs is correct. Application iterates over all segments using
mbuf->next ignoring mbuf->nb_segs which leads to undefined behavior.

So earlier assumption of just having right value in mbuf->nb_segs is
enough, is incorrect. Mbuf must contain valid and synced value in
nb_segs and next pointer.

Fixes: 364eb0e466 ("net/octeontx2: avoid per packet barrier with multi segment")
Cc: stable@dpdk.org

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-01-13 19:39:08 +01:00
Yunjian Wang
565789662e net/mvneta: check allocation in Rx queue flush
The function rte_malloc() could return NULL, the return value
need to be checked.

Fixes: ce7ea76459 ("net/mvneta: support Rx/Tx")
Cc: stable@dpdk.org

Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Acked-by: Liron Himi <lironh@marvell.com>
2021-01-13 19:39:08 +01:00
Somnath Kotur
6f5f3b9982 net/bnxt: check chip reset in stop and close
While the error recovery thread is running, an application
can invoke dev_stop or dev_close_op thus triggering a race
and unwanted consequences if dev_close is invoked while the
recovery is not yet completed.
Fix by having another lock to synchronize between the 2 threads and
return EGAIN if adapter is in the middle of recovery when dev_stop
or dev_close ops are invoked

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-01-13 19:24:30 +01:00
Somnath Kotur
9d276b439a net/bnxt: fix error handling in device start
Call bnxt_dev_stop in error path of bnxt_dev_start_op() to keep
it simple and consistent

Fixes: c09f57b49c ("net/bnxt: add start/stop/link update operations")
Cc: stable@dpdk.org

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-01-13 19:24:30 +01:00
Somnath Kotur
c9ffd6f886 net/bnxt: fix lock init and destroy
Invoking init/uninit locks in init_resources and uninit_resources
would end up initializing and destroying locks on every port start
stop which is not desired.
Move the 2 routines to dev_init and dev_close respectively as
locks need to be initialized and destroyed only once during the
lifetime of the driver.

Fixes: 1cb3d39a48 ("net/bnxt: synchronize between flow related functions")
Cc: stable@dpdk.org

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-01-13 19:24:30 +01:00
Kalesh AP
899f061307 net/bnxt: add Rx logic for 58818 chips
1. On the new 58818 chips, the RX completion is largely the same except
   for the new completion opcode and the stripped VLAN format and
   checksum status. Added bnxt_parse_csum_v2(), bnxt_parse_pkt_type_v2()
   and bnxt_rx_vlan_v2() to support the new RX completion logic.
2. Disable vector mode RX/TX for 58818 chips for now.
3. The cfa_code format on 58818 chips is different than legacy chips.
   So skip cfa_code parsing logic on 58818 chips for now.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-01-13 19:24:30 +01:00
Kalesh AP
eb6ed2a99f net/bnxt: modify context memory allocation
Newer devices like SR2 may have chip backing store and do not require
host backed memory allocation.

In these cases, HWRM_FUNC_BACKING_STORE_QCAPS will return a zero entry
size to indicate contexts for which the host should not allocate backing
store.

Selectively allocate context memory based on device capabilities and
only enable backing store for the appropriate contexts

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-01-13 19:24:30 +01:00
Kalesh AP
4e936604d2 net/bnxt: support LRO for SR2 chip
Add the new chip specific TPA v2 logic to bnxt_tpa_start() to fully
support TPA on the new chip.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-01-13 19:24:30 +01:00
Kalesh AP
5d47d06b2c net/bnxt: modify VNIC accounting
Modify VNIC accounting when enabling RFS on newer chips.
Unlike legacy chips, newer chips don't need additional VNIC resources
for ntuple filter. Fix the code accordingly so that we don't reserve
and allocate additional VNICs on newer chips.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-01-13 19:24:30 +01:00
Kalesh AP
e97661757d net/bnxt: add new Rx checksum mode
The 58818 chips support two different checksum modes.
Host driver has to register with FW which checksum mode it
prefers to use. DPDK driver want to use "cs_all_ok_mode=1".
FW advertises the support of the different checksum modes
on per VNIC basis in the HWRM_VNIC_QCAPS response.
Driver should use HWRM_VNIC_CFG to configure the needed
checksum mode.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-01-13 19:24:30 +01:00
Kalesh AP
ecf1474a61 net/bnxt: support 58818 chip family
The new chip (Stingray 2) is part of the P5 chip family with a number
of changes:

1. Implement the epoch doorbell bit for 58818 chip. With the new
   doorbell infrastructure and the unbounded index logic, now set the
   epoch doorbell bit to support proper doorbell operation on the new
   chip.  Toggle epoch bit of all rings when it's wrapped to support
   doorbell overflow checking.
2. Get the legacy doorbell size from firmware. Legacy doorbell support
   has been removed in Stingray 2. So, the fast path doorbell pages
   start from the base of the BAR. Drivers need to use
   legacy_l2_db_space_size_kb field in the hwrm_func_qcfg_output
   response to get the legacy doorbell page offset from the BAR.
3. Set VALID doorbell bit on 58818 chip family. This class of chip has a
   valid doorbell bit added and it needs to be set.
4. Use "chip_num" returned by firmware. The "chip_num" field in the
   HWRM_VER_GET output returns the chip number. Use this value to
   identify chip category for 58818 chip family.
5. Added device ids for Stingray2 PF/VF devices.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-01-13 19:24:30 +01:00
Jeff Guo
68b6240ee9 net/ice: refactor packet type parsing
If the capability of a PTYPE within a specific package could be
negotiated, no need to maintain a different PTYPE list for each
type of the package when parsing PTYPE. So refactor the PTYPE
parsing mechanism for each flow engines.

Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:59 +01:00
Jeff Guo
8a923ee7e7 net/ice/base: add more packet type values
Add some macros for some PType value.

Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:59 +01:00
Murphy Yang
696ad314cc net/i40e: add null input checks
Pointer 'NULL' check for 'mac_addr' or 'conf' within i40e PMD APIs.

Fixes: 66c78f4799 ("net/i40e: add support for packet template to flow director")
Fixes: 04b443fb2c ("net/i40e: fix port id type")
Cc: stable@dpdk.org

Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Haiyue Wang
1c301e8c3c net/iavf: support new VLAN capabilities
The new VLAN virtchnl opcodes introduce new capabilities like VLAN
filtering, stripping and insertion.

The AVF needs to query the VLAN capabilities based on current device
configuration firstly.

AVF is able to configure inner VLAN filter when port VLAN is enabled
base on negotiation; and AVF is able to configure outer VLAN (0x8100)
if port VLAN is disabled to be compatible with legacy mode.

When port VLAN is updated by DCF, the AVF needs to reset to query the
new VLAN capabilities.

Signed-off-by: Qiming Yang <qiming.yang@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Haiyue Wang
5674465a32 net/ice: add DCF VLAN handling
Add the DCF port representor infrastructure for the VFs of DCF attached
PF. Then the standard ethdev API like VLAN can be used to configure the
VFs.

Signed-off-by: Qiming Yang <qiming.yang@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Haiyue Wang
e5c9ed3bbd net/iavf: support CRC strip disabling
The VF will check the PF's CRC strip capability firstly, then set the
'CRC strip disable' value in the queue configuration according to the
RX CRC offload setting.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Qi Zhang
7815caa653 common/iavf: update copyright date
Updated the Copyright for 2021.
Updated FreeBSD IAVF driver of version.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Qi Zhang
4b4d2affbd common/iavf: support VLAN offload by DCF
Add new opcode VIRTCHNL_OP_DCF_VLAN_OFFLOAD to set VLAN offload
by DCF, the virtchnl message includes:
1. A valid target VF
2. Type of VLAN to be supported: outer or inner
3. Ethertype of the VLAN (either 0x8100 or 0x88A8 or 0x9100)
4. VLAN insert settings
   a). No insert offload, VLAN ID in the packet (default)
   b). Offload via transmit descriptor
   c). Insert as a port VLAN (via VSI)
5. VLAN strip settings
   a). Strip (and discard)
   b). Strip and place in descriptor
   c). No Strip
6. VLAN ID for the target VF

Signed-off-by: Qiming Yang <qiming.yang@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Qi Zhang
86edb0bd75 common/iavf: support new VLAN capabilities
Currently VIRTCHNL only allows for VLAN filtering and offloads to happen
on a single 802.1Q VLAN. Add support to filter and offload on inner,
outer, and/or inner + outer VLANs.

This is done by introducing the new capability
VIRTCHNL_VF_OFFLOAD_VLAN_V2. The flow to negotiate this new capability
is shown below.

1. VF - sets the VIRTCHNL_VF_OFFLOAD_VLAN_V2 bit in the
   virtchnl_vf_resource.vf_caps_flags during the
   VIRTCHNL_OP_GET_VF_RESOURCES request message. The VF should also set
   the VIRTCHNL_VF_OFFLOAD_VLAN bit in case the PF driver doesn't
   support the new capability.

2. PF - sets the VLAN capability bit it supports in the
   VIRTCHNL_OP_GET_VF_RESOURCES response message. This will either be
   VIRTCHNL_VF_OFFLOAD_VLAN_V2, VIRTCHNL_VF_OFFLOAD_VLAN, or none.

3. VF - If the VIRTCHNL_VF_OFFLOAD_VLAN_V2 capability was ACK'd by the
   PF, then the VF needs to request the VLAN capabilities of the
   PF/Device by issuing a VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS request.
   If the VIRTCHNL_VF_OFFLOAD_VLAN capability was ACK'd then the VF
   knows only single 802.1Q VLAN filtering/offloads are supported. If no
   VLAN capability is ACK'd then the PF/Device doesn't support hardware
   VLAN filtering/offloads for this VF.

4. PF - Populates the virtchnl_vlan_caps structure based on what it
   allows/supports for that VF and sends that response via
   VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS.

After VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS is successfully negotiated
the VF driver needs to interpret the capabilities supported by the
underlying PF/Device. The VF will be allowed to filter/offload the
inner 802.1Q, outer (various ethertype), inner 802.1Q + outer
(various ethertypes), or none based on which fields are set.

The VF will also need to interpret where the VLAN tag should be inserted
and/or stripped based on the negotiated capabilities.

Also, update the virtchnl_op_str() function to support the added opcodes.

Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Leyi Rong
295906ffaa net/ice: enlarge Rx queue rearm threshold to 64
We observe performance drop on ice AVX512 data path after stop and
start by using testpmd.

As CPU polling is faster in AVX512 path, L3 contested accesses is
intensified when rxrearm_start is a random value after testpmd
stop/start.

Enlarge ICE_RXQ_REARM_THRESH to 64 to ease the contested accesses and
fix the performance drop issue.

Cc: stable@dpdk.org

Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Murphy Yang
30dc028802 net/ice: disable IPv4 checksum offload in vector Tx
ICE choices vector TX path or basic TX path by macro
'ICE_NO_VECTOR_FLAGS'.

This patch adds 'DEV_TX_OFFLOAD_IPV4_CKSUM' in 'ICE_NO_VECTOR_FLAGS'
to make IPv4 checksum offload processed by basic TX path.

Fixes: a224832088 ("net/ice: disable TSO offload in vector path")
Cc: stable@dpdk.org

Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Alvin Zhang
7fe2fde05a net/ice: fix RSS lookup table initialization
RSS look-up table initialization is done incorrectly due to
divide-by-zero error.
Add a check to rx-queue count.

Fixes: 50370662b7 ("net/ice: support device and queue ops")
Cc: stable@dpdk.org

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Tested-by: Wei Xie <weix.xie@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-13 18:51:58 +01:00
Murphy Yang
653b88893b net/iavf: fix conflicting RSS combination rules
Currently, when use 'flow' command to create a rule with following
invalid RSS type combination, it can be created successfully.

Invalid RSS combinations list:
 - ETH_RSS_IPV4 | ETH_RSS_NONFRAG_IPV4_TCP
 - ETH_RSS_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP

This patch adds these combinations in 'invalid_rss_comb' array to do
valid check, if the combination check failed, the rule will be created
unsuccessful.

Fixes: 91f27b2e39 ("net/iavf: refactor RSS")
Cc: stable@dpdk.org

Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
Acked-by: Jeff Guo <jia.guo@intel.com>
2021-01-13 18:51:58 +01:00
Jiawen Wu
7d1a4d2fb6 net/txgbe: add security type in flow action
Add security type in flow action.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
2021-01-13 18:51:58 +01:00
Jiawen Wu
d51a133cc7 net/txgbe: add security offload in Rx and Tx
Add security offload in Rx and Tx process.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
2021-01-13 18:51:58 +01:00
Jiawen Wu
87d8a2a4a8 net/txgbe: destroy security session
Add support to clear a security session's private data,
get the size of a security session,
add update the mbuf with provided metadata.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
2021-01-13 18:51:58 +01:00
Jiawen Wu
07cafb2adb net/txgbe: add security session create operation
Add support to configure a security session.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
2021-01-13 18:51:58 +01:00
Jiawen Wu
f437d97c3d net/txgbe: add IPsec context creation
Initialize securiry context, and add support to get
security capabilities.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
2021-01-13 18:51:58 +01:00
Jiawen Wu
1784c5f947 net/txgbe: add TM hierarchy commit
Add traffic manager hierarchy commit.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
2021-01-13 18:51:58 +01:00
Jiawen Wu
0611a69bb7 net/txgbe: support TM node add and delete
Support traffic manager node add and delete operations.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
2021-01-13 18:51:58 +01:00
Jiawen Wu
c0edeccdbd net/txgbe: support TM shaper profile add and delete
Support traffic manager profile add and delete operations.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
2021-01-13 18:51:58 +01:00