Right now a PMD decides if it is critical that an offload cannot
be disabled (i.e. not requested, but still enabled). If PMD treaks
it as OK, we should not spam logs with corresponding messages
by default. Default log level in ethdev is INFO, so change the
message level to DEBUG.
Fixes: 1daa338058 ("ethdev: validate offloads set by PMD")
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
By default RSS hash delivery (offload) is bound to RSS mode and
it is incorrect to advertise it as enabled if Rx multi-queue mode
has no RSS.
Fixes: 8b945a7f7d ("drivers/net: update Rx RSS hash offload capabilities")
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Add support to set supported ptypes for octeontx2 and
remove devarg scheme to disable ptype parsing support as
application can use rte_eth_dev_set_ptypes() normative API
to enable the same use case.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Issue has been observed if PTP is already enabled on PF and
later VFs are configured. Since PTP requires mbuf data off
to be shifted by 8 bytes, due to this l3fwd/l2fwd was not
working with VFs.
Also some extra garbage bytes were observed in packet data
when ptp was enabled.
Fixes: b5dc314044 ("net/octeontx2: support base PTP")
Cc: stable@dpdk.org
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
After otx2_nix_register_cq_irqs() is called and the IRQs are setup,
otx2_nix_unregister_cq_irqs() need to be called in the subsequent error
exit paths.
Fixes: d34db5ccbf ("net/octeontx2: fix driver reconfiguration")
Cc: stable@dpdk.org
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Retrieve burst mode information according to the selected Rx/Tx mode and
offloads.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Update "mbuf->ol_flags" correctly for 'Checksum Unknown' errors
for both tunneled and non-tunneled IP packets.
Fixes: b875339622 ("net/bnxt: fix L4 checksum indication in non-vector Rx")
Cc: stable@dpdk.org
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Fix missing new line token at the end of log.
Fixes: 5d30897295 ("ethdev: add mbuf RSS update as an offload")
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Introducing new register and unregister API for ifpga interrupt.
1. register FME and AFU interrupt
ifpga_register_msix_irq()
2. unregister FME and AFU interrupt
ifpga_unregister_msix_irq()
On PAC N3000 card, there is one PCIe MSIX interrupt for FME management,
like the error report, thermal management, we use this interrupt in
ifpga_rawdev device driver. on the other hand, there are about 4 PCIe
MSIX interrupts are reserved for AFU which end-user can use those
interrupts in their AFU logic design. End-user can use those APIs to
register interrupt handler in their AFU drivers.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
In PAC N3000 card, there is one MAX10 chip in each card, and
all of the sensors are connected to MAX10 chip. To support multiple
cards in one server, we introducing a sensor device list under
intel_max10_device instead of a global list. On the other hand, we
using separate intel_max10_device instance for each opae_adatper.
Add mutex lock on do_transaction() function for SPI driver to avoid
race condition.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
Add new API to get the board info.
opae_mgr_get_board_info()
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
We can change the PKVL FEC mode when the A10 NIOS FW
initialization. The end-user can use this feature the
change the FEC mode, the default mode is RS FEC mode.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
In PAC N3000 Card, MAX10 Board Management Controller (BMC) implements
the security functionality.
Security functionality adds secure Remote System Update (RSU)
authentication and integrity checks for FPGA flat image,
and FW updates to the card.
This patch adds security feature support for MAX10, in secure solution
some registers and the content of the Device Tree changes.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
The ipn3ke board FPGA and i40e BDF scan has added in ifpga_rawdev,
so it doesn't need to provide configuration for i40e port bonding.
Signed-off-by: Rosen Xu <rosen.xu@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
Add SEU interrupt support for FPGA.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Rosen Xu <rosen.xu@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
The sensor devices are connected in MAX10 FPGA. we used the
device tree to describe those sensor devices. Parse the device
tree to get the sensor devices and add them into a list.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
The length of send buffer of SPI bus should be 4bytes align.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
In PAC N3000 card, this is a BMC chip which using MAX10 FPGA
to manage the board configuration, like sensors, flash controller,
QSFP, powers. And this is a SPI bus connected between A10 FPGA and
MAX10, we can access the MAX10 registers over this SPI bus.
In BMC, there are about 19 sensors in MAX10 chip, including the FPGA
core temperature, Board temperature, board current, voltage and so on.
We use DTB (Device tree table) to describe it. This DTB file is store
in nor flash partition, which will flashed in Factory when the boards
delivery to customers. And the same time, the customers can easy to
customize the BMC configuration like change the sensors.
Add device tree support by using libfdt library in Linux distribution.
The end-user should pre-install the libfdt and libfdt-devel package
before use DPDK on PAC N3000 Card.
For Centos 7.x: sudo yum install libfdt libfdt-devel
For Ubuntu 18.04: sudo apt install libfdt-dev libfdt1
To eliminate build error, we currently do not compile raw/ifpga
and net/ipn3ke. User should install libfdt and libfdt-devel first,
modify config/common_linux, CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=n
to CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y, modify config/common_base,
CONFIG_RTE_LIBRTE_IPN3KE_PMD=n to CONFIG_RTE_LIBRTE_IPN3KE_PMD=y.
Then this function can work.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
This patch exposes SEU error information to application then application
could compare this information (128bit) with its own SMH file to know
if this SEU is a fatal error or not.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
Every defined bit in FME_ERROR0 is RW1C. Other reserved bits are always
0 when readout and it will plan to be RW1C if needed in future.
So it is safe just write the read back value to clear all the errors.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
Add IRQ support for ifpga FME global error, port error and unit.
We implemented this feature by vfio interrupt mechanism.
To build this feature, CONFIG_RTE_EAL_VFIO should be enabled.
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
In ipn3ke, each FPGA network side port bonding to an i40e pf,
each i40e pf link status should get data from FPGA network,
side port. This patch provide bonding relationship.
Signed-off-by: Rosen Xu <rosen.xu@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
The kernel driver (starting from OFED 4.7.3.1.3) uses the upper half
of metadata register C0 to provide VHCA and vport id's. The mlx5 PMD
should check the actual mask of register C0 and shift the vport id
value for port actions appropriately.
Fixes: f07341e7ae ("net/mlx5: update source and destination vport translations")
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The state of environment variable MLX5_BF_SHUT_UP was not
recovered correctly if there was no tx_db_nc devarg specified.
Fixes: 8409a28573 ("net/mlx5: control transmit doorbell register mapping")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Fixes: 84dc7a95a2 ("net/ice: enable flow director engine")
Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Currently, multiple rte_flow RSS rules may map to the same
hardware rule if a later rule is just for input set change or
symm turn on/off. So after one of the rules be destroyed, we will
get error ICE_ERR_DOES_NOT_EXIST when destroying any other rules.
The patch simply fixes this by ignoring this error. A more
sophisticated fix that remember the sequence and replay properly
will be provided in the future.
Fixes: 5ad3db8d4b ("net/ice: enable advanced RSS")
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
In ice_hash_create(), whatever the hash_function is, the
filter_ptr->symm is always 0 and when we destroy the flow, the
ice_rem_rss_cfg() is never carried out. So the destroy function never
works well. The patch fixes this issue and at the same time
distinguishes between simple_xor and symmetric_toeplitz.
To fix this issue, the patch adds a new structure to include a flag to
indicate if it is a simple_xor flow so that it's easier to remove the
config when destroying the flow. The patch also simplifies code
implementation logic in ice_hash_create().
Fixes: 5ad3db8d4b ("net/ice: enable advanced RSS")
Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Null-checking "rxq" suggests that it may be null, but it has already
been dereferenced on all paths leading to the check.
Refactored the code to address this issue.
Coverity issue: 350594
Fixes: fc4bfea596 ("net/bnxt: fix Rx queue start/stop for Thor based NICs")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
When an existing mac_addr is tried to get programmed again, a
message is displayed that the mac_addr already exists.
However the message is of type ERR. This patch changes the message
to type DEBUG
Fixes: 938a87db43 ("net/bnxt: fix redundant MAC address check")
Cc: stable@dpdk.org
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
We would hit a segfault in bnxt_dev_xstats_get_op() if xstats argument
is NULL, Check if the argument is NULL and return appropriately.
Fixes: bfb9c2260b ("net/bnxt: support xstats get/reset")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Andy Gospodarek <gospo@broadcom.com>
In non-RSS mode, vnics map 1:1 with Rx queues during init. This can
create problems if non-consecutive group IDs are given as part of
subsequent flow create cmds as they can end up pointing to Rx queues
(mapped during init) that are different than the intended destination
queue as specified in the flow create cmd.
To fix this, now that we have the ability to dynamically create
vnics, do not create any additional vnics other than the default vnic
during init. Allocate them only during flow/filter creation time.
When RSS is disabled we need to use the COS queue count queried
from firmware.
Fixes: 36024b2e7f ("net/bnxt: allow dynamic creation of VNIC")
Signed-off-by: Rahul Gupta <rahul.gupta@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Cap max queue count to 128 for NS3 devices and ensure that same count
is reported as part of dev_info_get_op as well
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Rahul Gupta <rahul.gupta@broadcom.com>
Driver should fail the eth_dev_ops callbacks and accessing
Tx and Rx queues when device is in reset or in error state.
Added missing checks for fw reset in few routines.
Fixes: be14720def ("net/bnxt: support FW reset")
Reviewed-by: Santoshkumar Karanappa Rastapur <santosh.rastapur@broadcom.com>
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
The layer bits should be unique otherwise layer info will be
interpreted wrongly.
Fixes: 70d84dc797 ("net/mlx5: add internal tag item and action")
Fixes: 55deee1715 ("net/mlx5: extend flow mark support")
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Function flow_verbs_counter_query() was recently modified.
The new 'if' condition uses a pointer to flow counter-set.
This pointer is valid only if flow contains a count action.
This patch adds check to verify the pointer is valid.
Fixes: d85c7b5ea5 ("net/mlx5: split hairpin flows")
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Function mlx5_rxq_get_type() uses the input queue index, without
checking it, as index to the Rx queues array.
If this value is too high, it will result in pointer to memory out
of Rx queues array bounds.
This patch adds check of the input queue index, to verify it is valid.
Fixes: d85c7b5ea5 ("net/mlx5: split hairpin flows")
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The variable cleanup was erroneously done before pointer usage.
The cleanup is moved to appropriate place, comment is clarified.
Fixes: 8d72fa6689 ("net/mlx5: share tag between meter and metadata")
Reported-by: Eli Britstein <elibr@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
This reverts commit 304ffe576f.
It tried to optimize the amount of the default flow
rules and created it only once on top of the PF representor.
For each FDB rule, the default port ID to match on is like of the port
that triggers the flow.
Hence, the single default rule will not be matched on the VF traffic.
As a result, all the traffic of the VFs will not match to the jump flow
in the root table and will always be forwarded to the representor port.
Revert the commit.
Fixes: 304ffe576f ("net/mlx5: fix condition to create default rule")
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
To avoid wild pointer, pointers should be set to NULL after free them.
Fixes: 1a2fc1799f ("net/ice: reject duplicated flow for flow director")
Fixes: 84dc7a95a2 ("net/ice: enable flow director engine")
Fixes: 0f880c3df1 ("net/ice: add flow director counter resource init/release")
Signed-off-by: Shougang Wang <shougangx.wang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
All the counter resources should be cleaned up when teardown.
Fixes: 0f880c3df1 ("net/ice: add flow director counter resource init/release")
Signed-off-by: Shougang Wang <shougangx.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
The removal of FDIR profile should start from the next
of ICE_FLTR_PTYPE_NONF_NONE.
Fixes: 109e8e0624 ("net/ice: configure HW flow director rule")
Signed-off-by: Shougang Wang <shougangx.wang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
To avoid memzone reserve failure and memory leak, following
resources management should be added.
- Check if the FDIR Memzone already exists before reserving.
- Free FDIR memzone when teardown and other failure scenarios.
Fixes: 84dc7a95a2 ("net/ice: enable flow director engine")
Signed-off-by: Shougang Wang <shougangx.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Correct an error in the IPV6 header bitmask used for programming switch
rules.
Also, change other programming switch headers to use big endian
fields in order to make setting these easier.
Fixes: 04b8ec1ea8 ("net/ice/base: add protocol structures and defines")
Cc: stable@dpdk.org
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
When compiling with 16B descriptor support enabled, clang compiles gave
an error, complaining that the final parameter of _mm256_blend_epi32()
had to be an immediate value (i.e. compile-time constant):
i40e_rxtx_vec_avx2.c:561:21: error: argument to
'__builtin_ia32_pblendd256' must be a constant integer
__m256i tmp0_1 = _mm256_blend_epi32(fdir_zero_mask,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
While it appears that GCC was able to convert the constant variable
value "fdir_blend_mask" into the blend call, clang was not doing so. To
guarantee the use of an immediate we convert the variable value to a
"#define".
Fixes: 7d087a0a8b ("net/i40e: support flow director on AVX Rx")
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Fix iavf vf_checksum_sw case fail in X710/XXV710, set bit2 to 1
of CMD field in Tx descriptor of AVX Tx path according to Spec.
Fixes: af0c246a38 ("net/iavf: enable AVX2 for iavf")
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
