Commit Graph

15 Commits

Author SHA1 Message Date
Qi Zhang
97f4f78bbd net/ice/base: add functions for device clock control
The ice hardware supports exposing a hardware clock for high precision
timestamping. This is primarily intended for accelerating the Precision
Time Protocol.

Add several low level functions intended to be used as the basis for
enabling the device clock, and ensuring that the port timers are
synchronized properly.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-08-11 04:23:18 +02:00
Qi Zhang
d84e220a8d net/ice/base: update copyright date
Updated the Copyright for 2021
Updated ice driver version.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-08 19:03:09 +01:00
Qi Zhang
36a7d65eb5 net/ice/base: cleanup style
A few style issues reported by checkpatch have snuck into the code,
resolve the style issues.

PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
2021-01-08 19:03:08 +01:00
Qi Zhang
484d2637a4 net/ice/base: remove unused struct member
The only time you can ever have a rq_last_status is if
a firmware event was somehow reporting a status on the receive
queue, which are generally firmware initiated events or
mailbox messages from a VF.  Mostly this struct member was unused.

Fix this problem by still printing the value of the field in a debug
print, but don't store the value forever in a struct, potentially
creating opportunities for callers to use the wrong struct member.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2021-01-08 16:03:06 +01:00
Qi Zhang
64589777b9 net/ice/base: increase control queue timeout
250 msec timeout is insufficient for some AQ commands. Advice from FW
team was to increase the timeout. Increased to 1 second.

Signed-off-by: Fabio Pricoco <fabio.pricoco@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2021-01-08 16:03:06 +01:00
Xiaoyun Li
dc496974cd net/ice/base: update copyright
Clarify Intel copyright and update the date to 2020.

Fixes: f3202a097f ("net/ice/base: add ACL module")
Fixes: a90fae1d07 ("net/ice/base: add admin queue structures and commands")
Fixes: 2d2bdc0267 ("net/ice/base: add various headers")
Fixes: c9e37832c9 ("net/ice/base: rework on bit ops")
Fixes: 453d087cca ("net/ice/base: add common functions")
Fixes: 6c1f26be50 ("net/ice/base: add control queue information")
Fixes: 1082f78654 ("net/ice/base: support DCB")
Fixes: 6aa406714a ("net/ice/base: add device IDs for Intel E800 Series NICs")
Fixes: bd984f155f ("net/ice/base: support FDIR")
Fixes: 51d04e4933 ("net/ice/base: add flexible pipeline module")
Fixes: 2d2bdc0267 ("net/ice/base: add various headers")
Fixes: aa1cd410fa ("net/ice/base: add flow module")
Fixes: 51c7f09f3f ("net/ice/base: add registers for Intel E800 Series NIC")
Fixes: 64e9587d56 ("net/ice/base: add structures for Rx/Tx queues")
Fixes: 557fa75bcf ("net/ice/base: add code to work with the NVM")
Fixes: b06499a433 ("net/ice/base: update Boot Configuration Section read of NVM")
Fixes: 04b8ec1ea8 ("net/ice/base: add protocol structures and defines")
Fixes: 2a27e0a16d ("net/ice/base: add sideband queue info")
Fixes: 93e84b1bfc ("net/ice/base: add basic Tx scheduler")
Fixes: c7dd159311 ("net/ice/base: add virtual switch code")
Fixes: a240ff5050 ("net/ice/base: add basic structures")
Cc: stable@dpdk.org

Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2020-05-18 20:35:57 +02:00
Qi Zhang
af0d0df350 net/ice/base: handle critical FW error
A race condition between FW and SW can occur between admin queue setup
and the first command sent. A link event may occur and FW attempts to
notify a non-existent queue. FW will set the critical error bit and
disable the queue. When this happens retry queue setup.

Signed-off-by: Evan Swanson <evan.swanson@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-04-21 13:57:05 +02:00
Qi Zhang
e0b977dddb net/ice/base: update copyright date
Update copyright date to 2020.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2020-04-21 13:57:05 +02:00
Qi Zhang
29897f43a1 net/ice/base: update FW API minor version
Update FW API minor version to align to current value advertised
by FW in NVM images.

Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2019-10-07 15:00:56 +02:00
Qi Zhang
6b1172d4dc net/ice/base: remove redundant empty lines
Remove redundant empty lines

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2019-10-07 15:00:55 +02:00
Qi Zhang
fc882012b3 net/ice/base: delay less
Shorten the delay for SQ responses, but increase the number of loops.
Max delay time is unchanged, but some operations complete much more
quickly.

In the process, add a new define to make the delay count and delay time
more explicit, and simplify the code so it's the same for both switch
and NIC mode. Add comments to make things more explicit.

Signed-off-by: Mitch Williams <mitch.a.williams@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Qi Zhang
6632c0556d net/ice/base: correct abbreviations
Correct abbreviation issues found by running abbrevcheck.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2019-10-07 15:00:53 +02:00
Leyi Rong
9396e6dab5 net/ice/base: optimize data structures
Move a bunch of members around to make more efficient use of
memory, eliminating holes where possible. None of these members
are hot path so cache line alignment is not very important here.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2019-06-28 20:31:48 +02:00
Qi Zhang
abd6cd540e net/ice/base: update copyright time
Update copyright time to 2019.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Qiming Yang <qiming.yang@intel.com>
Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
2019-03-29 17:25:31 +01:00
Paul M Stillwell Jr
6c1f26be50 net/ice/base: add control queue information
Add the structures for the control queues.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2018-12-21 16:22:40 +01:00