years for head. However, it is continuously misused as the mpsafe argument
for callout_init(9). Deprecate the flag and clean up callout_init() calls
to make them more consistent.
Differential Revision: https://reviews.freebsd.org/D2613
Reviewed by: jhb
MFC after: 2 weeks
files to vendor-provided ones. It should make easier to adopt platform
code to new revisions of hardware and to use DTS overlays for various
Beaglebone extensions (shields/capes).
Original dts filenames were not changed, they're now wrappers over dts
files provided by TI. So make sure you update .dtb files on your
devices as part of kernel update
GPIO addressing was changed: instead of one global /dev/gpioc0 there
are per-bank instances of /dev/gpiocX. Each bank has 32 pins so for
instance pin 121 on /dev/gpioc0 in old addressing scheme is now pin 25
on /dev/gpioc3
On Pandaboard serial console devices was changed from /dev/ttyu0 to
/dev/ttyu2 so you'll have to update /etc/ttys to get login prompt
on serial port in multiuser mode. Single user mode serial console
should work as-is
Differential Revision: https://reviews.freebsd.org/D2146
Reviewed by: rpaulo, ian, Michal Meloun, Svatopluk Kraus
This is based on the patch sent by Alexander Fedorov with the following
fixes/improvements:
- Better error handling;
- Clock is derived from PLL6 (obtained from netbsd);
- No more unnecessary busy loops on interrupt handler;
- style(9) fixes and code cleanup.
I also want to thanks Martin Galvan who has sent an alternative
implementation with some interesting fixes.
Tested on CubieBoard2, Banana-Pi (thanks to netgate!) and Cubieboard1
(Pratik Singhal).
This is intended to pave the way for the upcoming GSoC work (and make
easier the build of images for the supported boards).
PR: 196081
Submitted by: Alexander Fedorov <alexander.fedorov@rtlservice.com>
The replacement started at r283088 was necessarily incomplete without
replacing boolean_t with bool. This also involved cleaning some type
mismatches and ansifying old C function declarations.
Pointed out by: bde
Discussed with: bde, ian, jhb
determined at runtime so there's no need to set the values in
each DTS.
Tested on YYHD18 (aml8726-m3), VSATV102 (aml8726-m6), and
ODROIDC1 (aml8726-m8b).
Differential Revision: https://reviews.freebsd.org/D2588
Submitted by: John Wehle
of AML8726 and into board specific config files since some boards
(e.g. YYHD18) use the aml8726-m3 which only have a single core.
r283057 applied most of D2432, however while it removed SMP from
AML8726, it missed adding the SMP option to the board specific
config files.
Differential Revision: https://reviews.freebsd.org/D2589
Submitted by: John Wehle
we have both the Amlogic pic and a GIC. This may be the case in some
configurations.
Differential Revision: https://reviews.freebsd.org/D2432
Submitted by: John Wehle <john@feith.com>
1. Align to a 64-bit address so 64-bit data will be correctly aligned.
2. Add a comment explaining why.
3. Remove an unneeded value from the struct.
This fixes an issue where the struct may not be correctly aligned on the
stack in the syscall function. This may lead to accesing a 64-bit value
at a non 64-bit. This will raise an exception and panic the kernel.
We have been lucky where on arm and armv6 both clang and gcc correctly
align the data, even without us asking to, however, on armeb with clang to
not be the case. This tells the compiler we really do need this to be
aligned.
Reported and tested by: jmg (on armeb with clang)
MFC after: 1 Week [1, 2]
when loader(8) passed physical addresses in loader metadata for arm, but
that is no longer true; all metadata has already been adjusted to vitual
addresses by loader.
I can't track down the exact revision in loader where a change from physical
to virtual metadata addresses happened. The code involved is very twisty
and complicated. I suspect the change was an unintended consequence of the
r247301, r247413, r248118 series of changes I made a couple years ago.
comment to this effect and switch the default. My old AT91SAM9G20
now boots, fsck's the SD card and runs w/o an issue for the first
time since a 9.1-ish stable build I did a few years ago.
Problems with unmapped I/O:
o un-page-aligned I/O requests to devices fail (notably fsck
and newfs).
o write-back caching was totally broken. write-through caching
needed to be enabled.
o Even page-aligned I/O requests sometimes failed for reasons
not thoroughly investigated.
Suggested by: ian@
MFC after: 2 days
The Alpine Platform-On-Chip offers multicore processing
(quad ARM Cortex-A15), 1/10Gb Ethernet, SATA 3, PCI-E 3,
DMA engines, Virtualization, Advanced Power Management and other.
This code drop involves basic platform support including:
SMP, IRQs, SerDes, SATA. As of now it is missing the PCIe support.
Part of the functionality is provided by the low-level code (HAL)
delivered by the chip vendor (Annapurna Labs) and is a subject to
change in the future (is planned to be moved to sys/contrib directory).
The review log for this commit is available here:
https://reviews.freebsd.org/D2340
Reviewed by: andrew, ian, imp
Obtained from: Semihalf
Sponsored by: Annapurna Labs
Perform cache writebacks and invalidations in the correct (inner to outer
or vice versa) order, and add comments that explain that.
Consistantly use 'va' as the variable name for virtual addresses.
Submitted by: Michal Meloun <meloun@miracle.cz>
For consistency with the naming conventions used by the other
implementations kill armv7_sleep and keep armv7_cpu_sleep.
Differential Revision: https://reviews.freebsd.org/D2537
Submitted by: John Wehle
Reviewed by: ian@, andrew@
The consumers of hw.intrnames expect a NULL byte at end of the string
containing the interrupt names.
On ARM all the interrupt name slots are initialized and this leave no room
for the terminating NULL byte, which makes vmstat read beyond the end of
intrnames.
PR: 199891
Tested on: RPi 2 and BeagleBone Black
The aml8726-m3 SoC is identified as a Cortex A9-r2 rev 4 CPU and
it hangs sometimes during the boot when WFI is used by the kernel.
Differential Revision: https://reviews.freebsd.org/D2473
Submitted by: John Wehle
Suggested by: ian@
because the i386 pmap on which the new armv6 pmap is based had it, and in
r281707 pmap_lazyfix() was removed from the i386 pmap.
Discussed with: kib
Submitted by: Michal Meloun (via Svatopluk Kraus)
main ARMv6 target, the Raspberry Pi, doesn't support Thumb-2.
This as been tested with a Thumb-2 userland, however building one is
currently unsupported as there are known toolchain issues breaking some
binaries. Further work will also be needed to decide on the method of
selecting which instruction set to build for, and to benchmark both to
find how building everything as Thumb-2 will affect performance.
Relnotes: yes
Of note:
- This commit adds native FreeBSD/arm release build support without
requiring out-of-tree utilities.
- Part of this merge removes the WANDBOARD-{SOLO,DUAL,QUAD} kernel
configuration files, for which the IMX6 kernel configuration file
should be used instead.
- The resulting images have a 'freebsd' user (password 'freebsd'),
to allow ssh(1) access when console access is not available (VGA
or serial). The default 'root' user password is set to 'root'.
- The /etc/ttys file for arm images now enable both ttyv0 and ttyu0
by default.
Help from: many (boot testing, feedback, etc.)
Sponsored by: The FreeBSD Foundation
since it supports all of these board variants.
While here, remove the WANDBOARD-{QUAD,SOLO,DUAL} kernel
configuration files.
Discussed with: ian
Sponsored by: The FreeBSD Foundation
Offet for the power control register was specified incorrectly (it had
the same value as the prefetch control register.) This change corrects
the offset value to 0xF80, per the ARM PL310 documentation.
Submitted by: Steve Kiernan <stevek@juniper.net>
Obtained from: Juniper Networks, Inc.
available on the aml8726-m6 (and later) SoC which allows for
lower speeds.
Differential Revision: https://reviews.freebsd.org/D2433
Submitted by: John Wehle
each of the existing kernel configs. This gives a place to put config
that applies to the entire arch.
Add the ARM_NEW_PMAP option to std.armv6. This is working well in early
testing and it's time for wide exposure, but it's still nice to be able
to fall back to the old implementation for testing when a problem comes
along. Eventually the option and the old implementation will go away.
The opportunity now exists to move a whole lot of boilerplate from all the
arm kernel config files into std.arm*, but that's a commit for another day.
Use the BCM2835_MBOX_CHAN_PROP mbox channel to setup the framebuffer,
remove DMA code (its now done in bcm2835_mbox.c).
Also adjust the color palette when bcm2708_fb.fbswap is set. The
firmware used on RPi 2 uses this mode.
Tested on: RPi-B and RPi 2 with 16, 24 and 32bpp
Note: The 32bpp mode on RPi-B has the red and blue swapped, this
is a know problem (not a driver problem).
Use the BCM2835_MBOX_CHAN_PROP mbox channel to setup the framebuffer,
remove unused code and unnecessary includes.
Adjust the color palette when bcm2708_fb.fbswap is set on /chosen/bootargs
node of DTB. The firmware used on RPi 2 uses this mode.
Tested on: RPi-B and RPi 2 with 16, 24 and 32bpp
BCM2835_MBOX_CHAN_PROP channel. The old channel (BCM2835_MBOX_CHAN_FB)
seems deprecated on recent firmware versions and is causing a freeze on
RPi 2.
The actual changes in the framebuffer drivers will follow in subsequent
commits.
1) Advertise the actual min / max speeds the hardware is capable
of supporting given the reference clock used by the board.
2) Rather than attempting to extend the hardware's timeout register
in software (the hardware doesn't have sufficient bits to directly
support long timeouts), simply implement the same timeout approach
used in the SDXC driver.
3) Set the timeout for a linked command (e.g. STOP TRANSMISSION) based
on the previous multiblock read / write.
The changes have been smoke tested on both the ODROID-C1 and the VSATV102-M6
using the following cards:
* PQI 2GB microSD
* SanDisk 2GB microSD
* PQI 8GB SDHC (not a microSD so only tested on the ATV-102)
* PNY 8GB microSDHC
* SanDisk Ultra 32GB microSDHC
Submitted by: John Wehle
pages which pass a NULL virtual address. If the BUS_DMA_KEEP_PG_OFFSET
flag is set, use the physical address to compute the page offset
instead. The physical address should always be valid when adding
bounce pages and should contain the same page offset like the virtual
address.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
MFC after: 1 week
Reviewed by: jhb@
into the kernel, which is used mostly on early development stages.
On RPI(2) the DTB is loaded and modified by firmware and then handed to
kernel via U-Boot and ubldr.
The RPI firmware adds (or modify) a few valuable data to the in memory
DTB, like:
- System memory;
- Ethernet MAC address;
- framebuffer settings;
- Board serial and revision;
- clock-frequency for most of devices.
Each TX queue can hold one packet (yes, if_emac can send only two(!)
packets at a time).
Even with this change the very limited FIFO buffer (3 KiB for TX and 13 KiB
for RX) fill up too quick to sustain higher throughput.
For the TCP case it turns out that TX isn't the limiting factor, but the RX
side is (the FIFO fill up and starts to discard packets, so the sender has
to slow down).
Do not strip the ethernet CRC until we read all data from FIFO, otherwise
the CRC bytes would be left in FIFO causing the failure of next packet
(wrong packet header).
When this error happens the receiver has to be disabled and the RX FIFO
flushed, discarding valid packets.
With this fix if_emac behaves a lot better.
There are a few differences between the two. On arm we need to provide a
list of addresses we may be mapping before we have initialised the virtual
memory subsystem, however on arm64 we allocate a small (2MiB for a 4k
granule) range to be used for such purposes.
Differential Revision: https://reviews.freebsd.org/D2249
Sponsored by: The FreeBSD Foundation
handles versions 0.1 and 0.2 of the standard on 32-bit ARM.
With this driver we can shutdown in QEMU. Further work is needed to
turn secondary cores on on boot and to support later revisions of the
specification.
Submitted by: Robin Randhawa <Robin.Randhawa at ARM.com>
Sponsored by: The FreeBSD Foundation
This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the registers at 4-byte
addresses meaning the value should be 2.
This patch fixes this for the pl011 when configured using the fdt. The
other drivers have a default value of 0 to keep this a no-op.
MFC after: 1 week
supply clk81 information. It also changes the hardware strings
in some of the drivers to match what's present in the GNU files.
Submitted by: John Wehle
Reviewed by: imp
Previously we used pmap_kremove(), but with ARM_NEW_PMAP it does the remove
in a way that isn't SMP-coherent (which is appropriate in some circumstances
such as mapping/unmapping sf buffers). With matching enter/remove routines
for device mappings, each low-level implementation can do the right thing.
Reviewed by: Svatopluk Kraus <onwahe@gmail.com>
- Add macros to handle the differences in accessing these registers on arm
and arm64.
- Use the fdt data to detect if we are on an ARMv7 or ARMv8.
- Use the virtual timer by default on arm64, we may not have access to
the physical timer.
Differential Revision: https://reviews.freebsd.org/D2208
Reviewed by: emaste
Sponsored by: The FreeBSD Foundation
not have interupt property in pl310 node. Interrupt is used only to
detect cache activity when L2 cache is disabled, it's not vital for
normal operations.
- Fix intrhook allocation/initialization
specially aml8726-m6 and aml8726-m8b SoC based devices.
aml8726-m6 SoC exist in devices such as Visson ATV-102.
Hardkernel ODROID-C1 board has aml8726-m8b SoC.
The following support is included:
Basic machdep code
SMP
Interrupt controller
Clock control driver (aka gate)
Pinctrl
Timer
Real time clock
UART
GPIO
I2C
SD controller
SDXC controller
USB
Watchdog
Random number generator
PLL / Clock frequency measurement
Frame buffer
Submitted by: John Wehle
Approved by: stas (mentor)
the PMC_IN_KERNEL() macro definition.
Add missing macros to extract the return address (LR) from the trapframe.
Discussed with: andrew
Obtained from: Cambridge/L41
Sponsored by: DARPA, AFRL
MFC after: 2 weeks
This is pretty much a complete rewrite based on the existing i386 code. The
patches have been circulating for a couple years and have been looked at by
plenty of people, but I'm not putting anybody on the hook as having reviewed
this in any formal sense except myself.
After this has gotten wider testing from the user community, ARM_NEW_PMAP
will become the default and various dregs of the old pmap code will be
removed.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>
the startup trampoline code. The old code allocated a kva page, mapped it
using using pmap_kenter_nocache(), then freed the kva without destroying
the mapping. This is the only use of pmap_kenter_nocache() in the system,
so redoing this one use of allows it to be garbage collected in the
near future.
the Raspberry Pi B we support most of the devices are already supported,
however the base address has changed.
A few items are not working, or missing. The main ones are:
* DMA doesn't work in the sdhci driver.
* Enabling vchiq halts the boot, may be interrupt related.
* There is no U-Boot port yet so the DTB is embedded in the kernel.
The last point will make it difficult to boot FreeBSD, however there is
support for the Raspberry Pi 2 in the U-Boot git repo. As I have not tested
this it is left as an open task to create a port to build.
X-MFC: When the above issues are fixed
Sponsored by: ABT Systems Ltd
we're not looking at it.
Fix this by increasing l2->l2_occupancy before we try to alloc (and decrease
it if the allocation failed, or if another thread did a similar allocation).
Submitted by: Kohji Okuno <okuno.kohji@jp.panasonic.com>
MFC after: 1 week
to get the default frequency of the sdhci device.
While here use a u_int to hold the frequency as it may be too large to fit
in a 32-bit signed integer. This is the case when we have a 250MHz clock.
Each plaform performs virtual memory split between kernel and user space
and assigns kernel certain amount of memory space. However, is is sometimes
reasonable to change the default values. Such situation may happen on
systems where the demand for kernel buffers is high, many devices occupying
memory etc. This of course comes with the cost of decreasing user space
memory range so shall be used with care. Most embedded systems will not
suffer from this limtation but rather take advantage of this potential
since default behavior is left unchanged.
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: imp
Obtained from: Semihalf
These are left over from long ago when there was no way to load modules
on early armv6 platforms, and when there was a build problem with ahc
that has long since been fixed, and they just keep getting copy-pasted
into new configs.
ntpd is hard-coded to use /dev/ppsN, and typically when multiple PPS sources
are available the sysadmin will symlink the right one(s) to /dev/ppsN, so
it's best to not usurp those names directly.
Also ensure dsb precedes isb in all icache maintenance routines (first
do a data sync, then stall the instruction stream until it finishes).
Submitted by: Michal Meloun
been done by U-Boot. This allows the USB to work when we load the kernel
directly.
No dma sync is performed after these operations as the data we read/write
is not used by the cpu after the calls to the maimbox driver.
Differential Revision: https://reviews.freebsd.org/D1940
Reviewed by: imp, Michal Meloun (meloun AT miracle.cz)
MFC after: 1 Week
Sponsored by: ABT Systems Ltd
both the post-filter and post-thread callbacks.
Also eliminate a completely unecessary write to INTC_ISR_CLEAR register,
which clears a software-generated interrupt that can only happen with a
write to INTC_ISR_SET (which nothing does).
uart implementations, and export them using the new linker-set mechanism.
Differential Revision: https://reviews.freebsd.org/D1993
Submitted by: Michal Meloun
PL (programmable logic) uses FCLK0..FCLK3 as a clock sources.
Normally they're configured by first stage boot loader (FSBL)
and normal user never has to touch them. These sysctls may come
useful for hardware developers
hw.fpga.fclk.N.source: clock source (IO, DDR, ARM)
hw.fpga.fclk.N.freq: requested frequency in Hz
hw.fpga.fclk.N.actual_freq: actual frequency in Hz (R/O)
hw.fgpa.level_shifters: 0/1 to enable/disable PS-PL level shifters,
normally they're enabled either by FSBL or after programming
FPGA through devcfg(4)
emulate the instructions used in function entry and exit.
For function entry ARM will use a push instruction to push up to 16
registers to the stack. While we don't expect all 16 to be used we need to
handle any combination the compiler may generate, even if it doesn't make
sense (e.g. pushing the program counter).
On function return we will either have a pop or branch instruction. The
former is similar to the push instruction, but with care to make sure we
update the stack pointer and program counter correctly in the cases they
are either in the list of registers or not. For branch we need to take the
24-bit offset, sign-extend it, and add that number of 4-byte words to the
program counter. Care needs to be taken as, due to historical reasons, the
address the branch is relative to is not the current instruction, but 8
bytes later.
This allows us to use the following probes on ARM boards:
dtrace -n 'fbt::malloc:entry { stack() }'
and
dtrace -n 'fbt:🆓return { stack() }'
Differential Revision: https://reviews.freebsd.org/D2007
Reviewed by: gnn, rpaulo
Sponsored by: ABT Systems Ltd
the translation table (this may be left over from armv5 days). It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.
Submitted by: Michal Meloun
used by other places that expect to unwind the stack, e.g. dtrace and
stack(9).
As I have written most of this code I'm changing the license to the
standard FreeBSD license. I have received approval from the other
developers who have changed any of the affected code.
Approved by: ian, imp, rpaulo, eadler (all license change)
Switch the cache line size during invalidations/flushes
to be read from CP15 cache type register.
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: ian, imp
Obtained from: Semihalf
