- Initialize lock before starting worker process
- Do not hold lock when destroying evdev. By that time ther should be no
other active code pathes that can access softc
- Convert "options EVDEV" to "device evdev" and "device uinput", add
modules for both new devices. They are isolated subsystems and do not
require any compile-time changes to general kernel subsytems
- For hybrid drivers that have evdev as an optional way to deliver input
events add option EVDEV_SUPPORT. Update all existing hybrid drivers
to use it instead of EVDEV
- Remove no-op DECLARE_MODULE in evdev, it's not required, MODULE_VERSION
is enough
- Add evdev module dependency to uinput
Submitted by: Vladimir Kondratiev <wulf@cicgroup.ru>
VM_MEMATTR_WRITE_COMBINING sets write-through cache flag for framebuffer
memory that prevents pixel data from being stuck in cache until evicition
happens
100 cycles per us seems accurate enough, at least it's better than the 200 value
that was used before.
Reviewed by: andrew, imp
Differential Revision: https://reviews.freebsd.org/D8062
Technically touchscreen chip is FT5406 but all hardware
communication is performed by VideCore and only final results
are presented to ARM part through memory region shared between
VC and ARM.
evdev is used as userland interface. FT5406 supports up to
10 touchpoints, but for now driver emulates single touch device
because I do not have GUI bits to test this functionality.
Driver is not enabled in default config for RPI and RPI2
Tested with: evdev-dump, tslib
The hardware can be set to limit the number of interrupts from 2 to 63
interrupts per ms.
To keep the compatibility with the TI documentation the sysctl take the
interval between the interrupts pulses: 16~500 us.
Sponsored by: Rubicon Communications, LLC (Netgate)
SMP SoCs and qemu virt. Further SoCs can be supported if they support the
PLATFORM, PLATFORM_SMP, and MULTIDELAY options.
Tested by: manu
Sponsored by: ABT Systems Ltd
On amd64, arm64 and i386, we have the possibility to switch between TLS
areas in userspace. The nice thing about this is that it makes it easier
to do light-weight threading, if we ever feel like doing that. On armv6,
let's go into the same direction by making it possible to safely use the
TPIDRURW register, which is intended for this purpose.
Clean up the ARMv6 code to remove md_tp entirely. Simply add a dedicated
field to the PCB to hold the value of TPIDRURW across context switches,
like we do for any other register. As userspace currently uses the
read-only TPIDRURO register, simply ensure that we keep both values in
sync where possible. The system calls for modifying the read-only
register will simply write the intended value into both registers, so
that it lazily ends up in the PCB during the next context switch.
Reviewed by: https://reviews.freebsd.org/D7951
Approved by: andrew
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D7951
SPI-mapped MSI interrupts coming from a controller other
than GICv2m need to have their trigger and polarity
properly configured. This patch fixes MSI/MSI-X
on Annapurna Alpine platform with GICv2.
Obtained from: Semihalf
Submitted by: Michal Stanek <mst@semihalf.com>
Sponsored by: Annapurna Labs
Reviewed by: skra, wma
Differential Revision: https://reviews.freebsd.org/D7698
keep the beaglebone defaults: USB0 -> peripheral/gadget, USB1 -> host.
This is only a workaround as in fact fact this hardware is capable of detect
the USB port mode based on type of cable and act according with the detected
mode. Unfortunately the driver does not handle that at moment.
MFC after: 3 days
Sponsored by: Rubicon Communications, LLC (Netgate)
In order to make CloudABI work on ARMv6, start off by copying over the
sysvec for ARM64 and adjust it to use 32-bit registers. Also add code
for fetching arguments from the stack if needed, as there are fewer
register than on ARM64.
Also import the vDSO that is needed to invoke system calls. This vDSO
uses the intra procedure call register (ip) to store the system call
number. This is a bit simpler than what native FreeBSD does, as FreeBSD
uses r7, while preserving the original r7 into ip.
This sysvec seems to be complete enough to start CloudABI processes.
These processes are capable of linking in the vDSO and are therefore
capable of executing (most?) system calls successfully. Unfortunately,
the biggest show stopper is still that TLS is completely broken:
- The linker used by CloudABI, LLD, still has troubles with some of the
relocations needed for TLS. See LLVM bug 30218 for more details.
- Whereas FreeBSD uses the tpidruro register for TLS, for CloudABI I
want to make use of tpidrurw, so that userspace can modify the base
address directly. This is needed for efficient emulation.
Unfortunately, this register doesn't seem to be preserved across
context switches yet.
Obtained from: https://github.com/NuxiNL/cloudabi (the vDSO)
- evdev_set_methods call is not required if actual methods are no-ops
- evdev_set_serial is also optional if there is no meaningful input device
identifier
- evdev_set_id on the other hand is mandatory, so set virtual bus with
dummy vendor/product/version
Suggested by: Vladimir Kondratiev
Add generic evdev support to touchscreen part of ti_adc: two absolute
coordinates + button touch to indicate pen position. Pressure value
reporting is not implemented yet.
Tested on: Beaglebone Black + 4DCAPE-43T + tslib
Rename registers as in the manual.
Do a hard reset of the controller before a soft one.
Since DMA is always used remove dependancy on allwinner_soc_family, it was used
to differentiate SoC as the fdt compatible string were the same.
Tested on A10, A20, H3 and A64.
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D6868
Move PMAP_TS_REFERENCED_MAX out of the various pmap implementations and
into vm/pmap.h, and describe what its purpose is. Eliminate the archaic
"XXX" comment about its value. I don't believe that its exact value, e.g.,
5 versus 6, matters.
Update the arm64 and riscv pmap implementations of pmap_ts_referenced()
to opportunistically update the page's dirty field.
On amd64, use the PDE value already cached in a local variable rather than
dereferencing a pointer again and again.
Reviewed by: kib, markj
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D7836
The cxgbev/cxlv driver supports Virtual Function devices for Chelsio
T4 and T4 adapters. The VF devices share most of their code with the
existing PF4 driver (cxgbe/cxl) and as such the VF device driver
currently depends on the PF4 driver.
Similar to the cxgbe/cxl drivers, the VF driver includes a t4vf/t5vf
PCI device driver that attaches to the VF device. It then creates
child cxgbev/cxlv devices representing ports assigned to the VF.
By default, the PF driver assigns a single port to each VF.
t4vf_hw.c contains VF-specific routines from the shared code used to
fetch VF-specific parameters from the firmware.
t4_vf.c contains the VF-specific PCI device driver and includes its
own attach routine.
VF devices are required to use a different firmware request when
transmitting packets (which in turn requires a different CPL message
to encapsulate messages). This alternate firmware request does not
permit chaining multiple packets in a single message, so each packet
results in a firmware request. In addition, the different CPL message
requires more detailed information when enabling hardware checksums,
so parse_pkt() on VF devices must examine L2 and L3 headers for all
packets (not just TSO packets) for VF devices. Finally, L2 checksums
on non-UDP/non-TCP packets do not work reliably (the firmware trashes
the IPv4 fragment field), so IPv4 checksums for such packets are
calculated in software.
Most of the other changes in the non-VF-specific code are to expose
various variables and functions private to the PF driver so that they
can be used by the VF driver.
Note that a limited subset of cxgbetool functions are supported on VF
devices including register dumps, scheduler classes, and clearing of
statistics. In addition, TOE is not supported on VF devices, only for
the PF interfaces.
Reviewed by: np
MFC after: 2 months
Sponsored by: Chelsio Communications
Differential Revision: https://reviews.freebsd.org/D7599
Let drivers for Alpine CCU, NB and Serdes take care of internal SoC configuration.
Obtained from: Semihalf
Submitted by: Michal Stanek <mst@semihalf.com>
Sponsored by: Annapurna Labs
Reviewed by: imp,wma
Differential Revision: https://reviews.freebsd.org/D7566
This commit adds drivers for Alpine Cache Coherency Unit
and North Bridge Service whose task is to configure
the system fabric and enable cache coherency.
Obtained from: Semihalf
Submitted by: Michal Stanek <mst@semihalf.com>
Sponsored by: Annapurna Labs
Reviewed by: wma
Differential Revision: https://reviews.freebsd.org/D7565
Idle page zeroing has been disabled by default on all architectures since
r170816 and has some bugs that make it seemingly unusable. Specifically,
the idle-priority pagezero thread exacerbates contention for the free page
lock, and yields the CPU without releasing it in non-preemptive kernels. The
pagezero thread also does not behave correctly when superpage reservations
are enabled: its target is a function of v_free_count, which includes
reserved-but-free pages, but it is only able to zero pages belonging to the
physical memory allocator.
Reviewed by: alc, imp, kib
Differential Revision: https://reviews.freebsd.org/D7714
dependent pmap_ts_referenced() so that it updates the page's dirty field
if a modified bit is found while counting reference bits. This
opportunistic update can be performed at low cost and can eliminate the
need for some future calls to pmap_is_modified() by the machine-
independent layer.
MFC after: 3 weeks
because the bootloader, ie redboot, won't let them do so, and so used the
memory before the kernel for early memory allocation, such as pagetables,
stacks, etc...
Make a bit of an effort to try to get that memory mapped.
Value passed as islocked argument to knlist_add should
be consistent with actual lock state so add lock/unlock
calls around knlist_add
PR: 212120
Submitted by: Manuel Stuhn
The thermal sensor lives in the touch screen controller. Touch screen part
isn't done for now.
Temperature is read every ~2 seconds and exposed via sysctl.
to generate one. This is was U-Boot does to generate a random MAC so we end
up with the same MAC address as if U-Boot did generate it.
MFC after: 1 week
Currently boot parameters (r0 - r3) are forgotten in ARM trampoline code.
This patch save them at startup and restore them before jumping into kernel
_start() routine.
This is usefull when booting with Linux ABI and/or custom bootloader.
Submitted by: Grégory Soutadé <soutade@gmail.com>
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D7395
- Read interrupt properties at bus enumeration time and store
it into global mapping table.
- At bus_activate_resource() time, given mapping entry is resolved and
connected to real interrupt source. A copy of mapping entry is attached
to given resource.
- At bus_setup_intr() time, mapping entry stored in resource is used
for delivery of requested interrupt configuration.
- For MSI/MSIX interrupts, mapping entry is created within
pci_alloc_msi()/pci_alloc_msix() call.
- For legacy PCI interrupts, mapping entry must be created within
pcib_route_interrupt() by pcib driver itself.
Reviewed by: nwhitehorn, andrew
Differential Revision: https://reviews.freebsd.org/D7493
Allwinner Uniprocessor SoC.
As of now it works with A10 and A13 (and possibly R8 as it is the same as the A13).
Move files.a10 into a1o subdirectory as it should be.
Rename std.a10 into std.allwinner_up
This removes the need to set the MMC pins with pullups in our DTS.
Thanks to jmcneill@ for spotting this.
Tested on Orange Pi One (Allwinner H3).
MFC after: 1 week
GPIO_INPUT/GPIO_OUTPUT.
a10_gpio_get_pud now returns the whole pud not only PULLDOWN/PULLUP.
Add a10_gpio_get_drv to get the current drive strenght.
During fdt pin configure, avoid setting function/drive/pud if it's already in
the correct value.
Tested on Allwinner H3 and A20
MFC after: 1 week
Right now, userspace (fast) gettimeofday(2) on x86 only works for
RDTSC. For older machines, like Core2, where RDTSC is not C2/C3
invariant, and which fall to HPET hardware, this means that the call
has both the penalty of the syscall and of the uncached hw behind the
QPI or PCIe connection to the sought bridge. Nothing can me done
against the access latency, but the syscall overhead can be removed.
System already provides mappable /dev/hpetX devices, which gives
straight access to the HPET registers page.
Add yet another algorithm to the x86 'vdso' timehands. Libc is updated
to handle both RDTSC and HPET. For HPET, the index of the hpet device
to mmap is passed from kernel to userspace, index might be changed and
libc invalidates its mapping as needed.
Remove cpu_fill_vdso_timehands() KPI, instead require that
timecounters which can be used from userspace, to provide
tc_fill_vdso_timehands{,32}() methods. Merge i386 and amd64
libc/<arch>/sys/__vdso_gettc.c into one source file in the new
libc/x86/sys location. __vdso_gettc() internal interface is changed
to move timecounter algorithm detection into the MD code.
Measurements show that RDTSC even with the syscall overhead is faster
than userspace HPET access. But still, userspace HPET is three-four
times faster than syscall HPET on several Core2 and SandyBridge
machines.
Tested by: Howard Su <howard0su@gmail.com>
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
Differential revision: https://reviews.freebsd.org/D7473
Uses of commas instead of a semicolons can easily go undetected. The comma
can serve as a statement separator but this shouldn't be abused when
statements are meant to be standalone.
Detected with devel/coccinelle following a hint from DragonFlyBSD.
MFC after: 1 month
allow us to add an ACPI attachment for arm64.
Obtained from: ABT Systems Ltd
MFC after: 1 month
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D7307
The rootkey is burnt at production and can't be changed, thus is can be used
as a device unique ID or to generate a MAC address (This is was u-boot does).
The rootkey is exposed as a sysctl (dev.aw_sid.<unit>.rootkey).
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D6383
Summary:
This driver supports the following methods to trigger gathering random bits from the hardware:
1. interrupt when the FIFO is full (default) fed into the harvest queue
2. callout (when BCM2835_RNG_USE_CALLOUT is defined) every second if hz is less than 100, otherwise hz / 100, feeding the random bits into the harvest queue
If the kernel is booted with verbose enabled, the contents of the registers will be dumped after the RBG is started during the attach routine.
Author: hackagadget_gmail.com (Stephen J. Kiernan)
Test Plan: Built RPI2 kernel and booted on board. Tested the different methods to feed the harvest queue (callout, interrupt) and the interrupt driven approach seems best. However, keeping the other method for people to be able to experiment with.
Reviewed By: adrian, delphij, markm
Differential Revision: https://reviews.freebsd.org/D6888
simplebus_add_device() expect a simplebus_softc structure associated with
the device.
Add the simplebus_softc as first member in am335x_pwmss_softc structure.
Sponsored by: Rubicon Communications (Netgate)
H3 EMAC is the same as A83T/A64 except the SoC includes an (optional)
internal 10/100 PHY. Both internal and external PHYs are supported on H3
with this driver.
- Support DEVICE_POLLING
- Increase TX descriptors to 1024
- Add support for passing a chain of mbufs to if_input, reducing the
number of calls to mtx_unlock/mtx_lock under load.
- Remove duplicate byteswap when setting TX_INT_CTL in TX descriptor.
- Set undocumented "TX_NEXT_FRAME" bit in TX control 1 register.
According to the A83T BSP, setting this bit allows the DMA engine to
operate on a packet while receiving another.
Tested on A83T (1000Mbps PHY) and H3 (100Mbps PHY).
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D7031
on arm64 and all SoCs using the old FIFO register location are 32-bit only,
so unconditionally use the new location for arm64.
Reviewed by: andrew, manu
In some cases, the driver must handle given properties located in
specific OF subnode. Instead of creating duplicate set of function, add
'node' as argument to existing functions, defaulting it to device OF node.
MFC after: 3 weeks
All armv6 processors are plenty fast enough for HZ=1000.
No changes are made for older arm systems, because some chips are a bit
wimpy for 1000 while others do fine, so it has to be set on a per-config
basis.
Sometimes the software loses the race when appending more descriptors to
the tx ring and the tx queue stops.
This commit detects this condition and restart the tx queue whenever it stall.
Tested by: sobomax@, Keith White <kwhite@site.uottawa.ca>,
Paul Mather <paul@gromit.dlib.vt.edu>
Sponsored by: Rubicon Communications (Netgate)
Approved by: re (kib)
fully-pessimized implementation that requires a type to be aligned to
its natural size.
On armv6+ the compiler might generate load-/store-multiple instructions
which require 4-byte alignment even though the source code is only
accessing individual uint32_t values in a way that doesn't require any
particular alignment at all. The compiler apparently feels free to
combine multiple accesses into a single instruction that requires a
more-strict alignment, and no set of compiler flags seems to disable
this behavior (at least in clang 3.8).
This fixes alignment faults on arm systems using wifi adapters. The
wifi code uses ALIGNED_POINTER(p, uint32_t) to decide whether it needs
to copy-align tcp headers. Because clang is combining several uint32_t
accesses into a single ldm instruction, we need to say that accessing a
uint32_t requires 4-byte alignment.
Approved by: re(gjb)
threads, to make it less confusing and using modern kernel terms.
Rename the functions to reflect current use of the functions, instead
of the historic KSE conventions:
cpu_set_fork_handler -> cpu_fork_kthread_handler (for kthreads)
cpu_set_upcall -> cpu_copy_thread (for forks)
cpu_set_upcall_kse -> cpu_set_upcall (for new threads creation)
Reviewed by: jhb (previous version)
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Approved by: re (hrs)
Differential revision: https://reviews.freebsd.org/D6731
initialisation. This ensures it will complete before signalling to the boot
CPU it has booted. This fixes a race with the GIC where the arm_gic_map may
not be populated before it is used to bind interrupts leading to some
interrupts becoming bound to no CPUs.
Approved by: re (kib)
Sponsored by: ABT Systems Ltd
are no longer natural-alignment strict, there are still some restrictions.
FreeBSD network code assumes data is naturally-aligned or is running
on a platform with no restrictions; pointers are not annotated to
indicate the data pointed to may be packed or unaligned. The clang
optimizer can sometimes combine the load or store of a pair of adjacent
32-bit values into a single doubleword load/store, and that operation
requires at least 4-byte alignment. __NO_STRICT_ALIGNMENT can lead
to tcp headers being only 2-byte aligned.
Note that alignment faults remain disabled on armv6, this change reverts
only the defining of the symbol which leads to some overly-agressive code
shortcuts when building common/shared drivers and network code for arm.
Approved by: re(kib)
the exact CPU we are running on to set the cpu functions. Relax the check
to ignore the CPU revision. Even so this may still be too specific.
Reviewed by: mmel
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D6504
controller devices are attached. This has already been done for
bus_setup_intr().
There was no doubt that if someone wants to setup an interrupt,
corresponding interrupt controller device must already be attached.
However, the same must be valid for allocation of an interrupt resource
unless the allocation is done blindly, without any information that
such interrupt even exists. While it was done this blind way before,
it won't be possible after next INTRNG change.
Check if there is a second CESA SRAM node in FDT and add a CPU window
for it. Define A38X specific macro for setting device attribute for
each node.
Submitted by: Michal Stanek <mst@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D6216
On other platforms with CESA accelerator the SRAM memory is mapped in
early init before driver is attached. This method only works correctly
with mappings no smaller than L1 section size (1MB). There may be more
SRAM blocks and they may have smaller sizes than 1MB as is the case
for Armada38x. Instead, map SRAM memory with bus_space_map() in CESA
driver attach. Note that we can no longer assume that VA == PA for the
SRAM.
Submitted by: Michal Stanek <mst@semihalf.com
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D6215
- Reset debug architecture and enable monitor for secondary
CPUs in init_secondary() rather than when configuring watchpoint, etc.
- Disable HW debugging capabilities when one of the CPU cores fails
to set up.
- Use dbg_capable() in a more atomic manner to avoid any mismatch
between CPUs.
Differential Revision: https://reviews.freebsd.org/D6009
- Enable monitor mode prior to accessing watchpoint
registers for v6, v6.1 architectures.
- Fix configuration scheme for v6, v6.1 and v7 Debug Archs
- Enable monitor unconditionally and for good instead
of enabling and disabling it (needed for single stepping
on on v6/v6.1)
Tested on RPI-B and Arndale
Differential Revision: https://reviews.freebsd.org/D6008
Pressing the PEK (power enable key) will shutdown the board.
Some events are reported to devd via system "PMU" and subsystem
"Battery", "AC" and "USB" such as connected/disconnected.
Some sensors values (power source voltage/current) are reported via
sysctl (dev.axp209_pmu.X.)
It also expose a gpioc node usable in kernel and userland. Only 3 of
the 4 GPIO are exposed (The GPIO3 is different and mostly unused on
boards). Most popular boards uses GPIO1 as a sense pin for OTG power.
Add a dtsi file that adds gpio-controller capability to the device as
upstream doesn't defined it and include it in our custom DTS.
Reviewed by: jmcneill
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D6135
Previously the USB PHY driver would enable all regulators at attach time.
This prevented boards from booting when powered by the USB OTG port, as
it didn't take VBUS presence into consideration.
of hardware. Mostly this focuses on the big changes needed for setting the
bus clock, because ESDHC is SDHCI v2.0 and USDHC is 3.0, and the number,
location, and interpretation of clock divisor bits is vastly different
between the two. This doesn't get the device all the way to functioning
on ESDHC hardware yet, but it's much closer, now getting through all the
card detection and negotiation of capabilties and speed (but it eventually
hangs on what appears to be a missing interrupt).
Another missing chunk of code for handling ESDHC's 32 bit command-and-mode
register using sdhci's pair of 16 bit writes is added.
This also does some leading whitespace cleanups and sorts some softc
struct members by size, and adds some comments (because when do I ever
touch code without adding comments?).
to match the new state of affairs. The hardware we support has always been
able to do unaligned accesses, we've just never enabled it until now.
This brings FreeBSD into line with all the other major OSes, and should help
with the growing volume of 3rd-party software that assumes unaligned access
will just work on armv6 and armv7.
have ACLE support built in. The ACLE (ARM C Language Extensions) defines
a set of standardized symbols which indicate the architecture version and
features available. ACLE support is built in to modern compilers (both
clang and gcc), but absent from gcc prior to 4.4.
ARM (the company) provides the acle-compat.h header file to define the
right symbols for older versions of gcc. Basically, acle-compat.h does
for arm about the same thing cdefs.h does for freebsd: defines
standardized macros that work no matter which compiler you use. If ARM
hadn't provided this file we would have ended up with a big #ifdef __arm__
section in cdefs.h with our own compatibility shims.
Remove #include <machine/acle-compat.h> from the zillion other places (an
ever-growing list) that it appears. Since style(9) requires sys/types.h
or sys/param.h early in the include list, and both of those lead to
including cdefs.h, only a couple special cases still need to include
acle-compat.h directly.
Loves it: imp
where possible. In the places that doesn't work (multi-line inline asm,
and places where the old armv4 cpufuncs mechanism is used), annotate the
accesses with a comment that includes SCTLR. Now a grep -i sctlr can find
all the system control register manipulations.
No functional changes.
After r285994, sysctl(8) was fixed to use 273.15 instead of 273.20 as 0C
reference and as result, the temperature read in sysctl(8) now exibits a
+0.1C difference.
This commit fix the kernel references to match the reference value used in
sysctl(8) after r285994.
Sponsored by: Rubicon Communications (Netgate)
compilers can emit arm instructions that require 8-byte alignment. The
alignment-sensitive instructions were added in armv5, which has to be
supported by our combined v4/v5 kernels, so the value is set uncoditionally
for all arm architecture versions.
Also adjust the comment to explain in more detail why the macros have the
form and values they do.
Per advice from bde@, maintain the unsignedness of the value of _ALIGNBYTES
(but do so using his second choice of allowing sizeof() to supply the
unsignedness, rather than just hardcoding '8U', which in my mind would
require an even more verbose comment to explain why it's right). Also
explain in the comment that the resulting type of _ALIGN() is equivelent
to uinptr_t on arm (32-bit unsigned int), but it's purposely spelled as
"unsigned" to avoid problems with including other header files. Even
including machine/_types.h to allow use of __uintptr_t causes compilation
failures because of this header being included (indirectly) in asm code.
The discussion that led to this change (albeit at a glacial pace) is at
https://lists.freebsd.org/pipermail/svn-src-head/2014-November/064593.html
needed in later changes where we may not be able to lock the pic list lock
to perform a lookup, e.g. from within interrupt context.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
If platform support EXT_RESOURCES, clocks and resets are handled out of
the box.
If not driver can be subclassed using the generic_usb interface.
generic_usb name was choosed because at one point I'll add generic-ehci
FDT driver.
Reviewed by: jmcneill, hselasky
Approved by: andrew (mentor)
Differential Revision: https://reviews.freebsd.org/D5481
supports the Security Extensions or not. This bit is not the same as the CPU one.
Currently we are not checking for either before trying to write to the special
registers. This can lead to problems on hardware or simulators that do not
provide the security extensions. Add the missing checks. Their interactions with
the CPU flag is not entirely clear to me but using a macro will make it easier
to quickly adjust the condition once the CPU bits are sorted as well.
Reviewed by: br
Sponsored by: DARPA/AFRL
Differential Revision: https://reviews.freebsd.org/D6397
so the module could be loaded.
Discussed with: andrew
Reviewed by: andrew
Sponsored by: DARPA/AFRL
Differential Revision: https://reviews.freebsd.org/D6359
interface with 5 methods to mirror the 5 MSI/MSI-X methods in the pcib
interface. The pcib driver will need to perform a device specific lookup
to find the MSI controller and pass this to intrng as the xref. Intrng
will finally find the controller and have it handle the requested operation.
Obtained from: ABT Systems Ltd
MFH: yes
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5985
The A83T thermal sensor controller has three sensors. Sensor 0 corresponds
to CPU cluster 0, sensor 1 to CPU cluster 1, and sensor 2 to the GPU. This
driver exports the temperature sensor readings via sysctl.
Calibration data is obtained from SRAM found in the Secure ID module.
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D6378
The RSB controller speaks a simplified two wire protocol at speeds up to
20MHz. It is used on sun8i and sun9i family SoCs to communicate with
power management ICs.
RSB isn't really I2C or SMBus, but the driver exposes an iicbus interface
to simplify power management IC drivers (which may need to support both
RSB and I2C connectivity).
- Introduce new OF API function OF_prop_free to free memory allocated by
OF_getprop_alloc and OF_getencprop_alloc. Current code just calls free(9)
with M_OFWPROP memory class which assumes knowledge about OF_*prop_alloc
functions' internals and leads to unneccessary code coupling
- Convert some of the free(..., M_OFWPROP) instances to OF_prop_free
Files affected by this commit are the ones I was able to test on real
hardware. The rest of free(..., M_OFWPROP) instances will be handled with
idividual maintainers
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D6315
Current API assumes that "gpios" property belongs to the device's node but for
some binding it's not true: gpiokeys has set of child nodes with this property.
Patch adds new argument instead of replacing device_t because device_t will be
used to track ownership for allocated pins
Reviewed by: mmel
Differential Revision: https://reviews.freebsd.org/D6277
This function works with all smp non-multicluster allwinner SoC (A20, A31, A31S and H3).
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D6269
Note that the updated comment is valid only for INTRNG. This should not
be a problem as not INTRNG code is left in place for debugging reasons
only and should not be used anymore. It's anticipated that this old
code will be removed soon.
- Hardcode '8' instead of NBBY in _BITSET_BITS.
- Define a private version of 'howmany' for use in __bitset_words().
- While here, move a few more things out of _bitset.h and _cpuset.h to
bitset.h and cpuset.h, respectively. The only things left in
_bitset.h and _cpuset.h are the bits needed to define a bitset
structure.
Reviewed by: bde, kib (ish)
struct associated with some type defined in enum intr_map_data_type
must have struct intr_map_data on the top of its own definition now.
When such structs are used, correct type and size must be filled in.
There are three such structs defined in sys/intr.h now. Their
definitions should be moved to corresponding headers by follow-up
commits.
While this change was propagated to all INTRNG like PICs,
pic_map_intr() method implementations were corrected on some places.
For this specific method, it's ensured by a caller that the 'data'
argument passed to this method is never NULL. Also, the return error
values were standardized there.
Clocks, GPIO, UART, SD card / eMMC, USB, watchdog, and ethernet are
supported. Note that the A83T contains two clusters of four Cortex-A7
CPUs, and only CPUs in first cluster are started for now.
Tested on a Sinovoip Banana Pi BPI-M3.
The datasheets refer to this controller as EMAC, not to be confused with
the fast ethernet controller (also named EMAC) found in A10/A20 SoCs.
Tested on a BananaPi M3 (A83T), which uses an external RGMII PHY (RTL8211E).
Reviewed by: adrian
Differential Revision: https://reviews.freebsd.org/D6169
Add the needed hardcoded gem5 attachments for the UART there, re-using all
the other bits.
In collaboration with: andrew
Sponsored by: DARPA/AFRL
Reviewed by: andrew
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D6204
In case we do not have an interrupt assignment for the virtual timer,
force the physical timer.
Also skip resource allocation for any timer we do not have an interrupt
assignment for.
In collaboration with: andrew
Submitted by: br ([1] from his gem5 arm64 work)
Sponsored by: DARPA/AFRL
Reviewed by: andrew
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D6203
In case of updating it with a very low value it might expire again
after writing the tval but before updating ctrl. In that case we do
lose the status bit saying that the timer expired and we will consequently
not get an interrupt for it, leaving the timer in a "dead" state.
In order to solve this increase the minimum period with what the timer
can be loaded to something higher.
Found & analysed with: gem5
Debugged with: andrew
Sponsored by: DARPA/AFRL
Reviewed by: andrew
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D6202
implementations. Early in the boot the kernel will use an approximate,
however after the timer has been probed it will switch to a more accurate
implementation.
Reviewed by: manu
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5762
Split ADC driver in two halves: ADC(analog ot digital) and
TSC(touchscreen). Touchscreen driver is fully functional
up to the point of reporting samples. This part will be added
once FreeBSD has API for touchscreen.
Tested on: Beaglebone Black + 4DCAPE-43T
Reviewed by: loos
Differential Revision: https://reviews.freebsd.org/D5847
On ARM, we can directly switch between translation tables only when
the size of the mapping for any given virtual address is the same in
the old and new translation tables. The load of new TTB and subsequent
TLB flush is not atomic operation. So speculative page table walk can
load TLB entry from new mapping while rest of TLB entries are still the
old ones. In worst case, this can lead to situation when TLB cache can
contain multiple matching TLB entries. One (from old mapping) L2 entry
for VA + 4k and one (from new mapping) L1 entry for VA.
Thus, we must switch to kernel pmap translation table as intermediate
mapping because all sizes of these (old pmap and kernel pmap) mappings
are same (or unmapped). The same is true for switch from kernel pmap
translation table to new pmap one.
Set MMC_CAP_4_BIT_DATA and MMC_CAP_8_BIT_DATA based on the "bus-width"
DT property and reduce maximum bus frequency from 52MHz to 50MHz to match
the capabilities of the clock provider.
Tested on a BananaPi BPI-M3 (A83T).
Such situation is defined as UNPREDICTABLE by arm arm manual.
This patch fixes all explicit TLB fetches which could cause this issue
and speculative TLB fetches for sections mapped in user address space.
Speculative TLB fetches for sections mapped in kernel address space are
not fixed yet as the break-before-make approach must be implemented for
kernel mappings too. This means that promoted/demoted section will be
unmapped for a while. Either kernel stack the promotion/demotion is
being done on or L1 page table(s) which must be modified may be mapped
by this section. Thus the fix will not be so simple like for userland
mappings.
The issue was detectable only on Cortex-A8 platforms and only very
rarely. It was reported few times. First, it was by Mikael Urankar
in June 2015. He helped to identify the mechanism of this issue, but
we were not sure how to fix it correctly until now.
PR: 208381
Reported by: Mikael Urankar (mikael.urankar at gmail.com)
Reviewed by: kib
and R/W emulation aborts under pmap lock.
There were two reasons for using of atomic operations:
(1) the pmap code is based on i386 one where they are used,
(2) there was an idea that access and R/W emulation aborts should be
handled as quick as possible, without pmap locking.
However, the atomic operations in i386 pmap code are used only because
page table entries may be modified by hardware. At the beginning, we
were not sure that it's the only reason. So even if arm hardware does
not modify them, we did not risk to not use them at that time. Further,
it turns out after some testing that using of pmap lock for access and
R/W emulation aborts does not bring any extra cost and there was no
measurable difference. Thus, we have decided finally to use pmap lock
for all operations on page table entries and so, there is no reason for
atomic operations on them. This makes the code cleaner and safer.
This decision introduce a question if it's safe to use pmap lock for
access and R/W emulation aborts. Anyhow, there may happen two cases in
general:
(A) Aborts while the pmap lock is locked already - this should not
happen as pmap lock is not recursive. However, under pmap lock only
internal kernel data should be accessed and such data should be mapped
with A bit set and NM bit cleared. If double abort happens, then
a mapping of data which has caused it must be fixed.
(B) Aborts while another lock(s) is/are locked - this already can
happen. There is no difference here if it's either access or R/W
emulation abort, or if it's some other abort.
Reviewed by: kib
(PL1) and unprivileged (PL0) read/write access. As cp15 virtual to
physical address translation operations are used, interrupts must be
disabled to get consistent result when they are called.
These functions should be used only in very specific occasions like
during abort handling or kernel debugging. One of them is going to be
used in pmap_fault(). However, complete function set is added. It cost
nothing, as they are inlined.
While here, fix comment of #endif.
Reviewed by: kib
rounddown2 tends to produce longer lines than the original code
and when the code has a high indentation level it was not really
advantageous to do the replacement.
This tries to strike a balance between readability using the macros
and flexibility of having the expressions, so not everything is
converted.
bcm2835_mbox_fb_init sets configuration so SET_VIRTUAL_OFFSET should be used
instead of GET_VIRTUAL_OFFSET
Submitted by: Sylvain Garrigues <sylvain@sylvaingarrigues.com>
VideoCore reports garbage in viewport geometry fields unless
viewport was set previously by earlier stage boot loader. So
when booting FreeBSD kernel directly from VideoCore's start.elf
framebuffer intialization fails due to invalid vxres, vyres
values. Make sure we request viewport to be equal to physical
resolution
Submitted by: Sylvain Garrigues <sylvain@sylvaingarrigues.com>
write to the End of Interrupt (EOI) register before handling the interrupt.
This should be a noop as it will be set for all edge triggered interrupts,
however this will not be the case for MSI interrupts. These are also edge
triggered, however we should not write to the EOI register until later in
arm_gic_pre_ithread.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
support MSI and MSI-X interrupts, however intrng needs updates before this
can happen.
For now we just attach the driver until the MSI API is ready.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5950
- Pre-buffer audio data to VideoCore so there are no audible glitches when
driver is too late to provide samples
- Start actual playback when there is some prebuffered audio,
it fixes audible noisy click in the beginning of playback
- Use #defines instead of hardcoded values where appropriate
- Fix copy-pasted comment
PR: 208678
value that can't ever be in an inconsistant intermediate state even when
some other thread is in the middle of writing the value/register.
Locking of the hardware remains in the few places that do r-m-w operations.
Locking of metadata access is restricted to places using memcpy or sprintf
to modify the metadata.
oddly separated from related functionality. This just moves some blocks
of code around so that setup_intr and teardown_intr are near each other
again, and likewise for enable/disable_intr. No functional changes.
The PLL_X, base CPU frequency source, doesn't have a bypass switch and thus
we must use another frequency source for CPU while changing its frequency.
PLL_P is ideal for this, it runs at 480MHz and CPU can be clocked at this
frequency at any CPU voltage.
many SoCs these two are the same, however there is no requirement for this
to be the case, e.g. on the ARM Juno we boot on what the GIC thinks of as
CPU 2, but FreeBSD numbers it CPU 0.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
a child of it. This is done in conformity with Linux dts files and
as preparation for rework of BCM2836 interrupt controller for INTRNG.
Reviewed by: gonzo
Differential Revision: https://reviews.freebsd.org/D5807
universal.
(1) New struct intr_map_data is defined as a container for arbitrary
description of an interrupt used by a device. Typically, an interrupt
number and configuration relevant to an interrupt controller is encoded
in such description. However, any additional information may be encoded
too like a set of cpus on which an interrupt should be enabled or vendor
specific data needed for setup of an interrupt in controller. The struct
intr_map_data itself is meant to be opaque for INTRNG.
(2) An intr_map_irq() function is created which takes an interrupt
controller identification and struct intr_map_data as arguments and
returns global interrupt number which identifies an interrupt.
(3) A set of functions to be used by bus drivers is created as well as
a corresponding set of methods for interrupt controller drivers. These
sets take both struct resource and struct intr_map_data as one of the
arguments. There is a goal to keep struct intr_map_data in struct
resource, however, this way a final solution is not limited to that.
(4) Other small changes are done to reflect new situation.
This is only first step aiming to create stable interface for interrupt
controller drivers. Thus, some temporary solution is taken. Interrupt
descriptions for devices are stored in INTRNG and two specific mapping
function are created to be temporary used by bus drivers. That's why
the struct intr_map_data is not opaque for INTRNG now. This temporary
solution will be replaced by final one in next step.
Differential Revision: https://reviews.freebsd.org/D5730
separate driver. Add support for activating clock and hwreset resources
for these devices when the EXT_RESOURCES option is present.
Reviewed by: andrew, mmel, Emmanuel Vadot <manu@bidouilliste.com>
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D5749
This driver works in PIO mode for now, interrupts are available only when
FIFO is enabled. The FIFO cannot be used with arbitrary sizes which defeat
its general use.
At some point we can add DMA transfers where the FIFO can be more useful.
Tested on uBMC (microBMC) and BBB.
Sponsored by: Rubicon Communications (Netgate)
different ID space than the kernel. Because of this we need to read the
ID from the hardware. The hardware will provide this value to the CPU by
reading any of the first 8 Interrupt Processor Targets Registers.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D5706
- in atags
- in DT blob (by using 'fdt chosen' U-Boot command)
The command line must start with guard's string 'FreeBSD:' and can contain
list of comma separated kenv strings. Also, boot modifier strings from
boot.h are recognised and parsed into boothowto.
The command line must be passed from U-Boot by setting of bootargs variable:
'setenv bootargs FreeBSD:boot_single=1,vfs.root.mountfrom=ufs:/dev/ada0s1a'
followed by 'fdt chosen' (only for DT based boot)
- Don't convert atags address passed from U-Boot. It's real physical
address (and we have 1:1 mapping).
- Size of tags is encoded in words, not in bytes
This allow us to boot FreeBSD kernel (using uImage encapsulation) directly
from U-boot using 'bootm' command or by Android fastboot loader.
For now, kernel uImage must be marked as Linux, but we can add support for
FreeBSD into U-Boot later.
controller IPI provider.
New struct intr_ipi is defined which keeps all info about an IPI:
its name, counter, send and dispatch methods. Generic intr_ipi_setup(),
intr_ipi_send() and intr_ipi_dispatch() functions are implemented.
An IPI provider must implement two functions:
(1) an intr_ipi_send_t function which is able to send an IPI,
(2) a setup function which initializes itself for an IPI and
calls intr_ipi_setup() with appropriate arguments.
Differential Revision: https://reviews.freebsd.org/D5700
a DRIVER_MODULE() referencing mmc_driver has a MODULE_DEPEND() on mmc. This
is because the kernel linker only searches for symbols in dependent modules,
so loading sdhci_pci (and other bus-flavors of sdhci) would fail when mmc
was not compiled into the kernel (even if you hand-loaded mmc first).
(Thanks to jilles@ for providing the vital clue about the kernel linker.)
On some architectures, u_long isn't large enough for resource definitions.
Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but
type `long' is only 32-bit. This extends rman's resources to uintmax_t. With
this change, any resource can feasibly be placed anywhere in physical memory
(within the constraints of the driver).
Why uintmax_t and not something machine dependent, or uint64_t? Though it's
possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on
32-bit architectures. 64-bit architectures should have plenty of RAM to absorb
the increase on resource sizes if and when this occurs, and the number of
resources on memory-constrained systems should be sufficiently small as to not
pose a drastic overhead. That being said, uintmax_t was chosen for source
clarity. If it's specified as uint64_t, all printf()-like calls would either
need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t
aren't horrible, but it would also bake into the API for
resource_list_print_type() either a hidden assumption that entries get cast to
uintmax_t for printing, or these calls would need the PRI*64 macros. Since
source code is meant to be read more often than written, I chose the clearest
path of simply using uintmax_t.
Tested on a PowerPC p5020-based board, which places all device resources in
0xfxxxxxxxx, and has 8GB RAM.
Regression tested on qemu-system-i386
Regression tested on qemu-system-mips (malta profile)
Tested PAE and devinfo on virtualbox (live CD)
Special thanks to bz for his testing on ARM.
Reviewed By: bz, jhb (previous)
Relnotes: Yes
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D4544
In dual emac mode, the CPSW subsystem provides two independent ethernets.
This is implemented (as recommended by TI's TRM) with a mixture of switch
settings (vlans) and specific features of CPSW subsystem.
The driver was splitted to accommodate the shared parts (RX and TX rings
for example) while it still provides two independent ethernets.
Each of the ethernet ports driver has it's own set of MDIO registers among
the other private settings.
Previously this driver always operate in promisc mode, now the Switch ALE
(address table entry) is properly initialized and enabled.
The driver is also tested (and known to work) with both ports operating in
single port mode (active_slave 0 or 1).
Tested on uBMC (dual emac mode, both ports in single mode, giga and fast
ethernet) and BBB (single port, fast ethernet).
Sponsored by: Rubicon Communications (Netgate)
We changed the ABI for ARM in 10, an removed support for the old ABI in 11,
as such binaries from these releases are unable to be run on a head kernel.
Reviewed by: bz, emast
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5652
r296861 addressed a build failure due to undefined SYS_freebsd6_lseek
by adding a COMPAT_FREEBSD6 conditional, but we do not support FreeBSD 6
compatibility on armeb anyway so remove it completely.
Reviewed by: andrew, bz
Differential Revision: https://reviews.freebsd.org/D5643
the ABI in 10.0, and have removed support for the old ABI in 11. As such
any of these options to provide compatibility prior to 10 are unneeded.
Sponsored by: ABT Systems Ltd
The following pheripherals are supported: UART, MMC, AHCI, EHCI, PCIe, I2C,
PMIC, GPIO, CPU temperature and clock.
Note: The PCIe driver is pure mash at this moment. It will be reworked
immediately when both D5237 and D2579 enter the current tree.
This commit provides attachment of xhci-platform for A38X boards, making
it possible to mount FreeBSD world from USB3.0 flash. 'xhci' device was
added to files.mv (as optional) and kernconf of Armada38x was enhanced.
It was also necessary to open programmable memory windows of USB3.0.
fdt_win_setup needed improvement so it's able to traverse through
children of internal-regs node.
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: hselasky
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D5031
After ARM_INTRNG introduction, MPIC code needed several modifications:
- IRQ resource and its handler added
- several DEVMETHODs of INTRNG interface implemented
- defines enhanced to ensure code compiles as well for AXP as for A38X
- added dummy MSI_IRQ, ERR_IRQ defines for Armada38x
- MPIC driver was added to files.armada38x, ARM_INTRNG option enabled in
kernconf file and regs of MPIC corrected in dts file.
Instead of modifying Armada38X DTS, offsets to CPU registers defined in
driver were changed. That required restoring 'reg' property of mpic node
in ArmadaXP to state compliant with Linux DTS.
Additionally, required ARM_INTRNG definitions were added to mv_common.c.
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: adrian, andrew, ian, skra
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D5030
code for the A20 to use the new PLATFORM_SMP interface, and extends it to
add support for the new SoCs allowing for both to coexist within the same
kernel.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D5342
adds a lock to ensure only a single device is accessing the hardware. A
reference count is added to only enable when we start to use the clock,
and to disable after we have finished needing the clock.
This was extracted from a larger review to add OHCI support to the
Allwinner SoCs.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: jmcneill
X-Differential Revision: https://reviews.freebsd.org/D5481
Very similar to the A10 RTC controller with a few register offsets changed
and a different location for the LOSC switch status.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: jmcneill
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D5500
taskqueue_enqueue() was changed to support both fast and non-fast
taskqueues 10 years ago in r154167. It has been a compat shim ever
since. It's time for the compat shim to go.
Submitted by: Howard Su <howard0su@gmail.com>
Reviewed by: sephe
Differential Revision: https://reviews.freebsd.org/D5131
is the physical memory size so may be larger than a u_long can hold, e.g.
on ARM with LPAE we could see an address space of up to 40 bits. On ARM
u_long is only 32 bits so the memory size will be truncated, possibly to
zero.
Reported by: bz
Sponsored by: ABT Systems Ltd
Summary:
As part of the migration of rman_res_t to be typed to uintmax_t, memory ranges
must be clamped appropriately for the bus, to prevent completely bogus addresses
from being used.
This is extracted from D4544.
Reviewed By: cem
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D5134
Use u_long instead of uint32_t variables to avoid overflow
in case of PA space bigger than 32-bit.
Obtained from: Semihalf
Submitted by: Michal Stanek <mst@semihalf.com>
Sponsored by: Annapurna Labs
Approved by: cognet (mentor)
Reviewed by: andrew, br, wma
Differential revision: https://reviews.freebsd.org/D5393
different methods to start the secondary cores in a kernel built for
multiple SoCs, e.g. with the Allwinner A20 and A31.
Sponsored by: ABT systems Ltd
Differential Revision: https://reviews.freebsd.org/D5466
Newer Allwinner MMC implementations use a different FIFO register offset
(0x200 instead of 0x100). Since the FDT uses the same compat string for
both cases, base the decision on which FIFO offset to use on the Allwinner
SoC family.
Reviewed by: Emmanuel Vadot <manu@bidouilliste.com>
Approved by: gonzo (mentor)
Differential Revision: https://reviews.freebsd.org/D5468
the interrupt framework is also going to be used by another (MIPS)
architecture. IPI implementations may vary much across different
architectures.
An IPI implementation should still define INTR_IPI_COUNT and use
intr_ipi_setup_counters() to setup IPI counters which are inside of
intrcnt[] and intrnames[] arrays. Those are used for sysctl and ddb.
Then, intr_ipi_increment_count() should be used to increment obtained
counter.
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D5459
Most calls to bus_alloc_resource() use "anywhere" as the range, with a given
count. Migrate these to use the new bus_alloc_resource_anywhere() API.
Reviewed by: jhb
Differential Revision: https://reviews.freebsd.org/D5370
intr_pic_init_secondary. Replace them with a direct call. On BCM2836
and ARMADA XP we need to add this function, but it can be empty.
Reviewed by: ian, imp
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5460
slightly wrong on the others. We should just check if mp_ncpus is set to
more than one CPU as we may wish to run on a single core even when SMP is
available.
Reviewed by: ian
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5458
support for the i2c, mmc, and gmac clocks. Further clocks can be added as
needed.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D5339
