to decide what protections are required by the faulting access. The old
code disassembled the faulting instruction, and there are a lot of new
instructions that aren't handled. The old code is still used for armv4/5
which doesn't have the WNR bit)
routine, now a platform can provide a pointer to an early_putc() routine
which is used instead of cn_putc(). Control can be handed off from early
printf support to standard console support by NULLing out the pointer
during standard console init.
This leverages all the existing error reporting that uses printf calls,
such as panic() which can now be usefully employed even in early
platform init code (useful at least to those who maintain that code and
build kernels with EARLY_PRINTF defined).
Reviewed by: imp, eadler
Real means the one TSC / Symmetricom / Microsemi actually uses on their 4370
and other rm9200 boards. This code demonstrates a variety of useful things
board init code can do, including adjusting the master clock frequency.
communicate the kernel's physical load address from where it's known in
initarm() into cpu_mp_start() which is called from non-arm code and
takes no parameters.
This adds the global variable and ensures that all the various copies
of initarm() set it. It uses the variable in cpu_mp_start(), eliminating
the last uses of KERNPHYSADDR outside of locore.S (where we can now
calculate it instead of relying on the constant).
a new physmem.c file. The new code provides helper routines that can be
used by legacy SoCs and newer FDT-based systems. There are routines to
add one or more regions of physically contiguous ram, and exclude one or
more physically contiguous regions of ram. Ram can be excluded from crash
dumps, from being given over to the vm system for allocation management,
or both. After all the included and excluded regions have been added,
arm_physmem_init_kernel_globals() processes the regions into the global
dump_avail and phys_avail arrays and realmem and physmem variables that
communicate memory configuration to the rest of the kernel.
Convert all existing SoCs to use the new helper code.
This was an optimization used only by a few xscale platforms. Part of
the optimization was to create a direct map for all physical pages, and
that resulted in making multiple mappings of pages in a way that bypassed
the logic in pmap.c to handle VIVT cache aliasing. It also just generally
made the code more complex and hard to maintain for all SoCs.
Reviewed by: cognet
and where the code that references it can safely be elided if it's not
defined (meaning the code is used for legacy arm platforms that still
define the compile-time PHYSADDR but not on newer systems that calculate
the value at runtime).
in effect due to r250753. That is sufficient for all SoCs with a 32 byte
cache line size. Systems with 64 byte cache lines will need the option;
that will be done in a separate commit.
Thanks to loos@ for pointing out r250753.
a sub-node of nexus (ofwbus) rather than direct attach under nexus. This
fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier.
SPARC is unchanged.
Reviewed by: imp, ian
the old way was to store pcpu in a register, and get curthread from pcpu,
which is not very atomic, and led to issues if the thread was migrated
to another core between the time we got the pcpu address and the time we
got curthread.
Instead, we now store curthread where pcpu used to be store, and we
calculate the pcpu address based on the cpu id.
to check the status property in their probe routines.
Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352. Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.
Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
It turns out the version of gas we're using interprets the old '_all' mask
as 'fc' instead of 'fsxc'. That is, "all" doesn't really mean "all".
This was the cause of the "wrong-endian register restore" bug that's
been causing problems with some cortex-a9 chips. The 'endian' bit in the
spsr register would never get changed (it falls into the 'x' mask group)
and the first return-from-exception would fail if the chip had powered on
with garbage in the spsr register that included the big-endian bit. It's
unknown why this affected only certain cortex-a9 chips.
strings and include arbitrary information (IRQ line/domain/sense). When the
ofw_bus_map_intr() API was introduced, it assumed that, as on most systems,
these were either 1 cell, containing an interrupt line, or 2, containing
a line number plus a sense code. It turns out a non-negligible number of
ARM systems use 3 (or even 4!) cells for interrupts, so make this more
general.
devices. This is a nop, except for what's reported by atmelbus for the
resources.
It would be nice if we could dymanically allocated these things, but
the pmap_mapdev panics if we don't keep the static mappings, so we
still need to play the carefully allocate VA space between all
supported SoC game.
User's with their own devices may need to make adjustments.
Note that this commit hasn't been compile tested because these files
are not hooked up to the build...
PR: 186129
Submitted by: Takanori Sawada
Approved by: rpaulo
Make comments match parameters
Add options for early printf so we get regression build testing on it.
Add preview of options for FDT support coming soon (I hope)
console, it calls the grab functions. These functions should turn off
the RX interrupts, and any others that interfere. This makes mountroot
prompt work again. If there's more generalized need other than
prompting, many of these routines should be expanded to do those new
things.
Reviewed by: bde (with reservations)
and invoke it for bootverbose logging, and also from a new DDB command,
"show devmap". Also tweak the format string for the bootverbose output
of physical memory chunks to get the leading zeros in the hex values.
this to the cache line size is required to avoid data corruption on armv4
and armv5, and improves performance on armv6, in both cases by avoiding
partial cacheline flushes for USB IO.
this to the cache line size is required to avoid data corruption on armv4
and armv5, and improves performance on armv6, in both cases by avoiding
partial cacheline flushes for USB IO.
All these configs already exist in 10-stable. A few that don't (and
thus can't be MFC'd yet) will be committed separately.
every arm system must have some static mappings to work correctly (although
currently they all do), so remove some panic() calls (which would never
been seen anyway, because they would happen before a console is available).
related to setting up static device mappings. Since it was only used by
arm/mv/mv_pci.c, it's now just static functions within that file, plus
one public function that gets called only from arm/mv/mv_machdep.c.
in the dts source, and adding the right devices to the kernel config. Also
generally bring the kernel config into line with what we have for other
Marvell/Kirkwood systems (add lots of useful devices and options).
One particularly notable addition amongst the kernel config changes is
USB_HOST_ALIGN=32, which may help eliminate data corruption on USB drives.
PR: kern/181975 arm/162159
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
(aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
requests to its parent (nexus). This allows x86 FDT devices to allocate
both memory and IO requests and removes the last notionally MI use of
fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
static device mappings.
This SoC relied heavily on the fact that all devices were static-mapped
at a fixed address, and it (rather bogusly) used bus_space read and write
calls passing hard-coded virtual addresses instead of proper bus handles,
relying on the fact that the virtual addresses of the mappings were known
at compile time, and relying on the implementation details of arm
bus_space never changing. All such usage was replaced with calls to
bus_space_map() to obtain a proper bus handle for the read/write calls.
This required adjusting some of the #define values that map out hardware
registers, and some of them were renamed in the process to make it clear
which were defining absolute physical addresses and which were defining
offsets. (The ones that just define offsets don't appear to be referenced
and probably serve no value other than perhaps documentation.)
and add static mappings that cover most of the on-chip peripherals with
1MB section mappings. This adds about 220MB or so available kva space
by not using a hard-coded 0xF0000000 as the mapping address.
when running on FDT systems. Unmap memory in nexus_deactivate_resource().
Also, call rman_activate_resource() before mapping device memory, and only
do the mapping if it returns success.
Reviewed by: nwhitehorn
searching. If you didn't configure a timer capture pin you'd get a data
abort as it wandered into the weeds, now you get a nice warning message
about your config, as originally intended.
Fix race condition in DELAY function: sc->tc was not initialized yet when
time_counter pointer was set, what resulted in NULL pointer dereference.
Export sysfreq to dts.
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Add suport for setting triggering level and polarity in GIC.
New function pointer was added to nexus which corresponds
to the function which sets level/sense in the hardware (GIC).
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
This seems to cause issues with jemalloc + {dhclient, sshd}.
Thus, revert this for now until the root cause can be found and
fixed.
This should quieten some runtime problems with the Raspberry Pi.
PR: kern/185046
MFC after: 3 days
capture mode together with the timecounter's PPS polling feature to get
very accurate PPS capture without any interrupt processing (or latency).
Hardware timers 4 through 7 have associated capture-trigger input pins.
When the PPS support is compiled in the code automatically chooses the
first timer it finds that has the capture-trigger pin set to input mode
(this is configured via the fdt data).
- Use named constants for register bits, instead of mystery numebrs
scattered around in the code.
- Use inline functions for bus space read/write, instead of macros
that rely on global variables.
- Move the timecounter struct into the softc instead of treating it
as a global variable. Backlink from it to the softc.
- This leaves a pointer to the softc as the only static/global variable
and it's now used only by DELAY().
clients. Mask RX interrupts while grabbed on the atmel serial
driver. This UART interrupts every character. When interrupts are
enabled at the mountroot> prompt, this means the ISR eats the
characters. Rather than try to create a cooperative buffering system
for the low level kernel console, instead just mask out the ISR. For
NS8250 and decsendents this isn't needed, since interrupts only happen
after 14 or more characters (depending on the fifo settings). Plumb
such that these are optional so there's no change in behavior for all
the other UART clients. ddb worked on this platform because all
interrupts were disabled while it was running, so this problem wasn't
noticed. The mountroot> issue has been around for a very very long
time.
MFC after: 3 days
Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural
similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded
boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064.
Approved by: stas (mentor)
completely full, we'd not complete any of the mbufs due to the fence
post error (this creates a large leak). When this is fixed, we still
leak, but at a much smaller rate due to a race between ateintr and
atestart_locked as well as an asymmetry where atestart_locked is
called from elsewhere. Ensure that we free in-flight packets that
have completed there as well. Also remove needless check for NULL on
mb, checked earlier in the loop and simplify a redundant if.
MFC after: 3 days
this change we may end up with a panic (Fatal kernel mode data abort:
'External Non-Linefetch Abort (S)') as described in
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/276862.aspx.
It is now possible to bring up I2C1 and I2C2 on BBB.
Approved by: adrian (mentor)
vm_max_virtual_address to be KERNVIRTADDR + 256MB. This allows some
future shock protection since the KVA requirements have gone up since
the unmapped changes have gone in, as well as preventing us from
overlapping with the hardware devices, which we map at 0xd0000000,
which we'd hit with anything more than 85MB...
MFC after: 3 days
always returning '0' for all the reads, even for the outputs. It is now
known to work with gpioiic(4) and gpioled(4).
Approved by: adrian (mentor)
Tested on: BBB
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky
Reviewed by: cperciva
enables data cache and other chip-specific features. It was previously
done via an early SYSINIT, but it was being done after pmap and vm setup,
and those setups need to use mutexes. On some modern ARM platforms,
the ldrex/strex instructions that implement mutexes require the data cache
to be enabled.
A nice side effect of enabling caching earlier is that it eliminates the
multi-second pause that used to happen early in boot while physical memory
and pmap and vm were being set up. On boards with 1 GB or more of ram
this pause was very noticible, sometimes 5-6 seconds.
PR: arm/183740
When entering a mapping via pmap_enter() unmanaged pages ought to be
naturally excluded from the "modified" and "referenced" emulation.
RW permission should be granted implicitly when requested,
otherwise unmanaged page will not recover from the permission fault
since there will be no PV entry to indicate that the page can be written.
In addition, only managed pages that participate in "modified"
emulation need to be marked as "dirty" and "writeable" when entered
with RW permissions. Likewise with "referenced" flag for managed pages.
Unmanaged ones however should not be marked as such.
Reviewed by: cognet, gber
When emulating modified bit the executable attribute was cleared by
mistake when calling pmap_set_prot(). This was not a problem before
changes to ref/mod emulation since all the pages were created RW basing
on the "prot" argument in pmap_enter(). Now however not all pages are RW
and the RW permission can be cleared in the process.
Added proper KTRs accordingly.
Spotted by: cognet
Reviewed by: gber
host.host_ocr, examine the correct field when setting up the hardware. Also,
the offset for the capabilties register should be 0x140, not 0x240.
Submitted by: Ilya Bakulin <ilya@bakulin.de>
Pointy hat to: me
rely only on checking the device unit to indentify the BSC unit we are
attaching to. Make use of the device base address to identify our BSC unit.
Approved by: adrian (mentor)
words, every architecture is now auto-sizing the kmem arena. This revision
changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes
mandatory and the definition of VM_KMEM_SIZE becomes optional.
Replace or eliminate all existing definitions of VM_KMEM_SIZE. With
auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling
for VM_KMEM_SIZE_MIN on most architectures. Use VM_KMEM_SIZE_MIN for
clarity.
Change kmeminit() so that the effect of defining VM_KMEM_SIZE is similar to
that of setting the tunable vm.kmem_size. Whereas the macros
VM_KMEM_SIZE_{MAX,MIN,SCALE} have had the same effect as the tunables
vm.kmem_size_{max,min,scale}, the effects of VM_KMEM_SIZE and vm.kmem_size
have been distinct. In particular, whereas VM_KMEM_SIZE was overridden by
VM_KMEM_SIZE_{MAX,MIN,SCALE} and vm.kmem_size_{max,min,scale}, vm.kmem_size
was not. Remedy this inconsistency. Now, VM_KMEM_SIZE can be used to set
the size of the kmem arena at compile-time without that value being
overridden by auto-sizing.
Update the nearby comments to reflect the kmem submap being replaced by the
kmem arena. Stop duplicating the auto-sizing formula in every machine-
dependent vmparam.h and place it in kmeminit() where auto-sizing takes
place.
Reviewed by: kib (an earlier version)
Sponsored by: EMC / Isilon Storage Division
fdtbus in most cases. This brings ARM and MIPS more in line with existing
Open Firmware platforms like sparc64 and powerpc, as well as preventing
double-enumeration of the OF tree on embedded PowerPC (first through nexus,
then through fdtbus).
This change is also designed to simplify resource management on FDT platforms
by letting there exist a platform-defined root bus resource_activate() call
instead of replying on fdtbus to do the right thing through fdt_bs_tag.
The OFW_BUS_MAP_INTR() and OFW_BUS_CONFIG_INTR() kobj methods are also
available to implement for similar purposes.
Discussed on: -arm, -mips
Tested by: zbb, brooks, imp, and others
MFC after: 6 weeks
allocates kva space from the top down for the device mappings and builds
entries in an internal table which is automatically used later by
arm_devmap_bootstrap(). The platform code just calls the new
arm_devmap_add_entry() function as many times as it needs to (up to 32
entries allowed; most platforms use 2 or 3 at most).
There is also a new arm_devmap_lastaddr() function that returns the lowest
kva address allocated; this can be used to implement initarm_lastaddr()
which is used to initialize vm_max_kernel_address.
The new code is based on a similar concept developed for the imx family
SoCs recently. They will soon be converted to use this new common code.
static device mappings, rather than as the first of the initializations
that a platform can hook into. This allows a platform to allocate KVA
from the top of the address space downwards for things like static device
mapping, and return the final "last usable address" result after that and
other early init work is done.
Because some platforms were doing work in initarm_lastaddr() that needs to
be done early, add a new initarm_early_init() routine and move the early
init code to that routine on those platforms.
Rename platform_devmap_init() to initarm_devmap_init() to match all the
other init routines called from initarm() that are designed to be
implemented by platform code.
Add a comment block that explains when these routines are called and the
type of work expected to be done in each of them.
new devmap.[ch] files. Emphasize the MD nature of these things by using
the prefix arm_devmap_ on the function and type names (already a few of
these things found their way into MI code, hopefully it will be harder to
do by accident in the future).
out common code related to mapping device memory into a new devmap.c file.
Remove the growing duplication of code that used pmap_devmap_find_pa() and
then did some math with the returned results to generate a virtual address,
and likewise in reverse to get a physical address. Now there are a pair
of functions, arm_devmap_vtop() and arm_devmap_ptov(), to do that. The
bus_space_map() implementations are rewritten in terms of these.
the essentially identical generic implementations instead. The generic
implementations differ only in the spelling of a couple variable names
and some formatting differences.
include it accordingly. The build machinery for universe and tinderbox
tries to build every kernel config whose name begins and ends with [A-Z0-9]
and the common include file that has most of the options isn't buildable
by itself, so the new lowercase .common will avoid building it.
accessed through the direct map unless the kernel configuration actually
includes a direct map. Only a few configurations do, and for the rest the
unnecessary free page pool is a small pessimization.
Tested by: zbb
MFC after: 6 weeks
Use the published compatible strings (our own invention, "ti,mmchs" is
still accepted as well, for now).
Don't blindly turn on 8-bit bus mode, because even though the conroller
supports it, the board has to be wired appropriately as well. Use the
published property (bus-width=<n>) and honor all the valid values (1,4,8).
The eMMC device on a Beaglebone Black is wired for 8-bit, update the dts.
The mmchs controller can inherently do both 1.8v and 3.0v on the first
device and 1.8v only on other devices, unless an external transceiver is
used. Set the voltage automatically for the first device and honor
the published fdt property (ti,dualvolt) for other devices.
Thanks go to Ilya Bakulin for figuring out the voltage compatibility stuff.
threaded handlers.
It's not easy to see from the diffs of this change exactly how it
accomplishes the above. The arm_mask_irq() and arm_unmask_irq() functions
are, respectively, the pre_thread and post_thread hooks. Not seen in
these diffs, the arm_post_filter() routine also EOIs. The post_filter
routine runs after filter handlers if there will be no threaded handlers,
so it just EOIs. The pre_thread routine masks the interrupt (at the
controller, not the source) and EOIs. So one way or another, the EOI
happens at the point where filter handlers are done.
the interrupt handler. If the event callback starts a new short timeout,
the timer can fire before returning from the event callback, and clearing
the interrupt status after that loses the interrupt and hangs until the
counter wraps. Fixing all of this removes the need for the do-nothing
loop at the top of the handler which really just waited for the counter to
roll over and reach the one-shot count again.
Also add a missing return(0) in the periodic timer start case.
Use values of the correct defines to determine statement's result.
ARM_ARCH_ symbols are always defined, hence only values are relevant.
Reviewed by: cognet
Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada
SoC family. Current in-tree support for PJ4Bv6 will not work and also
there should be no platforms in active use that would incorporate that
CPU revision.
Loading kernel to 0xf00000 has no practical reason.
Starting it from the u-boot's highest possible end address
(2MB counting from 0x0) makes more sense.
Tested by: kevlo
Depending on u-boot's flavor some boards have their SoC registers
base address configured to 0xD0000000 and other to 0xF1000000.
U-boot is passing currently set value via CP15 register.
In order to create proper mapping for SoC registers and allow further
successful initialization it is necessary to replace fdt_immr_pa with
the real value and eventually fix-up device tree blob.
Tested by: kevlo
Armada XP initialization flow requires SoC registers to be
mapped very early in order to configure Snoop Filter for SMP.
Additional mapping in locore.S is redundant as proper mapping is
made in pmap_devmap_bootstrap() prior to calling cpu_setup() which
configures the Snoop Filter.
For secondaru CPUs it is better to pass VA of the SoC
registers defined in MV_BASE and PA consistent with the value
in the Device Tree.
Tested by: kevlo
vm_pages. Provide trivial implementation which forwards the load to
_bus_dmamap_load_phys() page by page. Right now all architectures use
bus_dmamap_load_ma_triv().
Tested by: pho (as part of the functional patch)
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
The only remaining user was the code that allocates bounce pages for armv4
busdma. It's not clear why bounce pages would need uncached memory, but
if that ever changes, kmem_alloc_attr() would be the way to get it.
really need it. That would be almost everywhere it was included. Add
it in a couple files that really do need it and were previously getting
it by accident via another header.
included by vm/pmap.h, which is a prerequisite for arm/machine/pmap.h
so there's no reason to ever include it directly.
Thanks to alc@ for pointing this out.
of the address space downwards, and then returning the lowest mapped
device address from initarm_lastaddr(). This adds over 500MB of kva
space compared to the old way of hardcoding the end address as 0xE0000000.
Also, pre-map most of the SoC's common memory-mapped devices using 1MB
section mappings so that all device access uses just a few TLB entries.
Graphics devices aren't mapped this way yet, but probably should be.
To provide this new functionality without pasting identical code into
multiple imxNN_machdep.c files, rework the imx machdep code so that
things common to the whole family of SoCs are in a new imx_machdep.c file.
The rewritten imxNN_machdep.c files contain just things specific to an
individual SoC.
- The new allocator won't return coherent memory for any size > PAGE_SIZE,
so don't assume we have coherent memory, and explicitely use
bus_dmamap_sync().
Freescale SoCs including the i.MX series. This also works for the newer
SoCs with the ENET gigabit controller, but doesn't use any of the new
hardware features other than enabling gigabit speed.
the right register for power managment. It
was incorrectly using the clock register
which also caused the status to be the
opposite of what it is supposed to be.
1 - its disabled
0 - its enabled
Per kirkwood spec FSS_88F6180_9x_6281_OpenSource.pdf
