With some higher GCC/CLANG version, it is not recommended to use a
structure with a tailing flexible array inside another structure.
Accessing this array may be considered as a risk to corrupt the
following field even if it is by intention.
The error below was observed:
drivers/net/mlx5/linux/mlx5_ethdev_os.c: In function 'mlx5_get_flag_dropless_rq':
drivers/net/mlx5/linux/mlx5_ethdev_os.c:1679:42: error:
invalid use of structure with flexible array member [-Werror=pedantic]
1679 | struct ethtool_sset_info hdr;
| ^~~
Changing it to memory dynamic allocation method will help to get
rid of this complain.
Fixes: e848218741 ("net/mlx5: check delay drop settings in kernel driver")
Cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Add support of AVX512 vector data path for single queue model.
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Add Tx offloading support:
- support TSO for single queue model and split queue model.
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Add Rx offloading support:
- support CHKSUM and RSS offload for split queue model
- support CHKSUM offload for single queue model
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Enable write back on ITR expire, then packets can be received one by
one.
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Add basic Tx support in split queue mode and single queue mode.
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Add basic Rx support in split queue mode and single queue mode.
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Add support for tx_queue_setup ops.
In the single queue model, the same descriptor queue is used by SW to
post buffer descriptors to HW and by HW to post completed descriptors
to SW.
In the split queue model, "RX buffer queues" are used to pass
descriptor buffers from SW to HW while Rx queues are used only to
pass the descriptor completions, that is, descriptors that point
to completed buffers, from HW to SW. This is contrary to the single
queue model in which Rx queues are used for both purposes.
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Support device init and add the following dev ops:
- dev_configure
- dev_close
- dev_infos_get
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Introduce common library for IDPF (Infrastructure Data
Path Function) PMD.
Add base code and OS specific implementation first.
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Add check for null hash algorithm digest size.
Digest size should be 4B or request will be rejected.
Fixes: 1703e94ac5 ("qat: add driver for QuickAssist devices")
Cc: stable@dpdk.org
Signed-off-by: Brian Dooley <brian.dooley@intel.com>
Acked-by: Ciara Power <ciara.power@intel.com>
Add support for MD5, SHA1, SHA224, SHA256, SHA384, SHA512
Authentication algorithms with and without HMAC.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Add support for cipher algorithms,
including AES_ECB, AES_CBC, AES_XTS, and DES_CBC mode.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Support the basic dev control operations: configure, close, start,
stop and get info, as well as queue pairs operations.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Introduce a new crypto PMD for hardware accelerators based on UADK [1].
UADK is a framework for user applications to access hardware accelerators.
UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share
the same page table between IOMMU and MMU.
Thereby user application can directly use virtual address for device dma,
which enhances the performance as well as easy usability.
This patch adds the basic framework.
[1] https://github.com/Linaro/uadk
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Akhil Goyal <gakhil@marvell.com>
The index for sess_ctx was incorrect when setting the op session.
Fixes: 6812b9bf47 ("crypto/scheduler: use unified session")
Signed-off-by: Ciara Power <ciara.power@intel.com>
As the queue pair used in secondary process needs to be set up by
the primary process, this patch adds an IPC register function to help
secondary process to send out queue-pair setup request to primary
process via IPC request messages. A new "qp_in_used_pid" param stores
the PID to provide the ownership of the queue-pair so that only the PID
matched queue-pair can be free'd in the request.
Signed-off-by: Kai Ji <kai.ji@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
This patch fix the session pointer passed in set_session()
when ctx has NULL build request pointer in multi-processes
scenario.
Fixes: fb3b9f4922 ("crypto/qat: rework burst data path")
Cc: stable@dpdk.org
Signed-off-by: Kai Ji <kai.ji@intel.com>
Acked-by: Ciara Power <ciara.power@intel.com>
This commit adds verification option for elliptic curve
points when used along ECDH algorithm.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
This commit adds ECDH key exchange algorithm to Intel QuickAssist
Technology driver.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
All pointers passed to functions that are not supposed
to have its data changed should be marked as constant.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
For Kasumi cipher operation, IV is a must. Verify the arg provided in
session creation and remove datapath check.
Coverity issue: 381020, 381019
Fixes: 7a59ccc1b5 ("crypto/cnxk: remove extra indirection for FC and Kasumi")
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Add support to generate ipad and opad for MD5.
Skip the call to additional command WRITE_SA during SA creation.
Instead use the software defined function to generate opad and ipad.
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
For transport mode, IP header will not be part of encryption.
Update the response len calculation accordingly for transport mode.
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
AES-CMAC uses PDCP opcode and hence
length should be passed in bits.
Fixes: 759b5e6535 ("crypto/cnxk: support AES-CMAC")
Cc: stable@dpdk.org
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Read slice configuration of QAT capabilities.
This will allow to recognize if specific HW function
is available on particular generation of device.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
Read slice configuration of QAT capabilities.
This will allow to recognize if specific hw function
is available on particular generation of device.
Added function pointers for each QAT generations.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
Removed unnecessary session check which could lead to segfault,
in case api was changed.
Fixes: 002486db23 ("crypto/qat: refactor asymmetric session")
Cc: stable@dpdk.org
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Ciara Power <ciara.power@intel.com>
