Octeontx2 PMD's mailbox client uses device memory to send messages
to mailbox server in the admin function Linux kernel driver.
The device memory used for the mailbox communication needs to
be qualified as volatile memory type to avoid unaligned device
memory accesses because of compiler's memory access coalescing.
This patch modifies the mailbox request and responses as volatile
type which were non-volatile earlier and accessed from unaligned
memory addresses which resulted in bus errors on Fedora 30 with
gcc 9.1.1.
Fixes: 2b71657c86 ("common/octeontx2: add mbox request and response definition")
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Update workaround changes for erratas that are fixed on 96xx A1.
This patch also enables cq drop for all the passes for
maintaining performance along with updating a default
Rx ring size in dev_info.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Patch extends minimum supported max_sqb_count devarg value
such that it can limit the max sqb count to 8 buffers and
also defines NIX_DEF_SQB and uses it to compute the number
of sqe buffers required for the egress traffic.
NIX_DEF_SQB is defined as 16 which is optimal across multiple
octeontx2 platforms to scale up the performance proportional
to the corresponding port/queue to lcore mappings.
Fixes: fb0198b7dc ("net/octeontx2: add devargs parsing functions")
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
From B0 HW revision onwards, HW can drop the Rx and L2 error packets.
Enable this by default if the feature is available.
Since this bit field is used as reserved in old HW revisions,
No need to have additional HW version check.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
In case of QINT interrupt occurrence, SW fails to clear the QINT
line resulting in recursive interrupts because currently interrupt
handler gets the cause of the interrupt by reading
NIX_LF_RQ[SQ/CQ/AURA/POOL]_OP_INT but does not write 1 to clear
RQ[SQ/CQ/ERR]_INT field in respective NIX_LF_RQ[SQ/CQ/AURA/POOL]_OP_INT
registers.
Fixes: dc47ba15f6 ("net/octeontx2: handle queue specific error interrupts")
Fixes: 50b95c3ea7 ("mempool/octeontx2: add NPA IRQ handler")
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Adding support to parse GRE KEY for octeontx2 Flow.
Matching on GRE Key will only work, if checksum and routing
bits in the GRE header are equal to 0.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This patch implements read clock api whose purpose is to return
raw clock ticks. Using this API real time ticks spent in
processing a packet can be known:
<read_clock val at any time> - mbuf->timestamp
Calling mbox for reading raw clock ticks in fastpath is very
expensive so its value is derived from time stamp counter(tsc)
using freq multiplier (ratio of raw clock ticks and tsc) and clock
delta (by how much tsc is lagging from raw clock value).
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
A huge drop in per core MPPS value was observed when PTP stack is
enabled. The reason behind the bottleneck is HW serialises the
transfer of all SQEs, which seeks timestamp capture, on the same
send DMA path. Hence only those packets which requires timestamp
capture should set SETTSTAMP in send mem alg.
With this patch timestamping would be done only for those packets
with PKT_TX_IEEE1588_TMST set.
Fixes: fb3ae0951a ("net/octeontx2: support Tx")
Fixes: 8980a15300 ("event/octeontx2: support PTP for SSO")
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Earlier implementation for enabling ptp via RX offload flag was
causing segmentation fault as it was getting executed in the
device configuration stage where RX and TX queues were not
configured. As in the ptp enable process rx queues are used for
mbuf setup while tx queues are used for send descriptor setup.
Moving the logic in dev start as all the resources will be
configured.
Fixes: b5dc314044 ("net/octeontx2: support base PTP")
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Multi segmented packet may be spliced with indirect mbufs also.
Currently driver causes buffer leak for indirect mbufs as they
were not being freed to packet pool.
Patch fixes handling of indirect mbufs for following use cases
- packet contains all indirect mbufs only.
- packet contains mixed mbufs i.e. direct and indirect both.
Fixes: cbd5710db4 ("net/octeontx2: add Tx multi segment version")
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
When configure returns error, e.g. in case not supported offloads
(outer ip and sctp) driver released Rx,Tx queues. Then in case of
correct configuration the driver could not start due to queues already
released but the driver thought it was configured correctly.
Secondly if driver returns error from configuration librte_ethdev will
release, rx queues and tx queues, without chaining driver configured
state.
Fix that by 'releasing' configuration and changing driver state when
error is returned from otx2_nix_configure.
Fixes: 548b5839a3 ("net/octeontx2: add device configure operation")
Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
Reviewed-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Adding support for ipv6_ext header parsing in the octeontx2 flow.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add build bug on on fast path used fields that are
dependent on their positions and values.
Fixes: f1eff76ab6 ("net/octeontx2: add Rx vector version")
Fixes: ddc1bc26e9 ("net/octeontx2: add Tx vector version")
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Adding support for flags based extraction in octeontx2 Flow.
Patch supports extracting data greater than 32 bytes using lflags.
When flags based extraction is enabled, lower 4 bits will be
considered (16 flags) for indexing the flags, and will be used
for extraction.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Adding PF and VF action support for octeontx2 flow driver.
If RTE_FLOW_ACTION_TYPE_PF action is set from VF, then the packet
will be sent to the parent PF.
If RTE_FLOW_ACTION_TYPE_VF action is set and original is specified,
then the packet will be sent to the original VF, otherwise the packet
will be sent to the VF specified in the vf_id.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
In order to align name with other PCI driver flag such as
RTE_PCI_DRV_NEED_MAPPING and to reflect its purpose, change
RTE_PCI_DRV_IOVA_AS_VA flag name as RTE_PCI_DRV_NEED_IOVA_AS_VA.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
The incriminated commit broke the use of RTE_PCI_DRV_IOVA_AS_VA which
was intended to mean "driver only supports VA" but had been understood
as "driver supports both PA and VA" by most net drivers and used to let
dpdk processes to run as non root (which do not have access to physical
addresses on recent kernels).
The check on physical addresses actually closed the gap for those
drivers. We don't need to mark them with RTE_PCI_DRV_IOVA_AS_VA and this
flag can retain its intended meaning.
Document explicitly its meaning.
We can check that a driver requirement wrt to IOVA mode is fulfilled
before trying to probe a device.
Finally, document the heuristic used to select the IOVA mode and hope
that we won't break it again.
Fixes: 703458e19c ("bus/pci: consider only usable devices for IOVA mode")
Signed-off-by: David Marchand <david.marchand@redhat.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Tested-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
Update platform support of CNF95xx in documentation and
also, update the HW cap based on PCI subsystem id and revision id.
This patch also changes HW capability handling to be based on
PCI Revision ID. PCI Revision ID contains a unique identifier
to identify chip, major and minor revisions.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Formatting Ethernet address and getting a random value are
not in critical path so they should not be inlined.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Rami Rosen <ramirose@gmail.com>
Reviewed-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
Add support for setting the link up and down.
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
This patch implements rx interrupts feature required for power
saving. These interrupts can be enabled/disabled on demand.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add MTU set operation and MTU update feature.
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add device start operation and update the correct
function pointers for Rx and Tx burst functions.
This patch also update the octeontx2 NIC specific documentation.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Add vector version of packet Receive function.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Implement support for setting VLAN TPID and PVID for Tx packets.
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Support setting up VLAN filters so as to allow tagged
packet's reception after VLAN HW Filter offload is enabled.
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Support configuring VLAN offloads for an ethernet device and
dynamic promiscuous mode configuration for VLAN filters where
filters are updated according to promiscuous mode of the device.
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Adding the flow init and fini functionality. These will be called from
dev init and will initialize and de-initialize the flow related memory.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Adding few more flow operations like flow_destroy, flow_isolate
and flow_flush.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Adding the initial flow ops like flow_create and flow_validate.
These will be used to alloc and write flow rule to device and
validate the flow rule.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Adding support to parse flow actions like drop, count, mark, rss, queue.
On egress side, only drop and count actions were supported.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Adding functionality to parse inner layers from la to lc.
These will be used to parse inner layers L2, L3, L4 types.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Adding functionality to parse outer layers from ld to lh.
These will be used parse outer layers L2, L3, L4 and tunnel types.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Adding MCAM utility functions to alloc and write the entries.
These will be used to arrange the flow rules based on priority.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Adding mailbox utility functions for rte_flow. These will be used
to alloc, reserve and write the entries to the device on request.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
First pass rte_flow utility functions for octeontx2.
These will be used to communicate with AF driver.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Introducing flow infra for octeontx2.
This will be used to maintain rte_flow rules.
Create, destroy, validate, query, flush, isolate flow operations
will be supported.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vivek Sharma <viveksharma@marvell.com>
Add remaining PTP configuration/slowpath operations.
Timesync feature is available only for PF devices.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Zyta Szpak <zyta@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add flow control operations and exposed
otx2_nix_update_flow_ctrl_mode() to enable on the
configured mode in dev_start().
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
