New port mode names are defined for Medford2 and later, and
the existing names are aliased to them. Add comments with the
numeric port mode to clarify the external port modes table.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
The event timer interface has changed for Medford2 - for
details see bug66418 comment 9. Update the common code to
use the new timer semantics for Medford2.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Medford2 controllers support control and reporting of
FEC modes for 25G and higher links. See SF-109306-TC
for suggested usage in client code.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
The RX_ECC_ERR flag in RX events was misnamed, as it
reported frame truncation. Use the new RX_TRUNC_ERR
name for this flag.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Decode Medford2 FEC stats if available in MAC stats DMA buffer.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
On Medford2 and later the MAC stats buffer has been enlarged.
Use the MAC stats DMA buffer size to ensure that the stats END
generation count is read from the correct location, and that
over-reading of the DMA buffer is prevented.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
For Medford2 the DMA buffer used for one-shot or periodic MAC stats
has been extended. Ensure the MAC stats DMA buffer size is large
enough to hold the number of stats counters supported by firmware.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Previously the code relied on the callers of efx_mcdi_mac_stats
to provide a DMA buffer or NULL depending on the action. Fix
this so that the DMA buffer is only passed in the request when
needed, and that an error is reported for a missing DMA buffer.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
This reports the number of stats (and hence the DMA buffer size)
for MAC stats. If MC_GET_CAPABABILITIES_V4 is not supported then
use the legacy Siena-compatible MC_CMD_MAC_NSTATS value.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Inline efx_mcdi_get_capabilities() to prepare for reading
newer capabilities response versions.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
EFSYS_MEM_SIZE() reports the DMA mapped size of an efsys_mem_t
allocated region (the allocation size may be different due to
memory allocator and DMA alignment restrictions).
This ensures that common code internals have explicit knowledge
of the usable size of DMA mapped memory regions.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Report supported loopback modes for new Medford2 link speeds.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Add basic support for new link modes for Medford2.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
On Medford and earlier controllers the BAR layout is:
PF BAR 0: (32bit I/O) I/O mapped registers
PF BAR 2: (64bit Mem) Memory mapped registers (VI aperture)
PF BAR 4: (64bit Mem) MSI-X tables
VF BAR 0: (64bit Mem) Memory mapped registers (VI aperture)
VF BAR 2: (64bit Mem) MSI-X tables
On Medford2, the layout is:
PF/VF BAR 0: (64bit Mem) Memory mapped registers (VI aperture)
PF/VF BAR 2: (64bit Mem) MSI-X tables
Make the VI aperture BAR number available for drivers that need it.
Remove EFX_MEM_BAR define as it it is not correct on all platforms.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Addresses most of the warnings reported by the sfn windows driver.
Signed-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
The changes to efx_regs_ef10.h are auto-generated and include:
- Updated event RX_L4_CLASS which is now 2 bits (was 3).
The encoding of TCP, UDP and UNKNOWN are unchanged so
the narrower Medford2 field definition is compatible with
all controllers.
- Fix definition of FATSOv2 option descriptors. These were
added manually and differ from the auto-generated values
in some fields (not yet used in common code). The field
definitions have been corrected to agree with the Linux net
driver headers and SF-108452-SW.
The remaining changes adapt the common code to use the updated
headers.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Medford2 uses a configurable VI window size, and requires
updates to register accesses to use a runtime VI window size
rather than the *_STEP register constants used for earlier
controllers.
Update the common code to query the VI window size via MCDI,
and add new EFX_BAR_VI_* accessor macros for per-VI registers.
The existing EFX_BAR_TBL_* macros can be used for non-VI
register tables (and for code that can never be called for
a Medford2 controller e.g. Siena-only code).
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
