d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
d96aeddf2f
freebsd-dev/sys/dev/hwpmc/pmc_events.h

6912 lines
333 KiB
C
Raw Normal View History

MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
/*-
* Copyright (c) 2005 Joseph Koshy
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _DEV_HWPMC_PMC_EVENTS_H_
#define _DEV_HWPMC_PMC_EVENTS_H_
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
/*
Add counters for the i7 architecture which were accidentally left out of the original commit of i7 support. These are all the counters on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B_, June 2009. Almost all of these counters relate to operations on the L2 cache. Reviewed by: jkoshy MFC after: 1 month
2009-09-01 17:55:37 +00:00
* Note: Documentation on adding events can be found both in
* the source tree at src/share/doc/papers/hwpmc/hwpmc.ms
* as well as on-line at:
*
* http://wiki.freebsd.org/PmcTools/PmcHardwareHowTo
*
* Please refer to those resources before you attempt to modify
* this file or the hwpmc driver/subsystem.
*/
/* * PMC event codes.
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
*
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
* __PMC_EV(CLASS, SYMBOLIC-NAME)
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
*
*/
/*
* AMD K7 Events, from "The AMD Athlon(tm) Processor x86 Code
* Optimization Guide" [Doc#22007K, Feb 2002]
*/
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
#define __PMC_EV_K7() \
__PMC_EV(K7, DC_ACCESSES) \
__PMC_EV(K7, DC_MISSES) \
__PMC_EV(K7, DC_REFILLS_FROM_L2) \
__PMC_EV(K7, DC_REFILLS_FROM_SYSTEM) \
__PMC_EV(K7, DC_WRITEBACKS) \
__PMC_EV(K7, L1_DTLB_MISS_AND_L2_DTLB_HITS) \
__PMC_EV(K7, L1_AND_L2_DTLB_MISSES) \
__PMC_EV(K7, MISALIGNED_REFERENCES) \
__PMC_EV(K7, IC_FETCHES) \
__PMC_EV(K7, IC_MISSES) \
__PMC_EV(K7, L1_ITLB_MISSES) \
__PMC_EV(K7, L1_L2_ITLB_MISSES) \
__PMC_EV(K7, RETIRED_INSTRUCTIONS) \
__PMC_EV(K7, RETIRED_OPS) \
__PMC_EV(K7, RETIRED_BRANCHES) \
__PMC_EV(K7, RETIRED_BRANCHES_MISPREDICTED) \
__PMC_EV(K7, RETIRED_TAKEN_BRANCHES) \
__PMC_EV(K7, RETIRED_TAKEN_BRANCHES_MISPREDICTED) \
__PMC_EV(K7, RETIRED_FAR_CONTROL_TRANSFERS) \
__PMC_EV(K7, RETIRED_RESYNC_BRANCHES) \
__PMC_EV(K7, INTERRUPTS_MASKED_CYCLES) \
__PMC_EV(K7, INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \
__PMC_EV(K7, HARDWARE_INTERRUPTS)
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
#define PMC_EV_K7_FIRST PMC_EV_K7_DC_ACCESSES
#define PMC_EV_K7_LAST PMC_EV_K7_HARDWARE_INTERRUPTS
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
/*
* Intel P4 Events, from "IA-32 Intel(r) Architecture Software
* Developer's Manual, Volume 3: System Programming Guide" [245472-012]
*/
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
#define __PMC_EV_P4() \
__PMC_EV(P4, TC_DELIVER_MODE) \
__PMC_EV(P4, BPU_FETCH_REQUEST) \
__PMC_EV(P4, ITLB_REFERENCE) \
__PMC_EV(P4, MEMORY_CANCEL) \
__PMC_EV(P4, MEMORY_COMPLETE) \
__PMC_EV(P4, LOAD_PORT_REPLAY) \
__PMC_EV(P4, STORE_PORT_REPLAY) \
__PMC_EV(P4, MOB_LOAD_REPLAY) \
__PMC_EV(P4, PAGE_WALK_TYPE) \
__PMC_EV(P4, BSQ_CACHE_REFERENCE) \
__PMC_EV(P4, IOQ_ALLOCATION) \
__PMC_EV(P4, IOQ_ACTIVE_ENTRIES) \
__PMC_EV(P4, FSB_DATA_ACTIVITY) \
__PMC_EV(P4, BSQ_ALLOCATION) \
__PMC_EV(P4, BSQ_ACTIVE_ENTRIES) \
__PMC_EV(P4, SSE_INPUT_ASSIST) \
__PMC_EV(P4, PACKED_SP_UOP) \
__PMC_EV(P4, PACKED_DP_UOP) \
__PMC_EV(P4, SCALAR_SP_UOP) \
__PMC_EV(P4, SCALAR_DP_UOP) \
__PMC_EV(P4, 64BIT_MMX_UOP) \
__PMC_EV(P4, 128BIT_MMX_UOP) \
__PMC_EV(P4, X87_FP_UOP) \
__PMC_EV(P4, X87_SIMD_MOVES_UOP) \
__PMC_EV(P4, GLOBAL_POWER_EVENTS) \
__PMC_EV(P4, TC_MS_XFER) \
__PMC_EV(P4, UOP_QUEUE_WRITES) \
__PMC_EV(P4, RETIRED_MISPRED_BRANCH_TYPE) \
__PMC_EV(P4, RETIRED_BRANCH_TYPE) \
__PMC_EV(P4, RESOURCE_STALL) \
__PMC_EV(P4, WC_BUFFER) \
__PMC_EV(P4, B2B_CYCLES) \
__PMC_EV(P4, BNR) \
__PMC_EV(P4, SNOOP) \
__PMC_EV(P4, RESPONSE) \
__PMC_EV(P4, FRONT_END_EVENT) \
__PMC_EV(P4, EXECUTION_EVENT) \
__PMC_EV(P4, REPLAY_EVENT) \
__PMC_EV(P4, INSTR_RETIRED) \
__PMC_EV(P4, UOPS_RETIRED) \
__PMC_EV(P4, UOP_TYPE) \
__PMC_EV(P4, BRANCH_RETIRED) \
__PMC_EV(P4, MISPRED_BRANCH_RETIRED) \
__PMC_EV(P4, X87_ASSIST) \
__PMC_EV(P4, MACHINE_CLEAR)
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
#define PMC_EV_P4_FIRST PMC_EV_P4_TC_DELIVER_MODE
#define PMC_EV_P4_LAST PMC_EV_P4_MACHINE_CLEAR
/* Intel Pentium Pro, P-II, P-III and Pentium-M style events */
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
#define __PMC_EV_P6() \
__PMC_EV(P6, DATA_MEM_REFS) \
__PMC_EV(P6, DCU_LINES_IN) \
__PMC_EV(P6, DCU_M_LINES_IN) \
__PMC_EV(P6, DCU_M_LINES_OUT) \
__PMC_EV(P6, DCU_MISS_OUTSTANDING) \
__PMC_EV(P6, IFU_FETCH) \
__PMC_EV(P6, IFU_FETCH_MISS) \
__PMC_EV(P6, ITLB_MISS) \
__PMC_EV(P6, IFU_MEM_STALL) \
__PMC_EV(P6, ILD_STALL) \
__PMC_EV(P6, L2_IFETCH) \
__PMC_EV(P6, L2_LD) \
__PMC_EV(P6, L2_ST) \
__PMC_EV(P6, L2_LINES_IN) \
__PMC_EV(P6, L2_LINES_OUT) \
__PMC_EV(P6, L2_M_LINES_INM) \
__PMC_EV(P6, L2_M_LINES_OUTM) \
__PMC_EV(P6, L2_RQSTS) \
__PMC_EV(P6, L2_ADS) \
__PMC_EV(P6, L2_DBUS_BUSY) \
__PMC_EV(P6, L2_DBUS_BUSY_RD) \
__PMC_EV(P6, BUS_DRDY_CLOCKS) \
__PMC_EV(P6, BUS_LOCK_CLOCKS) \
__PMC_EV(P6, BUS_REQ_OUTSTANDING) \
__PMC_EV(P6, BUS_TRAN_BRD) \
__PMC_EV(P6, BUS_TRAN_RFO) \
__PMC_EV(P6, BUS_TRANS_WB) \
__PMC_EV(P6, BUS_TRAN_IFETCH) \
__PMC_EV(P6, BUS_TRAN_INVAL) \
__PMC_EV(P6, BUS_TRAN_PWR) \
__PMC_EV(P6, BUS_TRANS_P) \
__PMC_EV(P6, BUS_TRANS_IO) \
__PMC_EV(P6, BUS_TRAN_DEF) \
__PMC_EV(P6, BUS_TRAN_BURST) \
__PMC_EV(P6, BUS_TRAN_ANY) \
__PMC_EV(P6, BUS_TRAN_MEM) \
__PMC_EV(P6, BUS_DATA_RCV) \
__PMC_EV(P6, BUS_BNR_DRV) \
__PMC_EV(P6, BUS_HIT_DRV) \
__PMC_EV(P6, BUS_HITM_DRV) \
__PMC_EV(P6, BUS_SNOOP_STALL) \
__PMC_EV(P6, FLOPS) \
__PMC_EV(P6, FP_COMPS_OPS_EXE) \
__PMC_EV(P6, FP_ASSIST) \
__PMC_EV(P6, MUL) \
__PMC_EV(P6, DIV) \
__PMC_EV(P6, CYCLES_DIV_BUSY) \
__PMC_EV(P6, LD_BLOCKS) \
__PMC_EV(P6, SB_DRAINS) \
__PMC_EV(P6, MISALIGN_MEM_REF) \
__PMC_EV(P6, EMON_KNI_PREF_DISPATCHED) \
__PMC_EV(P6, EMON_KNI_PREF_MISS) \
__PMC_EV(P6, INST_RETIRED) \
__PMC_EV(P6, UOPS_RETIRED) \
__PMC_EV(P6, INST_DECODED) \
__PMC_EV(P6, EMON_KNI_INST_RETIRED) \
__PMC_EV(P6, EMON_KNI_COMP_INST_RET) \
__PMC_EV(P6, HW_INT_RX) \
__PMC_EV(P6, CYCLES_INT_MASKED) \
__PMC_EV(P6, CYCLES_INT_PENDING_AND_MASKED) \
__PMC_EV(P6, BR_INST_RETIRED) \
__PMC_EV(P6, BR_MISS_PRED_RETIRED) \
__PMC_EV(P6, BR_TAKEN_RETIRED) \
__PMC_EV(P6, BR_MISS_PRED_TAKEN_RET) \
__PMC_EV(P6, BR_INST_DECODED) \
__PMC_EV(P6, BTB_MISSES) \
__PMC_EV(P6, BR_BOGUS) \
__PMC_EV(P6, BACLEARS) \
__PMC_EV(P6, RESOURCE_STALLS) \
__PMC_EV(P6, PARTIAL_RAT_STALLS) \
__PMC_EV(P6, SEGMENT_REG_LOADS) \
__PMC_EV(P6, CPU_CLK_UNHALTED) \
__PMC_EV(P6, MMX_INSTR_EXEC) \
__PMC_EV(P6, MMX_SAT_INSTR_EXEC) \
__PMC_EV(P6, MMX_UOPS_EXEC) \
__PMC_EV(P6, MMX_INSTR_TYPE_EXEC) \
__PMC_EV(P6, FP_MMX_TRANS) \
__PMC_EV(P6, MMX_ASSIST) \
__PMC_EV(P6, MMX_INSTR_RET) \
__PMC_EV(P6, SEG_RENAME_STALLS) \
__PMC_EV(P6, SEG_REG_RENAMES) \
__PMC_EV(P6, RET_SEG_RENAMES) \
__PMC_EV(P6, EMON_EST_TRANS) \
__PMC_EV(P6, EMON_THERMAL_TRIP) \
__PMC_EV(P6, BR_INST_EXEC) \
__PMC_EV(P6, BR_MISSP_EXEC) \
__PMC_EV(P6, BR_BAC_MISSP_EXEC) \
__PMC_EV(P6, BR_CND_EXEC) \
__PMC_EV(P6, BR_CND_MISSP_EXEC) \
__PMC_EV(P6, BR_IND_EXEC) \
__PMC_EV(P6, BR_IND_MISSP_EXEC) \
__PMC_EV(P6, BR_RET_EXEC) \
__PMC_EV(P6, BR_RET_MISSP_EXEC) \
__PMC_EV(P6, BR_RET_BAC_MISSP_EXEC) \
__PMC_EV(P6, BR_CALL_EXEC) \
__PMC_EV(P6, BR_CALL_MISSP_EXEC) \
__PMC_EV(P6, BR_IND_CALL_EXEC) \
__PMC_EV(P6, EMON_SIMD_INSTR_RETIRED) \
__PMC_EV(P6, EMON_SYNCH_UOPS) \
__PMC_EV(P6, EMON_ESP_UOPS) \
__PMC_EV(P6, EMON_FUSED_UOPS_RET) \
__PMC_EV(P6, EMON_UNFUSION) \
__PMC_EV(P6, EMON_PREF_RQSTS_UP) \
__PMC_EV(P6, EMON_PREF_RQSTS_DN) \
__PMC_EV(P6, EMON_SSE_SSE2_INST_RETIRED) \
__PMC_EV(P6, EMON_SSE_SSE2_COMP_INST_RETIRED)
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
#define PMC_EV_P6_FIRST PMC_EV_P6_DATA_MEM_REFS
#define PMC_EV_P6_LAST PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED
/* AMD K8 PMCs */
#define __PMC_EV_K8() \
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
__PMC_EV(K8, FP_DISPATCHED_FPU_OPS) \
__PMC_EV(K8, FP_CYCLES_WITH_NO_FPU_OPS_RETIRED) \
__PMC_EV(K8, FP_DISPATCHED_FPU_FAST_FLAG_OPS) \
__PMC_EV(K8, LS_SEGMENT_REGISTER_LOAD) \
__PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE) \
__PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \
__PMC_EV(K8, LS_BUFFER2_FULL) \
__PMC_EV(K8, LS_LOCKED_OPERATION) \
__PMC_EV(K8, LS_MICROARCHITECTURAL_LATE_CANCEL) \
__PMC_EV(K8, LS_RETIRED_CFLUSH_INSTRUCTIONS) \
__PMC_EV(K8, LS_RETIRED_CPUID_INSTRUCTIONS) \
__PMC_EV(K8, DC_ACCESS) \
__PMC_EV(K8, DC_MISS) \
__PMC_EV(K8, DC_REFILL_FROM_L2) \
__PMC_EV(K8, DC_REFILL_FROM_SYSTEM) \
__PMC_EV(K8, DC_COPYBACK) \
__PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_HIT) \
__PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_MISS) \
__PMC_EV(K8, DC_MISALIGNED_DATA_REFERENCE) \
__PMC_EV(K8, DC_MICROARCHITECTURAL_LATE_CANCEL) \
__PMC_EV(K8, DC_MICROARCHITECTURAL_EARLY_CANCEL) \
__PMC_EV(K8, DC_ONE_BIT_ECC_ERROR) \
__PMC_EV(K8, DC_DISPATCHED_PREFETCH_INSTRUCTIONS) \
__PMC_EV(K8, DC_DCACHE_ACCESSES_BY_LOCKS) \
__PMC_EV(K8, BU_CPU_CLK_UNHALTED) \
__PMC_EV(K8, BU_INTERNAL_L2_REQUEST) \
__PMC_EV(K8, BU_FILL_REQUEST_L2_MISS) \
__PMC_EV(K8, BU_FILL_INTO_L2) \
__PMC_EV(K8, IC_FETCH) \
__PMC_EV(K8, IC_MISS) \
__PMC_EV(K8, IC_REFILL_FROM_L2) \
__PMC_EV(K8, IC_REFILL_FROM_SYSTEM) \
__PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_HIT) \
__PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_MISS) \
__PMC_EV(K8, IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \
__PMC_EV(K8, IC_INSTRUCTION_FETCH_STALL) \
__PMC_EV(K8, IC_RETURN_STACK_HIT) \
__PMC_EV(K8, IC_RETURN_STACK_OVERFLOW) \
__PMC_EV(K8, FR_RETIRED_X86_INSTRUCTIONS) \
__PMC_EV(K8, FR_RETIRED_UOPS) \
__PMC_EV(K8, FR_RETIRED_BRANCHES) \
__PMC_EV(K8, FR_RETIRED_BRANCHES_MISPREDICTED) \
__PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES) \
__PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED) \
__PMC_EV(K8, FR_RETIRED_FAR_CONTROL_TRANSFERS) \
__PMC_EV(K8, FR_RETIRED_RESYNCS) \
__PMC_EV(K8, FR_RETIRED_NEAR_RETURNS) \
__PMC_EV(K8, FR_RETIRED_NEAR_RETURNS_MISPREDICTED) \
__PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE) \
__PMC_EV(K8, FR_RETIRED_FPU_INSTRUCTIONS) \
__PMC_EV(K8, FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS) \
__PMC_EV(K8, FR_INTERRUPTS_MASKED_CYCLES) \
__PMC_EV(K8, FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \
__PMC_EV(K8, FR_TAKEN_HARDWARE_INTERRUPTS) \
__PMC_EV(K8, FR_DECODER_EMPTY) \
__PMC_EV(K8, FR_DISPATCH_STALLS) \
__PMC_EV(K8, FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE) \
__PMC_EV(K8, FR_DISPATCH_STALL_FOR_SERIALIZATION) \
__PMC_EV(K8, FR_DISPATCH_STALL_FOR_SEGMENT_LOAD) \
__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL) \
__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL) \
__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FPU_IS_FULL) \
__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_LS_IS_FULL) \
__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET) \
__PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING) \
__PMC_EV(K8, FR_FPU_EXCEPTIONS) \
__PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR0) \
__PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR1) \
__PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR2) \
__PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR3) \
__PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT) \
__PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW) \
__PMC_EV(K8, NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED) \
__PMC_EV(K8, NB_MEMORY_CONTROLLER_TURNAROUND) \
__PMC_EV(K8, NB_MEMORY_CONTROLLER_BYPASS_SATURATION) \
__PMC_EV(K8, NB_SIZED_COMMANDS) \
__PMC_EV(K8, NB_PROBE_RESULT) \
__PMC_EV(K8, NB_HT_BUS0_BANDWIDTH) \
__PMC_EV(K8, NB_HT_BUS1_BANDWIDTH) \
__PMC_EV(K8, NB_HT_BUS2_BANDWIDTH)
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
#define PMC_EV_K8_FIRST PMC_EV_K8_FP_DISPATCHED_FPU_OPS
#define PMC_EV_K8_LAST PMC_EV_K8_NB_HT_BUS2_BANDWIDTH
Correct a typo.
2008-03-14 06:16:18 +00:00
/*
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
* Intel Pentium and Pentium MMX events, from the "Intel 64 and IA-32
* Architectures Software Developer's Manual, Volume 3B: System Programming
* Guide, Part 2, August 2007".
Correct a typo.
2008-03-14 06:16:18 +00:00
*/
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
#define __PMC_EV_P5() \
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
__PMC_EV(P5, DATA_READ) \
__PMC_EV(P5, DATA_WRITE) \
__PMC_EV(P5, DATA_TLB_MISS) \
__PMC_EV(P5, DATA_READ_MISS) \
__PMC_EV(P5, DATA_WRITE_MISS) \
__PMC_EV(P5, WRITE_HIT_TO_M_OR_E_STATE_LINES) \
__PMC_EV(P5, DATA_CACHE_LINES_WRITTEN_BACK) \
__PMC_EV(P5, EXTERNAL_SNOOPS) \
__PMC_EV(P5, EXTERNAL_DATA_CACHE_SNOOP_HITS) \
__PMC_EV(P5, MEMORY_ACCESSES_IN_BOTH_PIPES) \
__PMC_EV(P5, BANK_CONFLICTS) \
__PMC_EV(P5, MISALIGNED_DATA_OR_IO_REFERENCES) \
__PMC_EV(P5, CODE_READ) \
__PMC_EV(P5, CODE_TLB_MISS) \
__PMC_EV(P5, CODE_CACHE_MISS) \
__PMC_EV(P5, ANY_SEGMENT_REGISTER_LOADED) \
__PMC_EV(P5, BRANCHES) \
__PMC_EV(P5, BTB_HITS) \
__PMC_EV(P5, TAKEN_BRANCH_OR_BTB_HIT) \
__PMC_EV(P5, PIPELINE_FLUSHES) \
__PMC_EV(P5, INSTRUCTIONS_EXECUTED) \
__PMC_EV(P5, INSTRUCTIONS_EXECUTED_V_PIPE) \
__PMC_EV(P5, BUS_CYCLE_DURATION) \
__PMC_EV(P5, WRITE_BUFFER_FULL_STALL_DURATION) \
__PMC_EV(P5, WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION) \
__PMC_EV(P5, STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE) \
__PMC_EV(P5, LOCKED_BUS_CYCLE) \
__PMC_EV(P5, IO_READ_OR_WRITE_CYCLE) \
__PMC_EV(P5, NONCACHEABLE_MEMORY_READS) \
__PMC_EV(P5, PIPELINE_AGI_STALLS) \
__PMC_EV(P5, FLOPS) \
__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR0_REGISTER) \
__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR1_REGISTER) \
__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR2_REGISTER) \
__PMC_EV(P5, BREAKPOINT_MATCH_ON_DR3_REGISTER) \
__PMC_EV(P5, HARDWARE_INTERRUPTS) \
__PMC_EV(P5, DATA_READ_OR_WRITE) \
__PMC_EV(P5, DATA_READ_MISS_OR_WRITE_MISS) \
__PMC_EV(P5, BUS_OWNERSHIP_LATENCY) \
__PMC_EV(P5, BUS_OWNERSHIP_TRANSFERS) \
__PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_U_PIPE) \
__PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_V_PIPE) \
__PMC_EV(P5, CACHE_M_LINE_SHARING) \
__PMC_EV(P5, CACHE_LINE_SHARING) \
__PMC_EV(P5, EMMS_INSTRUCTIONS_EXECUTED) \
__PMC_EV(P5, TRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS) \
__PMC_EV(P5, BUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY) \
__PMC_EV(P5, WRITES_TO_NONCACHEABLE_MEMORY) \
__PMC_EV(P5, SATURATING_MMX_INSTRUCTIONS_EXECUTED) \
__PMC_EV(P5, SATURATIONS_PERFORMED) \
__PMC_EV(P5, NUMBER_OF_CYCLES_NOT_IN_HALT_STATE) \
__PMC_EV(P5, DATA_CACHE_TLB_MISS_STALL_DURATION) \
__PMC_EV(P5, MMX_INSTRUCTION_DATA_READS) \
__PMC_EV(P5, MMX_INSTRUCTION_DATA_READ_MISSES) \
__PMC_EV(P5, FLOATING_POINT_STALLS_DURATION) \
__PMC_EV(P5, TAKEN_BRANCHES) \
__PMC_EV(P5, D1_STARVATION_AND_FIFO_IS_EMPTY) \
__PMC_EV(P5, D1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO) \
__PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITES) \
__PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITE_MISSES) \
__PMC_EV(P5, PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS) \
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
__PMC_EV(P5, \
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS_RESOLVED_IN_WB_STAGE) \
__PMC_EV(P5, MISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS) \
__PMC_EV(P5, PIPELINE_STALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS) \
__PMC_EV(P5, MISPREDICTED_OR_UNPREDICTED_RETURNS) \
__PMC_EV(P5, PREDICTED_RETURNS) \
__PMC_EV(P5, MMX_MULTIPLY_UNIT_INTERLOCK) \
__PMC_EV(P5, MOVD_MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION) \
__PMC_EV(P5, RETURNS) \
__PMC_EV(P5, BTB_FALSE_ENTRIES) \
__PMC_EV(P5, BTB_MISS_PREDICTION_ON_NOT_TAKEN_BRANCH) \
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
__PMC_EV(P5, \
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
FULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS) \
__PMC_EV(P5, STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE)
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
#define PMC_EV_P5_FIRST PMC_EV_P5_DATA_READ
#define PMC_EV_P5_LAST \
PMC_EV_P5_STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
/*
* Events supported by Intel architectural fixed function counters,
* from the "Intel 64 and IA-32 Architectures Software Developer's
* Manual Volume 3B: System Programming Guide, Part 2", July 2008.
*/
#define __PMC_EV_IAF() \
__PMC_EV(IAF, INSTR_RETIRED_ANY) \
__PMC_EV(IAF, CPU_CLK_UNHALTED_CORE) \
__PMC_EV(IAF, CPU_CLK_UNHALTED_REF)
#define PMC_EV_IAF_FIRST PMC_EV_IAF_INSTR_RETIRED_ANY
#define PMC_EV_IAF_LAST PMC_EV_IAF_CPU_CLK_UNHALTED_REF
Add aliases that map architectural event names to fixed function counters.
2008-12-03 15:23:08 +00:00
#define __PMC_EV_ALIAS_IAF() \
__PMC_EV_ALIAS("instruction-retired", IAF_INSTR_RETIRED_ANY) \
__PMC_EV_ALIAS("unhalted-core-cycles", IAF_CPU_CLK_UNHALTED_CORE) \
__PMC_EV_ALIAS("unhalted-reference-cycles", IAF_CPU_CLK_UNHALTED_REF)
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
/*
* Events supported by programmable function counters present in
* Intel Atom, Core and Core2 CPUs, from the "Intel 64 and IA-32
* Architectures Software Developer's Manual Volume 3B: System Programming
* Guide, Part 2", July 2008.
*
* These PMCs select events with a combination of an event code and
* unit mask. Quirks that need to be taken care of include:
* - The set of (event code, umask) combinations supported by a processor
* varies according to the processor model.
* - A given (event code, umask) combination need not measure the same
* hardware event in all processor models.
* - Event names in vendor documentation for an (event code, umask) pair
* may vary according to the CPU model.
* - Identically named events can map to different (event code, umask)
* pairs on different CPUs.
* - New (event code, umask) combinations continue to be added as CPUs
* evolve. The interface between hwpmc(4) and libpmc(3) needs to be
* robust with respect to ABI changes.
*
* The IAP_EVENT_* symbols below define the ABI between userland and kernel.
* New (event code, * umask) combinations used in new CPUs would be added
* to the end of the list. Vendor names for events are mapped to IAP_EVENT_*
* symbols using aliases. The final disambiguation of semantics based on
* the CPU model happens inside hwpmc(4).
*/
#define __PMC_EV_IAP() \
The Intel PMC architectural events have encodings which are identical to those of some non-architectural core events. This is not a problem in the general case as long as there's an 1:1 mapping between the two, but there are few exceptions. For example, 3CH_01H on Nehalem/Westmere represents both unhalted-reference-cycles and CPU_CLK_UNHALTED.REF_P. CPU_CLK_UNHALTED.REF_P on the aforementioned architectures does not measure reference (i.e. bus) but TSC, so there's the need to disambiguate. In order to avoid the namespace collision rename all the architectural events in a way they cannot be ambigous and refactor the architectural events handling function to reflect this change. While here, per Jim Harris request, rename iap_architectural_event_is_unsupported() to iap_event_is_architectural(). Discussed with: jimharris Reviewed by: jimharris, gnn
2013-04-30 15:31:45 +00:00
__PMC_EV(IAP, ARCH_BR_INS_RET) \
__PMC_EV(IAP, ARCH_BR_MIS_RET) \
__PMC_EV(IAP, ARCH_INS_RET) \
__PMC_EV(IAP, ARCH_LLC_MIS) \
__PMC_EV(IAP, ARCH_LLC_REF) \
__PMC_EV(IAP, ARCH_UNH_REF_CYC) \
__PMC_EV(IAP, ARCH_UNH_COR_CYC) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_02H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_02H_81H) \
__PMC_EV(IAP, EVENT_03H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_03H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_03H_02H) \
__PMC_EV(IAP, EVENT_03H_04H) \
__PMC_EV(IAP, EVENT_03H_08H) \
__PMC_EV(IAP, EVENT_03H_10H) \
__PMC_EV(IAP, EVENT_03H_20H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_03H_40H) \
__PMC_EV(IAP, EVENT_03H_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_04H_00H) \
__PMC_EV(IAP, EVENT_04H_01H) \
__PMC_EV(IAP, EVENT_04H_02H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_04H_04H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_04H_07H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_04H_08H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_04H_10H) \
__PMC_EV(IAP, EVENT_04H_20H) \
__PMC_EV(IAP, EVENT_04H_40H) \
__PMC_EV(IAP, EVENT_04H_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_05H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_05H_01H) \
__PMC_EV(IAP, EVENT_05H_02H) \
__PMC_EV(IAP, EVENT_05H_03H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_06H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_06H_01H) \
__PMC_EV(IAP, EVENT_06H_02H) \
__PMC_EV(IAP, EVENT_06H_04H) \
__PMC_EV(IAP, EVENT_06H_08H) \
__PMC_EV(IAP, EVENT_06H_0FH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_07H_00H) \
__PMC_EV(IAP, EVENT_07H_01H) \
__PMC_EV(IAP, EVENT_07H_02H) \
__PMC_EV(IAP, EVENT_07H_03H) \
__PMC_EV(IAP, EVENT_07H_06H) \
__PMC_EV(IAP, EVENT_07H_08H) \
__PMC_EV(IAP, EVENT_08H_01H) \
__PMC_EV(IAP, EVENT_08H_02H) \
__PMC_EV(IAP, EVENT_08H_04H) \
__PMC_EV(IAP, EVENT_08H_05H) \
__PMC_EV(IAP, EVENT_08H_06H) \
__PMC_EV(IAP, EVENT_08H_07H) \
__PMC_EV(IAP, EVENT_08H_08H) \
__PMC_EV(IAP, EVENT_08H_09H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_08H_0EH) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_08H_10H) \
__PMC_EV(IAP, EVENT_08H_20H) \
__PMC_EV(IAP, EVENT_08H_40H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_08H_60H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_08H_80H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV(IAP, EVENT_08H_81H) \
__PMC_EV(IAP, EVENT_08H_82H) \
__PMC_EV(IAP, EVENT_08H_84H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV(IAP, EVENT_08H_88H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_09H_01H) \
__PMC_EV(IAP, EVENT_09H_02H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_09H_04H) \
__PMC_EV(IAP, EVENT_09H_08H) \
__PMC_EV(IAP, EVENT_0BH_01H) \
__PMC_EV(IAP, EVENT_0BH_02H) \
__PMC_EV(IAP, EVENT_0BH_10H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_0CH_01H) \
__PMC_EV(IAP, EVENT_0CH_02H) \
__PMC_EV(IAP, EVENT_0CH_03H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_0DH_01H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_0DH_03H) \
__PMC_EV(IAP, EVENT_0DH_40H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_0DH_80H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_0EH_01H) \
__PMC_EV(IAP, EVENT_0EH_02H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV(IAP, EVENT_0EH_10H) \
__PMC_EV(IAP, EVENT_0EH_20H) \
__PMC_EV(IAP, EVENT_0EH_40H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_0FH_01H) \
__PMC_EV(IAP, EVENT_0FH_02H) \
__PMC_EV(IAP, EVENT_0FH_08H) \
__PMC_EV(IAP, EVENT_0FH_10H) \
__PMC_EV(IAP, EVENT_0FH_20H) \
__PMC_EV(IAP, EVENT_0FH_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_10H_00H) \
__PMC_EV(IAP, EVENT_10H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_10H_02H) \
__PMC_EV(IAP, EVENT_10H_04H) \
__PMC_EV(IAP, EVENT_10H_08H) \
__PMC_EV(IAP, EVENT_10H_10H) \
__PMC_EV(IAP, EVENT_10H_20H) \
__PMC_EV(IAP, EVENT_10H_40H) \
__PMC_EV(IAP, EVENT_10H_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_10H_81H) \
__PMC_EV(IAP, EVENT_11H_00H) \
__PMC_EV(IAP, EVENT_11H_01H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_11H_02H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_11H_81H) \
__PMC_EV(IAP, EVENT_12H_00H) \
__PMC_EV(IAP, EVENT_12H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_12H_02H) \
__PMC_EV(IAP, EVENT_12H_04H) \
__PMC_EV(IAP, EVENT_12H_08H) \
__PMC_EV(IAP, EVENT_12H_10H) \
__PMC_EV(IAP, EVENT_12H_20H) \
__PMC_EV(IAP, EVENT_12H_40H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_12H_81H) \
__PMC_EV(IAP, EVENT_13H_00H) \
__PMC_EV(IAP, EVENT_13H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_13H_02H) \
__PMC_EV(IAP, EVENT_13H_04H) \
__PMC_EV(IAP, EVENT_13H_07H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_13H_81H) \
__PMC_EV(IAP, EVENT_14H_00H) \
__PMC_EV(IAP, EVENT_14H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_14H_02H) \
__PMC_EV(IAP, EVENT_17H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_18H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_18H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_19H_00H) \
__PMC_EV(IAP, EVENT_19H_01H) \
__PMC_EV(IAP, EVENT_19H_02H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_1DH_01H) \
__PMC_EV(IAP, EVENT_1DH_02H) \
__PMC_EV(IAP, EVENT_1DH_04H) \
__PMC_EV(IAP, EVENT_1EH_01H) \
__PMC_EV(IAP, EVENT_20H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_21H) \
__PMC_EV(IAP, EVENT_22H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_22H_01H) \
__PMC_EV(IAP, EVENT_22H_02H) \
__PMC_EV(IAP, EVENT_22H_04H) \
__PMC_EV(IAP, EVENT_22H_08H) \
__PMC_EV(IAP, EVENT_22H_10H) \
__PMC_EV(IAP, EVENT_22H_20H) \
__PMC_EV(IAP, EVENT_22H_40H) \
__PMC_EV(IAP, EVENT_22H_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_23H) \
__PMC_EV(IAP, EVENT_24H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_24H_01H) \
__PMC_EV(IAP, EVENT_24H_02H) \
__PMC_EV(IAP, EVENT_24H_03H) \
__PMC_EV(IAP, EVENT_24H_04H) \
__PMC_EV(IAP, EVENT_24H_08H) \
__PMC_EV(IAP, EVENT_24H_0CH) \
__PMC_EV(IAP, EVENT_24H_10H) \
__PMC_EV(IAP, EVENT_24H_20H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_24H_21H) \
__PMC_EV(IAP, EVENT_24H_22H) \
__PMC_EV(IAP, EVENT_24H_24H) \
__PMC_EV(IAP, EVENT_24H_27H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_24H_30H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_24H_38H) \
__PMC_EV(IAP, EVENT_24H_3FH) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_24H_40H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_24H_41H) \
__PMC_EV(IAP, EVENT_24H_42H) \
__PMC_EV(IAP, EVENT_24H_44H) \
__PMC_EV(IAP, EVENT_24H_50H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_24H_80H) \
__PMC_EV(IAP, EVENT_24H_AAH) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_24H_BFH) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_24H_C0H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_24H_D8H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_24H_E1H) \
__PMC_EV(IAP, EVENT_24H_E2H) \
__PMC_EV(IAP, EVENT_24H_E4H) \
__PMC_EV(IAP, EVENT_24H_E7H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_24H_EFH) \
__PMC_EV(IAP, EVENT_24H_F7H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_24H_F8H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_24H_FFH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_25H) \
__PMC_EV(IAP, EVENT_26H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_26H_01H) \
__PMC_EV(IAP, EVENT_26H_02H) \
__PMC_EV(IAP, EVENT_26H_04H) \
__PMC_EV(IAP, EVENT_26H_08H) \
__PMC_EV(IAP, EVENT_26H_0FH) \
__PMC_EV(IAP, EVENT_26H_10H) \
__PMC_EV(IAP, EVENT_26H_20H) \
__PMC_EV(IAP, EVENT_26H_40H) \
__PMC_EV(IAP, EVENT_26H_80H) \
__PMC_EV(IAP, EVENT_26H_F0H) \
__PMC_EV(IAP, EVENT_26H_FFH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_27H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_27H_01H) \
__PMC_EV(IAP, EVENT_27H_02H) \
__PMC_EV(IAP, EVENT_27H_04H) \
__PMC_EV(IAP, EVENT_27H_08H) \
__PMC_EV(IAP, EVENT_27H_0EH) \
__PMC_EV(IAP, EVENT_27H_0FH) \
__PMC_EV(IAP, EVENT_27H_10H) \
__PMC_EV(IAP, EVENT_27H_20H) \
__PMC_EV(IAP, EVENT_27H_40H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_27H_50H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_27H_80H) \
__PMC_EV(IAP, EVENT_27H_E0H) \
__PMC_EV(IAP, EVENT_27H_F0H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_28H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_28H_01H) \
__PMC_EV(IAP, EVENT_28H_02H) \
__PMC_EV(IAP, EVENT_28H_04H) \
__PMC_EV(IAP, EVENT_28H_08H) \
__PMC_EV(IAP, EVENT_28H_0FH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_29H) \
__PMC_EV(IAP, EVENT_2AH) \
__PMC_EV(IAP, EVENT_2BH) \
__PMC_EV(IAP, EVENT_2EH) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_2EH_01H) \
__PMC_EV(IAP, EVENT_2EH_02H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_2EH_41H) \
__PMC_EV(IAP, EVENT_2EH_4FH) \
__PMC_EV(IAP, EVENT_30H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_30H_00H) \
__PMC_EV(IAP, EVENT_31H_00H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_32H) \
__PMC_EV(IAP, EVENT_3AH) \
__PMC_EV(IAP, EVENT_3AH_00H) \
__PMC_EV(IAP, EVENT_3BH_C0H) \
__PMC_EV(IAP, EVENT_3CH_00H) \
__PMC_EV(IAP, EVENT_3CH_01H) \
__PMC_EV(IAP, EVENT_3CH_02H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_3DH_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_40H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_40H_01H) \
__PMC_EV(IAP, EVENT_40H_02H) \
__PMC_EV(IAP, EVENT_40H_04H) \
__PMC_EV(IAP, EVENT_40H_08H) \
__PMC_EV(IAP, EVENT_40H_0FH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_40H_21H) \
__PMC_EV(IAP, EVENT_41H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_41H_01H) \
__PMC_EV(IAP, EVENT_41H_02H) \
__PMC_EV(IAP, EVENT_41H_04H) \
__PMC_EV(IAP, EVENT_41H_08H) \
__PMC_EV(IAP, EVENT_41H_0FH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_41H_22H) \
__PMC_EV(IAP, EVENT_42H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_42H_01H) \
__PMC_EV(IAP, EVENT_42H_02H) \
__PMC_EV(IAP, EVENT_42H_04H) \
__PMC_EV(IAP, EVENT_42H_08H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_42H_10H) \
__PMC_EV(IAP, EVENT_43H_01H) \
__PMC_EV(IAP, EVENT_43H_02H) \
__PMC_EV(IAP, EVENT_44H_02H) \
__PMC_EV(IAP, EVENT_45H_0FH) \
__PMC_EV(IAP, EVENT_46H_00H) \
__PMC_EV(IAP, EVENT_47H_00H) \
__PMC_EV(IAP, EVENT_48H_00H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_48H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_48H_02H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_49H_00H) \
__PMC_EV(IAP, EVENT_49H_01H) \
__PMC_EV(IAP, EVENT_49H_02H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_49H_04H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_49H_0EH) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_49H_10H) \
__PMC_EV(IAP, EVENT_49H_20H) \
__PMC_EV(IAP, EVENT_49H_40H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_49H_60H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_49H_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_4BH_00H) \
__PMC_EV(IAP, EVENT_4BH_01H) \
__PMC_EV(IAP, EVENT_4BH_02H) \
__PMC_EV(IAP, EVENT_4BH_03H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_4BH_08H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_4CH_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_4CH_01H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_4CH_02H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_4DH_01H) \
__PMC_EV(IAP, EVENT_4EH_01H) \
__PMC_EV(IAP, EVENT_4EH_02H) \
__PMC_EV(IAP, EVENT_4EH_04H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_4EH_10H) \
__PMC_EV(IAP, EVENT_4FH_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_4FH_02H) \
__PMC_EV(IAP, EVENT_4FH_04H) \
__PMC_EV(IAP, EVENT_4FH_08H) \
__PMC_EV(IAP, EVENT_4FH_10H) \
__PMC_EV(IAP, EVENT_51H_01H) \
__PMC_EV(IAP, EVENT_51H_02H) \
__PMC_EV(IAP, EVENT_51H_04H) \
__PMC_EV(IAP, EVENT_51H_08H) \
__PMC_EV(IAP, EVENT_52H_01H) \
__PMC_EV(IAP, EVENT_53H_01H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV(IAP, EVENT_58H_01H) \
__PMC_EV(IAP, EVENT_58H_02H) \
__PMC_EV(IAP, EVENT_58H_04H) \
__PMC_EV(IAP, EVENT_58H_08H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_59H_20H) \
__PMC_EV(IAP, EVENT_59H_40H) \
__PMC_EV(IAP, EVENT_59H_80H) \
__PMC_EV(IAP, EVENT_5BH_0CH) \
__PMC_EV(IAP, EVENT_5BH_0FH) \
__PMC_EV(IAP, EVENT_5BH_40H) \
__PMC_EV(IAP, EVENT_5BH_4FH) \
__PMC_EV(IAP, EVENT_5CH_01H) \
__PMC_EV(IAP, EVENT_5CH_02H) \
__PMC_EV(IAP, EVENT_5EH_01H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV(IAP, EVENT_5FH_01H) \
Update hwpmc to support the Xeon class of Ivybridge processors. case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-01-31 22:09:53 +00:00
__PMC_EV(IAP, EVENT_5FH_04H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_60H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_60H_01H) \
__PMC_EV(IAP, EVENT_60H_02H) \
__PMC_EV(IAP, EVENT_60H_04H) \
__PMC_EV(IAP, EVENT_60H_08H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_60H_10H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_61H) \
__PMC_EV(IAP, EVENT_61H_00H) \
__PMC_EV(IAP, EVENT_62H) \
__PMC_EV(IAP, EVENT_62H_00H) \
__PMC_EV(IAP, EVENT_63H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_63H_01H) \
__PMC_EV(IAP, EVENT_63H_02H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_64H) \
__PMC_EV(IAP, EVENT_64H_40H) \
__PMC_EV(IAP, EVENT_65H) \
__PMC_EV(IAP, EVENT_66H) \
__PMC_EV(IAP, EVENT_67H) \
__PMC_EV(IAP, EVENT_68H) \
__PMC_EV(IAP, EVENT_69H) \
__PMC_EV(IAP, EVENT_6AH) \
__PMC_EV(IAP, EVENT_6BH) \
__PMC_EV(IAP, EVENT_6CH) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_6CH_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_6DH) \
__PMC_EV(IAP, EVENT_6EH) \
__PMC_EV(IAP, EVENT_6FH) \
__PMC_EV(IAP, EVENT_70H) \
__PMC_EV(IAP, EVENT_77H) \
__PMC_EV(IAP, EVENT_78H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_79H_02H) \
__PMC_EV(IAP, EVENT_79H_04H) \
__PMC_EV(IAP, EVENT_79H_08H) \
__PMC_EV(IAP, EVENT_79H_10H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV(IAP, EVENT_79H_18H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_79H_20H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV(IAP, EVENT_79H_24H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_79H_30H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV(IAP, EVENT_79H_3CH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_7AH) \
__PMC_EV(IAP, EVENT_7BH) \
__PMC_EV(IAP, EVENT_7DH) \
__PMC_EV(IAP, EVENT_7EH) \
__PMC_EV(IAP, EVENT_7EH_00H) \
__PMC_EV(IAP, EVENT_7FH) \
__PMC_EV(IAP, EVENT_80H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_80H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_80H_02H) \
__PMC_EV(IAP, EVENT_80H_03H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_80H_04H) \
__PMC_EV(IAP, EVENT_80H_10H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_81H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_81H_01H) \
__PMC_EV(IAP, EVENT_81H_02H) \
__PMC_EV(IAP, EVENT_82H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_82H_02H) \
__PMC_EV(IAP, EVENT_82H_04H) \
__PMC_EV(IAP, EVENT_82H_10H) \
__PMC_EV(IAP, EVENT_82H_12H) \
__PMC_EV(IAP, EVENT_82H_40H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_83H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_83H_02H) \
__PMC_EV(IAP, EVENT_85H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_85H_01H) \
__PMC_EV(IAP, EVENT_85H_02H) \
__PMC_EV(IAP, EVENT_85H_04H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_85H_0EH) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_85H_10H) \
__PMC_EV(IAP, EVENT_85H_20H) \
__PMC_EV(IAP, EVENT_85H_40H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_85H_60H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_85H_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_86H_00H) \
__PMC_EV(IAP, EVENT_87H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_87H_01H) \
__PMC_EV(IAP, EVENT_87H_02H) \
__PMC_EV(IAP, EVENT_87H_04H) \
__PMC_EV(IAP, EVENT_87H_08H) \
__PMC_EV(IAP, EVENT_87H_0FH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_88H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_88H_01H) \
__PMC_EV(IAP, EVENT_88H_02H) \
__PMC_EV(IAP, EVENT_88H_04H) \
__PMC_EV(IAP, EVENT_88H_07H) \
__PMC_EV(IAP, EVENT_88H_08H) \
__PMC_EV(IAP, EVENT_88H_10H) \
__PMC_EV(IAP, EVENT_88H_20H) \
__PMC_EV(IAP, EVENT_88H_30H) \
__PMC_EV(IAP, EVENT_88H_40H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV(IAP, EVENT_88H_41H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_88H_80H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV(IAP, EVENT_88H_81H) \
__PMC_EV(IAP, EVENT_88H_82H) \
__PMC_EV(IAP, EVENT_88H_84H) \
__PMC_EV(IAP, EVENT_88H_88H) \
__PMC_EV(IAP, EVENT_88H_90H) \
__PMC_EV(IAP, EVENT_88H_A0H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_88H_7FH) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_88H_FFH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_89H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_89H_01H) \
__PMC_EV(IAP, EVENT_89H_02H) \
__PMC_EV(IAP, EVENT_89H_04H) \
__PMC_EV(IAP, EVENT_89H_07H) \
__PMC_EV(IAP, EVENT_89H_08H) \
__PMC_EV(IAP, EVENT_89H_10H) \
__PMC_EV(IAP, EVENT_89H_20H) \
__PMC_EV(IAP, EVENT_89H_30H) \
__PMC_EV(IAP, EVENT_89H_40H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV(IAP, EVENT_89H_41H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_89H_80H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV(IAP, EVENT_89H_81H) \
__PMC_EV(IAP, EVENT_89H_82H) \
__PMC_EV(IAP, EVENT_89H_84H) \
__PMC_EV(IAP, EVENT_89H_88H) \
__PMC_EV(IAP, EVENT_89H_90H) \
__PMC_EV(IAP, EVENT_89H_A0H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_89H_7FH) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_89H_FFH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_8AH_00H) \
__PMC_EV(IAP, EVENT_8BH_00H) \
__PMC_EV(IAP, EVENT_8CH_00H) \
__PMC_EV(IAP, EVENT_8DH_00H) \
__PMC_EV(IAP, EVENT_8EH_00H) \
__PMC_EV(IAP, EVENT_8FH_00H) \
__PMC_EV(IAP, EVENT_90H_00H) \
__PMC_EV(IAP, EVENT_91H_00H) \
__PMC_EV(IAP, EVENT_92H_00H) \
__PMC_EV(IAP, EVENT_93H_00H) \
__PMC_EV(IAP, EVENT_94H_00H) \
__PMC_EV(IAP, EVENT_97H_00H) \
__PMC_EV(IAP, EVENT_98H_00H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_9CH_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_A0H_00H) \
__PMC_EV(IAP, EVENT_A1H_01H) \
__PMC_EV(IAP, EVENT_A1H_02H) \
__PMC_EV(IAP, EVENT_A1H_04H) \
__PMC_EV(IAP, EVENT_A1H_08H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_A1H_0CH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_A1H_10H) \
__PMC_EV(IAP, EVENT_A1H_20H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_A1H_30H) \
__PMC_EV(IAP, EVENT_A1H_40H) \
__PMC_EV(IAP, EVENT_A1H_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_A2H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_A2H_01H) \
__PMC_EV(IAP, EVENT_A2H_02H) \
__PMC_EV(IAP, EVENT_A2H_04H) \
__PMC_EV(IAP, EVENT_A2H_08H) \
__PMC_EV(IAP, EVENT_A2H_10H) \
__PMC_EV(IAP, EVENT_A2H_20H) \
__PMC_EV(IAP, EVENT_A2H_40H) \
__PMC_EV(IAP, EVENT_A2H_80H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(IAP, EVENT_A3H_01H) \
__PMC_EV(IAP, EVENT_A3H_02H) \
__PMC_EV(IAP, EVENT_A3H_04H) \
__PMC_EV(IAP, EVENT_A3H_05H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_A3H_06H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(IAP, EVENT_A3H_08H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV(IAP, EVENT_A3H_0CH) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_A3H_10H) \
__PMC_EV(IAP, EVENT_A3H_14H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_A6H_01H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_A6H_02H) \
__PMC_EV(IAP, EVENT_A6H_04H) \
__PMC_EV(IAP, EVENT_A6H_08H) \
__PMC_EV(IAP, EVENT_A6H_10H) \
__PMC_EV(IAP, EVENT_A6H_40H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_A7H_01H) \
__PMC_EV(IAP, EVENT_A8H_01H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_A8H_02H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_AAH_01H) \
__PMC_EV(IAP, EVENT_AAH_02H) \
__PMC_EV(IAP, EVENT_AAH_03H) \
__PMC_EV(IAP, EVENT_AAH_08H) \
__PMC_EV(IAP, EVENT_ABH_01H) \
__PMC_EV(IAP, EVENT_ABH_02H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_ACH_02H) \
__PMC_EV(IAP, EVENT_ACH_08H) \
__PMC_EV(IAP, EVENT_ACH_0AH) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_AEH_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_B0H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_B0H_01H) \
__PMC_EV(IAP, EVENT_B0H_02H) \
__PMC_EV(IAP, EVENT_B0H_04H) \
__PMC_EV(IAP, EVENT_B0H_08H) \
__PMC_EV(IAP, EVENT_B0H_10H) \
__PMC_EV(IAP, EVENT_B0H_20H) \
__PMC_EV(IAP, EVENT_B0H_40H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_B0H_80H) \
__PMC_EV(IAP, EVENT_B1H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_B1H_01H) \
__PMC_EV(IAP, EVENT_B1H_02H) \
__PMC_EV(IAP, EVENT_B1H_04H) \
__PMC_EV(IAP, EVENT_B1H_08H) \
__PMC_EV(IAP, EVENT_B1H_10H) \
__PMC_EV(IAP, EVENT_B1H_1FH) \
__PMC_EV(IAP, EVENT_B1H_20H) \
__PMC_EV(IAP, EVENT_B1H_3FH) \
__PMC_EV(IAP, EVENT_B1H_40H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_B1H_80H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_B2H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_B3H_01H) \
__PMC_EV(IAP, EVENT_B3H_02H) \
__PMC_EV(IAP, EVENT_B3H_04H) \
__PMC_EV(IAP, EVENT_B3H_08H) \
__PMC_EV(IAP, EVENT_B3H_10H) \
__PMC_EV(IAP, EVENT_B3H_20H) \
__PMC_EV(IAP, EVENT_B3H_81H) \
__PMC_EV(IAP, EVENT_B3H_82H) \
__PMC_EV(IAP, EVENT_B3H_84H) \
__PMC_EV(IAP, EVENT_B3H_88H) \
__PMC_EV(IAP, EVENT_B3H_90H) \
__PMC_EV(IAP, EVENT_B3H_A0H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_B4H_01H) \
__PMC_EV(IAP, EVENT_B4H_02H) \
__PMC_EV(IAP, EVENT_B4H_04H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_B6H_01H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_B6H_04H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_B7H_01H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_B7H_02H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_B8H_01H) \
__PMC_EV(IAP, EVENT_B8H_02H) \
__PMC_EV(IAP, EVENT_B8H_04H) \
__PMC_EV(IAP, EVENT_BAH_01H) \
__PMC_EV(IAP, EVENT_BAH_02H) \
__PMC_EV(IAP, EVENT_BBH_01H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_BCH_11H) \
__PMC_EV(IAP, EVENT_BCH_12H) \
__PMC_EV(IAP, EVENT_BCH_14H) \
__PMC_EV(IAP, EVENT_BCH_18H) \
__PMC_EV(IAP, EVENT_BCH_21H) \
__PMC_EV(IAP, EVENT_BCH_22H) \
__PMC_EV(IAP, EVENT_BCH_24H) \
__PMC_EV(IAP, EVENT_BCH_28H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_BDH_01H) \
__PMC_EV(IAP, EVENT_BDH_20H) \
__PMC_EV(IAP, EVENT_BFH_05H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_C0H_00H) \
__PMC_EV(IAP, EVENT_C0H_01H) \
__PMC_EV(IAP, EVENT_C0H_02H) \
__PMC_EV(IAP, EVENT_C0H_04H) \
__PMC_EV(IAP, EVENT_C0H_08H) \
__PMC_EV(IAP, EVENT_C1H_00H) \
__PMC_EV(IAP, EVENT_C1H_01H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_C1H_02H) \
__PMC_EV(IAP, EVENT_C1H_08H) \
__PMC_EV(IAP, EVENT_C1H_10H) \
__PMC_EV(IAP, EVENT_C1H_20H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_C1H_3FH) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_C1H_40H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV(IAP, EVENT_C1H_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_C1H_FEH) \
__PMC_EV(IAP, EVENT_C2H_00H) \
__PMC_EV(IAP, EVENT_C2H_01H) \
__PMC_EV(IAP, EVENT_C2H_02H) \
__PMC_EV(IAP, EVENT_C2H_04H) \
__PMC_EV(IAP, EVENT_C2H_07H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_C2H_08H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_C2H_0FH) \
__PMC_EV(IAP, EVENT_C2H_10H) \
__PMC_EV(IAP, EVENT_C3H_00H) \
__PMC_EV(IAP, EVENT_C3H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_C3H_02H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_C3H_04H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_C3H_08H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_C3H_10H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_C3H_20H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_C4H_00H) \
__PMC_EV(IAP, EVENT_C4H_01H) \
__PMC_EV(IAP, EVENT_C4H_02H) \
__PMC_EV(IAP, EVENT_C4H_04H) \
__PMC_EV(IAP, EVENT_C4H_08H) \
__PMC_EV(IAP, EVENT_C4H_0CH) \
__PMC_EV(IAP, EVENT_C4H_0FH) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_C4H_10H) \
__PMC_EV(IAP, EVENT_C4H_20H) \
__PMC_EV(IAP, EVENT_C4H_40H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_C4H_7EH) \
__PMC_EV(IAP, EVENT_C4H_BFH) \
__PMC_EV(IAP, EVENT_C4H_EBH) \
__PMC_EV(IAP, EVENT_C4H_F7H) \
__PMC_EV(IAP, EVENT_C4H_F9H) \
__PMC_EV(IAP, EVENT_C4H_FBH) \
__PMC_EV(IAP, EVENT_C4H_FDH) \
__PMC_EV(IAP, EVENT_C4H_FEH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_C5H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_C5H_01H) \
__PMC_EV(IAP, EVENT_C5H_02H) \
__PMC_EV(IAP, EVENT_C5H_04H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_C5H_10H) \
__PMC_EV(IAP, EVENT_C5H_20H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_C5H_7EH) \
__PMC_EV(IAP, EVENT_C5H_BFH) \
__PMC_EV(IAP, EVENT_C5H_EBH) \
__PMC_EV(IAP, EVENT_C5H_F7H) \
__PMC_EV(IAP, EVENT_C5H_F9H) \
__PMC_EV(IAP, EVENT_C5H_FBH) \
__PMC_EV(IAP, EVENT_C5H_FDH) \
__PMC_EV(IAP, EVENT_C5H_FEH) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_C6H_00H) \
__PMC_EV(IAP, EVENT_C6H_01H) \
__PMC_EV(IAP, EVENT_C6H_02H) \
__PMC_EV(IAP, EVENT_C7H_00H) \
__PMC_EV(IAP, EVENT_C7H_01H) \
__PMC_EV(IAP, EVENT_C7H_02H) \
__PMC_EV(IAP, EVENT_C7H_04H) \
__PMC_EV(IAP, EVENT_C7H_08H) \
__PMC_EV(IAP, EVENT_C7H_10H) \
__PMC_EV(IAP, EVENT_C7H_1FH) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV(IAP, EVENT_C7H_20H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_C8H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_C8H_20H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_C9H_00H) \
__PMC_EV(IAP, EVENT_CAH_00H) \
__PMC_EV(IAP, EVENT_CAH_01H) \
__PMC_EV(IAP, EVENT_CAH_02H) \
__PMC_EV(IAP, EVENT_CAH_04H) \
__PMC_EV(IAP, EVENT_CAH_08H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_CAH_10H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_CAH_20H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_CAH_1EH) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_CAH_3FH) \
__PMC_EV(IAP, EVENT_CAH_50H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_CBH_01H) \
__PMC_EV(IAP, EVENT_CBH_02H) \
__PMC_EV(IAP, EVENT_CBH_04H) \
__PMC_EV(IAP, EVENT_CBH_08H) \
__PMC_EV(IAP, EVENT_CBH_10H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_CBH_1FH) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_CBH_40H) \
__PMC_EV(IAP, EVENT_CBH_80H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_CCH_00H) \
__PMC_EV(IAP, EVENT_CCH_01H) \
__PMC_EV(IAP, EVENT_CCH_02H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_CCH_03H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_CCH_20H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_CDH_00H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_CDH_01H) \
__PMC_EV(IAP, EVENT_CDH_02H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_CEH_00H) \
__PMC_EV(IAP, EVENT_CFH_00H) \
__PMC_EV(IAP, EVENT_D0H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_D0H_01H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_D0H_02H) \
__PMC_EV(IAP, EVENT_D0H_10H) \
Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandy bridge Xeon. Summary: These are PEBS events but they're also available as normal counter/sample events. The source table (Table 19-2) lists the base versions (LOAD, STLB_MISS, SPLIT, ALL) but it says they must be qualified with other values. This particular commit fleshes out those umask values. Source: * Linux; SDM June 2013, Volume 3B, Table 19-2 and 18-21. Tested: * Sandy Bridge (non-Xeon)
2013-08-25 02:07:28 +00:00
__PMC_EV(IAP, EVENT_D0H_11H) \
__PMC_EV(IAP, EVENT_D0H_12H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_D0H_20H) \
Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandy bridge Xeon. Summary: These are PEBS events but they're also available as normal counter/sample events. The source table (Table 19-2) lists the base versions (LOAD, STLB_MISS, SPLIT, ALL) but it says they must be qualified with other values. This particular commit fleshes out those umask values. Source: * Linux; SDM June 2013, Volume 3B, Table 19-2 and 18-21. Tested: * Sandy Bridge (non-Xeon)
2013-08-25 02:07:28 +00:00
__PMC_EV(IAP, EVENT_D0H_21H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_D0H_40H) \
Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandy bridge Xeon. Summary: These are PEBS events but they're also available as normal counter/sample events. The source table (Table 19-2) lists the base versions (LOAD, STLB_MISS, SPLIT, ALL) but it says they must be qualified with other values. This particular commit fleshes out those umask values. Source: * Linux; SDM June 2013, Volume 3B, Table 19-2 and 18-21. Tested: * Sandy Bridge (non-Xeon)
2013-08-25 02:07:28 +00:00
__PMC_EV(IAP, EVENT_D0H_41H) \
__PMC_EV(IAP, EVENT_D0H_42H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_D0H_80H) \
Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandy bridge Xeon. Summary: These are PEBS events but they're also available as normal counter/sample events. The source table (Table 19-2) lists the base versions (LOAD, STLB_MISS, SPLIT, ALL) but it says they must be qualified with other values. This particular commit fleshes out those umask values. Source: * Linux; SDM June 2013, Volume 3B, Table 19-2 and 18-21. Tested: * Sandy Bridge (non-Xeon)
2013-08-25 02:07:28 +00:00
__PMC_EV(IAP, EVENT_D0H_81H) \
__PMC_EV(IAP, EVENT_D0H_82H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_D1H_01H) \
__PMC_EV(IAP, EVENT_D1H_02H) \
__PMC_EV(IAP, EVENT_D1H_04H) \
__PMC_EV(IAP, EVENT_D1H_08H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_D1H_10H) \
Update hwpmc to support the Xeon class of Sandybridge processors. (Model 0x2D /* Per Intel document 253669-044US 08/2012. */) Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ fabient@ Obtained from: Yahoo! Inc. MFC after: 2 weeks
2012-10-19 17:01:27 +00:00
__PMC_EV(IAP, EVENT_D1H_20H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_D1H_40H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_D2H_01H) \
__PMC_EV(IAP, EVENT_D2H_02H) \
__PMC_EV(IAP, EVENT_D2H_04H) \
__PMC_EV(IAP, EVENT_D2H_08H) \
__PMC_EV(IAP, EVENT_D2H_0FH) \
__PMC_EV(IAP, EVENT_D2H_10H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV(IAP, EVENT_D3H_01H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV(IAP, EVENT_D3H_03H) \
Update hwpmc to support the Xeon class of Sandybridge processors. (Model 0x2D /* Per Intel document 253669-044US 08/2012. */) Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ fabient@ Obtained from: Yahoo! Inc. MFC after: 2 weeks
2012-10-19 17:01:27 +00:00
__PMC_EV(IAP, EVENT_D3H_04H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV(IAP, EVENT_D3H_0CH) \
Update hwpmc to support the Xeon class of Ivybridge processors. case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-01-31 22:09:53 +00:00
__PMC_EV(IAP, EVENT_D3H_10H) \
__PMC_EV(IAP, EVENT_D3H_20H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_D4H_01H) \
__PMC_EV(IAP, EVENT_D4H_02H) \
__PMC_EV(IAP, EVENT_D4H_04H) \
__PMC_EV(IAP, EVENT_D4H_08H) \
__PMC_EV(IAP, EVENT_D4H_0FH) \
__PMC_EV(IAP, EVENT_D5H_01H) \
__PMC_EV(IAP, EVENT_D5H_02H) \
__PMC_EV(IAP, EVENT_D5H_04H) \
__PMC_EV(IAP, EVENT_D5H_08H) \
__PMC_EV(IAP, EVENT_D5H_0FH) \
__PMC_EV(IAP, EVENT_D7H_00H) \
__PMC_EV(IAP, EVENT_D8H_00H) \
__PMC_EV(IAP, EVENT_D8H_01H) \
__PMC_EV(IAP, EVENT_D8H_02H) \
__PMC_EV(IAP, EVENT_D8H_03H) \
__PMC_EV(IAP, EVENT_D8H_04H) \
__PMC_EV(IAP, EVENT_D9H_00H) \
__PMC_EV(IAP, EVENT_D9H_01H) \
__PMC_EV(IAP, EVENT_D9H_02H) \
__PMC_EV(IAP, EVENT_D9H_03H) \
__PMC_EV(IAP, EVENT_DAH_00H) \
__PMC_EV(IAP, EVENT_DAH_01H) \
__PMC_EV(IAP, EVENT_DAH_02H) \
__PMC_EV(IAP, EVENT_DBH_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_DBH_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV(IAP, EVENT_DCH_01H) \
__PMC_EV(IAP, EVENT_DCH_02H) \
__PMC_EV(IAP, EVENT_DCH_04H) \
__PMC_EV(IAP, EVENT_DCH_08H) \
__PMC_EV(IAP, EVENT_DCH_10H) \
__PMC_EV(IAP, EVENT_DCH_1FH) \
__PMC_EV(IAP, EVENT_E0H_00H) \
__PMC_EV(IAP, EVENT_E0H_01H) \
__PMC_EV(IAP, EVENT_E2H_00H) \
__PMC_EV(IAP, EVENT_E4H_00H) \
- Add support for nehalem/corei7 cpus. This supports all of the core counters defined in the reference manual. It does not support the 'uncore' events. Reviewed by: jkoshy Sponsored by: Nokia
2009-01-27 07:29:37 +00:00
__PMC_EV(IAP, EVENT_E4H_01H) \
__PMC_EV(IAP, EVENT_E5H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_E6H_00H) \
__PMC_EV(IAP, EVENT_E6H_01H) \
Add counters for the i7 architecture which were accidentally left out of the original commit of i7 support. These are all the counters on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B_, June 2009. Almost all of these counters relate to operations on the L2 cache. Reviewed by: jkoshy MFC after: 1 month
2009-09-01 17:55:37 +00:00
__PMC_EV(IAP, EVENT_E6H_02H) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_E6H_08H) \
__PMC_EV(IAP, EVENT_E6H_10H) \
Update hwpmc to support the Xeon class of Ivybridge processors. case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-01-31 22:09:53 +00:00
__PMC_EV(IAP, EVENT_E6H_1FH) \
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
__PMC_EV(IAP, EVENT_E7H_01H) \
Add counters for the i7 architecture which were accidentally left out of the original commit of i7 support. These are all the counters on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B_, June 2009. Almost all of these counters relate to operations on the L2 cache. Reviewed by: jkoshy MFC after: 1 month
2009-09-01 17:55:37 +00:00
__PMC_EV(IAP, EVENT_E8H_01H) \
__PMC_EV(IAP, EVENT_E8H_02H) \
__PMC_EV(IAP, EVENT_E8H_03H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_ECH_01H) \
__PMC_EV(IAP, EVENT_F0H_00H) \
Add counters for the i7 architecture which were accidentally left out of the original commit of i7 support. These are all the counters on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B_, June 2009. Almost all of these counters relate to operations on the L2 cache. Reviewed by: jkoshy MFC after: 1 month
2009-09-01 17:55:37 +00:00
__PMC_EV(IAP, EVENT_F0H_01H) \
__PMC_EV(IAP, EVENT_F0H_02H) \
__PMC_EV(IAP, EVENT_F0H_04H) \
__PMC_EV(IAP, EVENT_F0H_08H) \
__PMC_EV(IAP, EVENT_F0H_10H) \
__PMC_EV(IAP, EVENT_F0H_20H) \
__PMC_EV(IAP, EVENT_F0H_40H) \
__PMC_EV(IAP, EVENT_F0H_80H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_F1H_01H) \
Add counters for the i7 architecture which were accidentally left out of the original commit of i7 support. These are all the counters on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B_, June 2009. Almost all of these counters relate to operations on the L2 cache. Reviewed by: jkoshy MFC after: 1 month
2009-09-01 17:55:37 +00:00
__PMC_EV(IAP, EVENT_F1H_02H) \
__PMC_EV(IAP, EVENT_F1H_04H) \
__PMC_EV(IAP, EVENT_F1H_07H) \
__PMC_EV(IAP, EVENT_F2H_01H) \
__PMC_EV(IAP, EVENT_F2H_02H) \
__PMC_EV(IAP, EVENT_F2H_04H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(IAP, EVENT_F2H_05H) \
__PMC_EV(IAP, EVENT_F2H_06H) \
Add counters for the i7 architecture which were accidentally left out of the original commit of i7 support. These are all the counters on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B_, June 2009. Almost all of these counters relate to operations on the L2 cache. Reviewed by: jkoshy MFC after: 1 month
2009-09-01 17:55:37 +00:00
__PMC_EV(IAP, EVENT_F2H_08H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(IAP, EVENT_F2H_0AH) \
Add counters for the i7 architecture which were accidentally left out of the original commit of i7 support. These are all the counters on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures Software Developer's Manual Vol 3B_, June 2009. Almost all of these counters relate to operations on the L2 cache. Reviewed by: jkoshy MFC after: 1 month
2009-09-01 17:55:37 +00:00
__PMC_EV(IAP, EVENT_F2H_0FH) \
__PMC_EV(IAP, EVENT_F3H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(IAP, EVENT_F3H_02H) \
__PMC_EV(IAP, EVENT_F3H_04H) \
__PMC_EV(IAP, EVENT_F3H_08H) \
__PMC_EV(IAP, EVENT_F3H_10H) \
__PMC_EV(IAP, EVENT_F3H_20H) \
__PMC_EV(IAP, EVENT_F4H_01H) \
__PMC_EV(IAP, EVENT_F4H_02H) \
__PMC_EV(IAP, EVENT_F4H_04H) \
__PMC_EV(IAP, EVENT_F4H_08H) \
__PMC_EV(IAP, EVENT_F4H_10H) \
__PMC_EV(IAP, EVENT_F6H_01H) \
__PMC_EV(IAP, EVENT_F7H_01H) \
__PMC_EV(IAP, EVENT_F7H_02H) \
__PMC_EV(IAP, EVENT_F7H_04H) \
__PMC_EV(IAP, EVENT_F8H_00H) \
__PMC_EV(IAP, EVENT_F8H_01H) \
__PMC_EV(IAP, EVENT_FDH_01H) \
__PMC_EV(IAP, EVENT_FDH_02H) \
__PMC_EV(IAP, EVENT_FDH_04H) \
__PMC_EV(IAP, EVENT_FDH_08H) \
__PMC_EV(IAP, EVENT_FDH_10H) \
__PMC_EV(IAP, EVENT_FDH_20H) \
__PMC_EV(IAP, EVENT_FDH_40H)
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
The Intel PMC architectural events have encodings which are identical to those of some non-architectural core events. This is not a problem in the general case as long as there's an 1:1 mapping between the two, but there are few exceptions. For example, 3CH_01H on Nehalem/Westmere represents both unhalted-reference-cycles and CPU_CLK_UNHALTED.REF_P. CPU_CLK_UNHALTED.REF_P on the aforementioned architectures does not measure reference (i.e. bus) but TSC, so there's the need to disambiguate. In order to avoid the namespace collision rename all the architectural events in a way they cannot be ambigous and refactor the architectural events handling function to reflect this change. While here, per Jim Harris request, rename iap_architectural_event_is_unsupported() to iap_event_is_architectural(). Discussed with: jimharris Reviewed by: jimharris, gnn
2013-04-30 15:31:45 +00:00
#define PMC_EV_IAP_FIRST PMC_EV_IAP_ARCH_BR_INS_RET
- Add support for nehalem/corei7 cpus. This supports all of the core counters defined in the reference manual. It does not support the 'uncore' events. Reviewed by: jkoshy Sponsored by: Nokia
2009-01-27 07:29:37 +00:00
#define PMC_EV_IAP_LAST PMC_EV_IAP_EVENT_FDH_40H
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
/*
* Map "architectural" event names to event ids.
*/
#define __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
The Intel PMC architectural events have encodings which are identical to those of some non-architectural core events. This is not a problem in the general case as long as there's an 1:1 mapping between the two, but there are few exceptions. For example, 3CH_01H on Nehalem/Westmere represents both unhalted-reference-cycles and CPU_CLK_UNHALTED.REF_P. CPU_CLK_UNHALTED.REF_P on the aforementioned architectures does not measure reference (i.e. bus) but TSC, so there's the need to disambiguate. In order to avoid the namespace collision rename all the architectural events in a way they cannot be ambigous and refactor the architectural events handling function to reflect this change. While here, per Jim Harris request, rename iap_architectural_event_is_unsupported() to iap_event_is_architectural(). Discussed with: jimharris Reviewed by: jimharris, gnn
2013-04-30 15:31:45 +00:00
__PMC_EV_ALIAS("branch-instruction-retired", IAP_ARCH_BR_INS_RET) \
__PMC_EV_ALIAS("branch-misses-retired", IAP_ARCH_BR_MIS_RET) \
__PMC_EV_ALIAS("instruction-retired", IAP_ARCH_INS_RET) \
__PMC_EV_ALIAS("llc-misses", IAP_ARCH_LLC_MIS) \
__PMC_EV_ALIAS("llc-reference", IAP_ARCH_LLC_REF) \
__PMC_EV_ALIAS("unhalted-reference-cycles", IAP_ARCH_UNH_REF_CYC) \
__PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC)
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
/*
* Aliases for Atom PMCs.
*/
#define __PMC_EV_ALIAS_ATOM() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("BACLEARS", IAP_EVENT_E6H_01H) \
__PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_00H) \
__PMC_EV_ALIAS("BR_BAC_MISSP_EXEC", IAP_EVENT_8AH_00H) \
__PMC_EV_ALIAS("BR_CALL_EXEC", IAP_EVENT_92H_00H) \
__PMC_EV_ALIAS("BR_CALL_MISSP_EXEC", IAP_EVENT_93H_00H) \
__PMC_EV_ALIAS("BR_CND_EXEC", IAP_EVENT_8BH_00H) \
__PMC_EV_ALIAS("BR_CND_MISSP_EXEC", IAP_EVENT_8CH_00H) \
__PMC_EV_ALIAS("BR_IND_CALL_EXEC", IAP_EVENT_94H_00H) \
__PMC_EV_ALIAS("BR_IND_EXEC", IAP_EVENT_8DH_00H) \
__PMC_EV_ALIAS("BR_IND_MISSP_EXEC", IAP_EVENT_8EH_00H) \
__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \
__PMC_EV_ALIAS("BR_INST_EXEC", IAP_EVENT_88H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ANY", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ANY1", IAP_EVENT_C4H_0FH) \
__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN", \
IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN", IAP_EVENT_C4H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN", IAP_EVENT_C4H_01H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN", IAP_EVENT_C4H_0CH) \
__PMC_EV_ALIAS("BR_MISSP_EXEC", IAP_EVENT_89H_00H) \
__PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC", IAP_EVENT_91H_00H) \
__PMC_EV_ALIAS("BR_RET_EXEC", IAP_EVENT_8FH_00H) \
__PMC_EV_ALIAS("BR_RET_MISSP_EXEC", IAP_EVENT_90H_00H) \
__PMC_EV_ALIAS("BR_TKN_BUBBLE_1", IAP_EVENT_97H_00H) \
__PMC_EV_ALIAS("BR_TKN_BUBBLE_2", IAP_EVENT_98H_00H) \
__PMC_EV_ALIAS("BUSQ_EMPTY", IAP_EVENT_7DH) \
__PMC_EV_ALIAS("BUS_BNR_DRV", IAP_EVENT_61H) \
__PMC_EV_ALIAS("BUS_DATA_RCV", IAP_EVENT_64H) \
__PMC_EV_ALIAS("BUS_DRDY_CLOCKS", IAP_EVENT_62H) \
__PMC_EV_ALIAS("BUS_HITM_DRV", IAP_EVENT_7BH) \
__PMC_EV_ALIAS("BUS_HIT_DRV", IAP_EVENT_7AH) \
__PMC_EV_ALIAS("BUS_IO_WAIT", IAP_EVENT_7FH) \
__PMC_EV_ALIAS("BUS_LOCK_CLOCKS", IAP_EVENT_63H) \
__PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING", IAP_EVENT_60H) \
__PMC_EV_ALIAS("BUS_TRANS_ANY", IAP_EVENT_70H) \
__PMC_EV_ALIAS("BUS_TRANS_BRD", IAP_EVENT_65H) \
__PMC_EV_ALIAS("BUS_TRANS_BURST", IAP_EVENT_6EH) \
__PMC_EV_ALIAS("BUS_TRANS_DEF", IAP_EVENT_6DH) \
__PMC_EV_ALIAS("BUS_TRANS_IFETCH", IAP_EVENT_68H) \
__PMC_EV_ALIAS("BUS_TRANS_INVAL", IAP_EVENT_69H) \
__PMC_EV_ALIAS("BUS_TRANS_IO", IAP_EVENT_6CH) \
__PMC_EV_ALIAS("BUS_TRANS_MEM", IAP_EVENT_6FH) \
__PMC_EV_ALIAS("BUS_TRANS_P", IAP_EVENT_6BH) \
__PMC_EV_ALIAS("BUS_TRANS_PWR", IAP_EVENT_6AH) \
__PMC_EV_ALIAS("BUS_TRANS_RFO", IAP_EVENT_66H) \
__PMC_EV_ALIAS("BUS_TRANS_WB", IAP_EVENT_67H) \
__PMC_EV_ALIAS("CMP_SNOOP", IAP_EVENT_78H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER", IAP_EVENT_3CH_02H) \
__PMC_EV_ALIAS("CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \
__PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_MASKED", \
IAP_EVENT_C6H_01H) \
__PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", \
IAP_EVENT_C6H_02H) \
__PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED", IAP_EVENT_86H_00H) \
__PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS", IAP_EVENT_08H_07H) \
__PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_LD", IAP_EVENT_08H_05H) \
__PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_ST", IAP_EVENT_08H_06H) \
__PMC_EV_ALIAS("DATA_TLB_MISSES.UTLB_MISS_LD", IAP_EVENT_08H_09H) \
__PMC_EV_ALIAS("DELAYED_BYPASS.FP", IAP_EVENT_19H_00H) \
__PMC_EV_ALIAS("DELAYED_BYPASS.LOAD", IAP_EVENT_19H_01H) \
__PMC_EV_ALIAS("DELAYED_BYPASS.SIMD", IAP_EVENT_19H_02H) \
__PMC_EV_ALIAS("DIV", IAP_EVENT_13H_00H) \
__PMC_EV_ALIAS("DIV.AR", IAP_EVENT_13H_81H) \
__PMC_EV_ALIAS("DIV.S", IAP_EVENT_13H_01H) \
__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_08H_01H) \
__PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD", IAP_EVENT_08H_04H) \
__PMC_EV_ALIAS("DTLB_MISSES.MISS_LD", IAP_EVENT_08H_02H) \
__PMC_EV_ALIAS("DTLB_MISSES.MISS_ST", IAP_EVENT_08H_08H) \
__PMC_EV_ALIAS("EIST_TRANS", IAP_EVENT_3AH_00H) \
__PMC_EV_ALIAS("ESP.ADDITIONS", IAP_EVENT_ABH_02H) \
__PMC_EV_ALIAS("ESP.SYNCH", IAP_EVENT_ABH_01H) \
__PMC_EV_ALIAS("EXT_SNOOP", IAP_EVENT_77H) \
__PMC_EV_ALIAS("FP_ASSIST", IAP_EVENT_11H_01H) \
__PMC_EV_ALIAS("FP_ASSIST.AR", IAP_EVENT_11H_81H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE", IAP_EVENT_10H_00H) \
__PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP", IAP_EVENT_CCH_02H) \
__PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX", IAP_EVENT_CCH_01H) \
__PMC_EV_ALIAS("HW_INT_RCV", IAP_EVENT_C8H_00H) \
__PMC_EV_ALIAS("ICACHE.ACCESSES", IAP_EVENT_80H_03H) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
__PMC_EV_ALIAS("IDLE_DURING_DIV", IAP_EVENT_18H_00H) \
__PMC_EV_ALIAS("ILD_STALL", IAP_EVENT_87H_00H) \
__PMC_EV_ALIAS("INST_QUEUE.FULL", IAP_EVENT_83H_02H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("INST_RETIRED.LOADS", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("INST_RETIRED.OTHER", IAP_EVENT_C0H_04H) \
__PMC_EV_ALIAS("INST_RETIRED.STORES", IAP_EVENT_C0H_02H) \
__PMC_EV_ALIAS("ITLB.FLUSH", IAP_EVENT_82H_04H) \
__PMC_EV_ALIAS("ITLB.LARGE_MISS", IAP_EVENT_82H_10H) \
__PMC_EV_ALIAS("ITLB.MISSES", IAP_EVENT_82H_02H) \
__PMC_EV_ALIAS("ITLB.SMALL_MISS", IAP_EVENT_82H_02H) \
__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C9H_00H) \
__PMC_EV_ALIAS("L1D_ALL_CACHE_REF", IAP_EVENT_43H_02H) \
__PMC_EV_ALIAS("L1D_ALL_REF", IAP_EVENT_43H_01H) \
__PMC_EV_ALIAS("L1D_CACHE.LD", IAP_EVENT_40H_21H) \
__PMC_EV_ALIAS("L1D_CACHE.ST", IAP_EVENT_41H_22H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK", IAP_EVENT_42H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION", IAP_EVENT_42H_10H) \
__PMC_EV_ALIAS("L1D_M_EVICT", IAP_EVENT_47H_00H) \
__PMC_EV_ALIAS("L1D_M_REPL", IAP_EVENT_46H_00H) \
__PMC_EV_ALIAS("L1D_PEND_MISS", IAP_EVENT_48H_00H) \
__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_10H) \
__PMC_EV_ALIAS("L1D_REPL", IAP_EVENT_45H_0FH) \
__PMC_EV_ALIAS("L1D_SPLIT.LOADS", IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("L1D_SPLIT.STORES", IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("L1I_MISSES", IAP_EVENT_81H_00H) \
__PMC_EV_ALIAS("L1I_READS", IAP_EVENT_80H_00H) \
__PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \
__PMC_EV_ALIAS("L2_DBUS_BUSY_RD", IAP_EVENT_23H) \
__PMC_EV_ALIAS("L2_IFETCH", IAP_EVENT_28H) \
__PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \
__PMC_EV_ALIAS("L2_LINES_IN", IAP_EVENT_24H) \
__PMC_EV_ALIAS("L2_LINES_OUT", IAP_EVENT_26H) \
__PMC_EV_ALIAS("L2_LOCK", IAP_EVENT_2BH) \
__PMC_EV_ALIAS("L2_M_LINES_IN", IAP_EVENT_25H) \
__PMC_EV_ALIAS("L2_M_LINES_OUT", IAP_EVENT_27H) \
__PMC_EV_ALIAS("L2_NO_REQ", IAP_EVENT_32H) \
__PMC_EV_ALIAS("L2_REJECT_BUSQ", IAP_EVENT_30H) \
__PMC_EV_ALIAS("L2_RQSTS", IAP_EVENT_2EH) \
__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \
__PMC_EV_ALIAS("LOAD_BLOCK.L1D", IAP_EVENT_03H_20H) \
__PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", IAP_EVENT_03H_08H) \
__PMC_EV_ALIAS("LOAD_BLOCK.STA", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_04H) \
__PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE", IAP_EVENT_03H_10H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_00H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_01H) \
__PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACRO_INSTS.ALL_DECODED", IAP_EVENT_AAH_03H) \
__PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED", IAP_EVENT_AAH_02H) \
__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET", IAP_EVENT_09H_01H) \
__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS", IAP_EVENT_09H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_04H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_01H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS", IAP_EVENT_CBH_08H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS", IAP_EVENT_CBH_02H) \
__PMC_EV_ALIAS("MUL", IAP_EVENT_12H_00H) \
__PMC_EV_ALIAS("MUL.AR", IAP_EVENT_12H_81H) \
__PMC_EV_ALIAS("MUL.S", IAP_EVENT_12H_01H) \
__PMC_EV_ALIAS("PAGE_WALKS.CYCLES", IAP_EVENT_0CH_03H) \
__PMC_EV_ALIAS("PAGE_WALKS.WALKS", IAP_EVENT_0CH_03H) \
__PMC_EV_ALIAS("PREFETCH.PREFETCHNTA", IAP_EVENT_07H_08H) \
__PMC_EV_ALIAS("PREFETCH.PREFETCHT0", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("PREFETCH.SW_L2", IAP_EVENT_07H_06H) \
__PMC_EV_ALIAS("PREF_RQSTS_DN", IAP_EVENT_F8H_00H) \
__PMC_EV_ALIAS("PREF_RQSTS_UP", IAP_EVENT_F0H_00H) \
__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \
__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("RAT_STALLS.FPSW", IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES", IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_DCH_1FH) \
__PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR", IAP_EVENT_DCH_10H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_DCH_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST", IAP_EVENT_DCH_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_DCH_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_DCH_02H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED", IAP_EVENT_A0H_00H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("SB_DRAIN_CYCLES", IAP_EVENT_04H_01H) \
__PMC_EV_ALIAS("SEGMENT_REG_LOADS.ANY", IAP_EVENT_06H_00H) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.ANY", IAP_EVENT_D5H_0FH) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.DS", IAP_EVENT_D5H_02H) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.ES", IAP_EVENT_D5H_01H) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.FS", IAP_EVENT_D5H_04H) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.GS", IAP_EVENT_D5H_08H) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY", IAP_EVENT_D4H_0FH) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.DS", IAP_EVENT_D4H_02H) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.ES", IAP_EVENT_D4H_01H) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.FS", IAP_EVENT_D4H_04H) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.GS", IAP_EVENT_D4H_08H) \
__PMC_EV_ALIAS("SIMD_ASSIST", IAP_EVENT_CDH_00H) \
__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", \
IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE", \
IAP_EVENT_CAH_01H) \
__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", \
IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", \
IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("SIMD_INSTR_RETIRED", IAP_EVENT_CEH_00H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY", IAP_EVENT_C7H_1FH) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR", IAP_EVENT_C7H_10H) \
__PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED", IAP_EVENT_CFH_00H) \
__PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.AR", IAP_EVENT_B1H_80H) \
__PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.S", IAP_EVENT_B1H_00H) \
__PMC_EV_ALIAS("SIMD_UOPS_EXEC.AR", IAP_EVENT_B0H_80H) \
__PMC_EV_ALIAS("SIMD_UOPS_EXEC.S", IAP_EVENT_B0H_00H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", IAP_EVENT_B3H_A0H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", IAP_EVENT_B3H_20H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.AR", IAP_EVENT_B3H_90H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.S", IAP_EVENT_B3H_10H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.AR", IAP_EVENT_B3H_81H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.S", IAP_EVENT_B3H_01H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.AR", IAP_EVENT_B3H_84H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.S", IAP_EVENT_B3H_04H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.AR", IAP_EVENT_B3H_82H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.S", IAP_EVENT_B3H_02H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.AR", IAP_EVENT_B3H_88H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.S", IAP_EVENT_B3H_08H) \
__PMC_EV_ALIAS("SNOOP_STALL_DRV", IAP_EVENT_7EH) \
__PMC_EV_ALIAS("SSE_PRE_EXEC.L2", IAP_EVENT_07H_02H) \
__PMC_EV_ALIAS("SSE_PRE_EXEC.STORES", IAP_EVENT_07H_03H) \
__PMC_EV_ALIAS("SSE_PRE_MISS.L1", IAP_EVENT_4BH_01H) \
__PMC_EV_ALIAS("SSE_PRE_MISS.L2", IAP_EVENT_4BH_02H) \
__PMC_EV_ALIAS("SSE_PRE_MISS.NTA", IAP_EVENT_4BH_00H) \
__PMC_EV_ALIAS("STORE_BLOCK.ORDER", IAP_EVENT_04H_02H) \
__PMC_EV_ALIAS("STORE_BLOCK.SNOOP", IAP_EVENT_04H_08H) \
__PMC_EV_ALIAS("STORE_FORWARDS.GOOD", IAP_EVENT_02H_81H) \
__PMC_EV_ALIAS("THERMAL_TRIP", IAP_EVENT_3BH_C0H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_10H) \
__PMC_EV_ALIAS("UOPS_RETIRED.FUSED", IAP_EVENT_C2H_07H) \
__PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION", IAP_EVENT_C2H_04H) \
__PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED", IAP_EVENT_C2H_08H) \
__PMC_EV_ALIAS("UOPS_RETIRED.STD_STA", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.AR", IAP_EVENT_10H_81H) \
__PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.S", IAP_EVENT_10H_01H) \
__PMC_EV_ALIAS("X87_OPS_RETIRED.ANY", IAP_EVENT_C1H_FEH) \
__PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH", IAP_EVENT_C1H_01H)
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
/*
* Aliases for Atom Silvermont PMCs.
*/
#define __PMC_EV_ALIAS_ATOM_SILVERMONT() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("REHABQ.LD_BLOCK_ST_FORWARD", IAP_EVENT_03H_01H) \
__PMC_EV_ALIAS("REHABQ.LD_BLOCK_STD_NOTREADY", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("REHABQ.ST_SPLITS", IAP_EVENT_03H_04H) \
__PMC_EV_ALIAS("REHABQ.LD_SPLITS", IAP_EVENT_03H_08H) \
__PMC_EV_ALIAS("REHABQ.LOCK", IAP_EVENT_03H_10H) \
__PMC_EV_ALIAS("REHABQ.STA_FULL", IAP_EVENT_03H_20H) \
__PMC_EV_ALIAS("REHABQ.ANY_LD", IAP_EVENT_03H_40H) \
__PMC_EV_ALIAS("REHABQ.ANY_ST", IAP_EVENT_03H_80H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.L1_MISS_LOADS", IAP_EVENT_04H_01H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.L2_HIT_LOADS", IAP_EVENT_04H_02H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.L2_MISS_LOADS", IAP_EVENT_04H_04H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.DTLB_MISS_LOADS", IAP_EVENT_04H_08H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.UTLB_MISS", IAP_EVENT_04H_10H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.HITM", IAP_EVENT_04H_20H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_04H_40H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_04H_80H) \
__PMC_EV_ALIAS("PAGE_WALKS.D_SIDE_CYCLES", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("PAGE_WALKS.I_SIDE_CYCLES", IAP_EVENT_05H_02H) \
__PMC_EV_ALIAS("PAGE_WALKS.WALKS", IAP_EVENT_05H_03H) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("L2_REJECT_XQ.ALL", IAP_EVENT_30H_00H) \
__PMC_EV_ALIAS("CORE_REJECT_L2Q.ALL", IAP_EVENT_31H_00H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("ICACHE.HIT", IAP_EVENT_80H_01H) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
__PMC_EV_ALIAS("ICACHE.ACCESSES", IAP_EVENT_80H_03H) \
__PMC_EV_ALIAS("NIP_STALL.ICACHE_MISS", IAP_EVENT_B6H_04H) \
__PMC_EV_ALIAS("OFFCORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFFCORE_RESPONSE_1", IAP_EVENT_B7H_02H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("UOPS_RETIRED.MS", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_10H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_01H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.FP_ASSIST", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.ALL", IAP_EVENT_C3H_08H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.JCC", IAP_EVENT_C4H_7EH) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_BFH) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NON_RETURN_IND", IAP_EVENT_C4H_EBH) \
__PMC_EV_ALIAS("BR_INST_RETIRED.RETURN", IAP_EVENT_C4H_F7H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CALL", IAP_EVENT_C4H_F9H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.IND_CALL", IAP_EVENT_C4H_FBH) \
__PMC_EV_ALIAS("BR_INST_RETIRED.REL_CALL", IAP_EVENT_C4H_FDH) \
__PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN_JCC", IAP_EVENT_C4H_FEH) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.JCC", IAP_EVENT_C5H_7EH) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.FAR", IAP_EVENT_C5H_BFH) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.NON_RETURN_IND", IAP_EVENT_C5H_EBH) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.RETURN", IAP_EVENT_C5H_F7H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CALL", IAP_EVENT_C5H_F9H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.IND_CALL", IAP_EVENT_C5H_FBH) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.REL_CALL", IAP_EVENT_C5H_FDH) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN_JCC", IAP_EVENT_C5H_FEH) \
__PMC_EV_ALIAS("NO_ALLOC_CYCLES.ROB_FULL", IAP_EVENT_CAH_01H) \
__PMC_EV_ALIAS("NO_ALLOC_CYCLES.RAT_STALL", IAP_EVENT_CAH_20H) \
__PMC_EV_ALIAS("NO_ALLOC_CYCLES.ALL", IAP_EVENT_CAH_3FH) \
__PMC_EV_ALIAS("NO_ALLOC_CYCLES.NOT_DELIVERED", IAP_EVENT_CAH_50H) \
__PMC_EV_ALIAS("RS_FULL_STALL.MEC", IAP_EVENT_CBH_01H) \
__PMC_EV_ALIAS("RS_FULL_STALL.ALL", IAP_EVENT_CBH_1FH) \
__PMC_EV_ALIAS("CYCLES_DIV_BUSY.ANY", IAP_EVENT_CDH_01H) \
__PMC_EV_ALIAS("BACLEARS.ALL", IAP_EVENT_E6H_01H) \
__PMC_EV_ALIAS("BACLEARS.RETURN", IAP_EVENT_E6H_08H) \
__PMC_EV_ALIAS("BACLEARS.COND", IAP_EVENT_E6H_10H) \
__PMC_EV_ALIAS("MS_DECODED.MS_ENTRY", IAP_EVENT_E7H_01H)
hwpmc: add initial Intel Broadwell support. The full list of aliases and events will follow in a subsequent commit. MFC after: 1 month
2015-04-05 05:14:20 +00:00
/*
* Aliases for Broadwell PMC events.
*/
#define __PMC_EV_ALIAS_BROADWELL() \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \
__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \
__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \
__PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \
__PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \
__PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \
IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \
IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \
__PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \
IAP_EVENT_58H_04H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \
IAP_EVENT_58H_08H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
IAP_EVENT_60H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \
IAP_EVENT_60H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \
IAP_EVENT_63H_01H) \
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \
__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
__PMC_EV_ALIAS("BR_MISP_EXE.COND", IAP_EVENT_89H_01H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_HIT", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \
IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \
IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \
IAP_EVENT_D3H_01H) \
__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \
__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H)
/*
* Aliases for Broadwell XEON PMC events.
*/
#define __PMC_EV_ALIAS_BROADWELL_XEON() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \
__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \
__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) /**/ \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \
__PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \
__PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \
__PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \
IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \
IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \
__PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \
IAP_EVENT_58H_04H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \
IAP_EVENT_58H_08H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
IAP_EVENT_60H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \
IAP_EVENT_60H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \
IAP_EVENT_63H_01H) \
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \
__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
__PMC_EV_ALIAS("BR_MISP_EXE.COND", IAP_EVENT_89H_01H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_HIT", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \
IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \
IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \
IAP_EVENT_D3H_01H) \
__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \
__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H)
/*
* Alisases for Skylake
*/
#define __PMC_EV_ALIAS_SKYLAKE() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_PENDING", IAP_EVENT_08H_10H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_20H) \
__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_01H) \
__PMC_EV_ALIAS("INT_MISC.CLEAR_RESTEER_CYCLES", IAP_EVENT_0DH_80H) \
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.VECTORS_WIDTH_MISMATCH", IAP_EVENT_0EH_02H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \
__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_38H) \
__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_D8H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_F7H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \
__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_EFH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", \
IAP_EVENT_3CH_02H) \
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
__PMC_EV_ALIAS("L1D_PEND_MISS.FB_FULL", IAP_EVENT_48H_02H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \
IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_PENDING", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_20H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_01H) \
__PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
IAP_EVENT_60H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \
IAP_EVENT_60H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", \
IAP_EVENT_60H_10H) \
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
__PMC_EV_ALIAS("ICACHE_16B.IFDATA_STALL", IAP_EVENT_80H_04H) \
__PMC_EV_ALIAS("ICACHE_64B.IFTAG_HIT", IAP_EVENT_83H_01H) \
__PMC_EV_ALIAS("ICACHE_64B.IFTAG_MISS", IAP_EVENT_83H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_PENDING", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_20H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_MISS", IAP_EVENT_A3H_01H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L3_MISS", IAP_EVENT_A3H_02H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_TOTAL", IAP_EVENT_A3H_04H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_MISS", IAP_EVENT_A3H_05H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L3_MISS", IAP_EVENT_A3H_06H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_MISS", IAP_EVENT_A3H_08H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L1D_MISS", IAP_EVENT_A3H_0CH) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_MEM_ANY", IAP_EVENT_A3H_10H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_MEM_ANY", IAP_EVENT_A3H_14H) \
__PMC_EV_ALIAS("EXE_ACTIVITY.EXE_BOUND_0_PORTS", IAP_EVENT_A6H_01H) \
__PMC_EV_ALIAS("EXE_ACTIVITY.1_PORTS_UTIL", IAP_EVENT_A6H_02H) \
__PMC_EV_ALIAS("EXE_ACTIVITY.2_PORTS_UTIL", IAP_EVENT_A6H_04H) \
__PMC_EV_ALIAS("EXE_ACTIVITY.3_PORTS_UTIL", IAP_EVENT_A6H_08H) \
__PMC_EV_ALIAS("EXE_ACTIVITY.4_PORTS_UTIL", IAP_EVENT_A6H_10H) \
__PMC_EV_ALIAS("EXE_ACTIVITY.BOUND_ON_STORES", IAP_EVENT_A6H_40H) \
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", \
IAP_EVENT_B0H_10H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_REQUESTS", IAP_EVENT_B0H_80H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.X87", IAP_EVENT_B1H_10H) \
__PMC_EV_ALIAS("OFF_CORE_REQUEST_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.ANY", IAP_EVENT_C1H_3FH) \
__PMC_EV_ALIAS("UOPS_RETIRED.STALL_CYCLES", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_TAKEN", IAP_EVENT_C5H_20H) \
__PMC_EV_ALIAS("FRONTEND_RETIRED.DSB_MISS", IAP_EVENT_C6H_01H) \
__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_01H) \
__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \
__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.128B_PACKED_DOUBLE", \
IAP_EVENT_C7H_04H) \
__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.128B_PACKED_SINGLE", \
IAP_EVENT_C7H_08H) \
__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.256B_PACKED_DOUBLE", \
IAP_EVENT_C7H_10H) \
__PMC_EV_ALIAS("FP_ARIT_INST_RETIRED.256B_PACKED_SINGLE", \
IAP_EVENT_C7H_20H) \
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
__PMC_EV_ALIAS("HW_INTERRUPTS.RECEIVED", IAP_EVENT_CBH_01H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_HIT", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.FB_HIT", IAP_EVENT_D1H_40H) \
__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", \
IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", \
IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_01H) \
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H)
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
2014-03-20 20:51:08 +00:00
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
/*
* Aliases for Core PMC events.
*/
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
#define __PMC_EV_ALIAS_CORE() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("BAClears", IAP_EVENT_E6H_00H) \
__PMC_EV_ALIAS("BTB_Misses", IAP_EVENT_E2H_00H) \
__PMC_EV_ALIAS("Br_BAC_Missp_Exec", IAP_EVENT_8AH_00H) \
__PMC_EV_ALIAS("Br_Bogus", IAP_EVENT_E4H_00H) \
__PMC_EV_ALIAS("Br_Call_Exec", IAP_EVENT_92H_00H) \
__PMC_EV_ALIAS("Br_Call_Missp_Exec", IAP_EVENT_93H_00H) \
__PMC_EV_ALIAS("Br_Cnd_Exec", IAP_EVENT_8BH_00H) \
__PMC_EV_ALIAS("Br_Cnd_Missp_Exec", IAP_EVENT_8CH_00H) \
__PMC_EV_ALIAS("Br_Ind_Call_Exec", IAP_EVENT_94H_00H) \
__PMC_EV_ALIAS("Br_Ind_Exec", IAP_EVENT_8DH_00H) \
__PMC_EV_ALIAS("Br_Ind_Missp_Exec", IAP_EVENT_8EH_00H) \
__PMC_EV_ALIAS("Br_Inst_Exec", IAP_EVENT_88H_00H) \
__PMC_EV_ALIAS("Br_Instr_Decoded", IAP_EVENT_E0H_00H) \
__PMC_EV_ALIAS("Br_Instr_Ret", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("Br_MisPred_Ret", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("Br_MisPred_Taken_Ret", IAP_EVENT_CAH_00H) \
__PMC_EV_ALIAS("Br_Missp_Exec", IAP_EVENT_89H_00H) \
__PMC_EV_ALIAS("Br_Ret_BAC_Missp_Exec", IAP_EVENT_91H_00H) \
__PMC_EV_ALIAS("Br_Ret_Exec", IAP_EVENT_8FH_00H) \
__PMC_EV_ALIAS("Br_Ret_Missp_Exec", IAP_EVENT_90H_00H) \
__PMC_EV_ALIAS("Br_Taken_Ret", IAP_EVENT_C9H_00H) \
__PMC_EV_ALIAS("Bus_BNR_Clocks", IAP_EVENT_61H_00H) \
__PMC_EV_ALIAS("Bus_DRDY_Clocks", IAP_EVENT_62H_00H) \
__PMC_EV_ALIAS("Bus_Data_Rcv", IAP_EVENT_64H_40H) \
__PMC_EV_ALIAS("Bus_Locks_Clocks", IAP_EVENT_63H) \
__PMC_EV_ALIAS("Bus_Not_In_Use", IAP_EVENT_7DH) \
__PMC_EV_ALIAS("Bus_Req_Outstanding", IAP_EVENT_60H) \
__PMC_EV_ALIAS("Bus_Snoop_Stall", IAP_EVENT_7EH_00H) \
__PMC_EV_ALIAS("Bus_Snoops", IAP_EVENT_77H) \
__PMC_EV_ALIAS("Bus_Trans_Any", IAP_EVENT_70H) \
__PMC_EV_ALIAS("Bus_Trans_Brd", IAP_EVENT_65H) \
__PMC_EV_ALIAS("Bus_Trans_Burst", IAP_EVENT_6EH) \
__PMC_EV_ALIAS("Bus_Trans_Def", IAP_EVENT_6DH) \
__PMC_EV_ALIAS("Bus_Trans_IO", IAP_EVENT_6CH) \
__PMC_EV_ALIAS("Bus_Trans_Ifetch", IAP_EVENT_68H) \
__PMC_EV_ALIAS("Bus_Trans_Inval", IAP_EVENT_69H) \
__PMC_EV_ALIAS("Bus_Trans_Mem", IAP_EVENT_6FH) \
__PMC_EV_ALIAS("Bus_Trans_P", IAP_EVENT_6BH) \
__PMC_EV_ALIAS("Bus_Trans_Pwr", IAP_EVENT_6AH) \
__PMC_EV_ALIAS("Bus_Trans_RFO", IAP_EVENT_66H) \
__PMC_EV_ALIAS("Bus_Trans_WB", IAP_EVENT_67H) \
__PMC_EV_ALIAS("Cycles_Div_Busy", IAP_EVENT_14H_00H) \
__PMC_EV_ALIAS("Cycles_Int_Masked", IAP_EVENT_C6H_00H) \
__PMC_EV_ALIAS("Cycles_Int_Pending_Masked", IAP_EVENT_C7H_00H) \
__PMC_EV_ALIAS("DCU_Snoop_To_Share", IAP_EVENT_78H) \
__PMC_EV_ALIAS("DCache_Cache_LD", IAP_EVENT_40H) \
__PMC_EV_ALIAS("DCache_Cache_Lock", IAP_EVENT_42H) \
__PMC_EV_ALIAS("DCache_Cache_ST", IAP_EVENT_41H) \
__PMC_EV_ALIAS("DCache_M_Evict", IAP_EVENT_47H_00H) \
__PMC_EV_ALIAS("DCache_M_Repl", IAP_EVENT_46H_00H) \
__PMC_EV_ALIAS("DCache_Pend_Miss", IAP_EVENT_48H_00H) \
__PMC_EV_ALIAS("DCache_Repl", IAP_EVENT_45H_0FH) \
__PMC_EV_ALIAS("Data_Mem_Cache_Ref", IAP_EVENT_44H_02H) \
__PMC_EV_ALIAS("Data_Mem_Ref", IAP_EVENT_43H_01H) \
__PMC_EV_ALIAS("Dbus_Busy", IAP_EVENT_22H) \
__PMC_EV_ALIAS("Dbus_Busy_Rd", IAP_EVENT_23H) \
__PMC_EV_ALIAS("Div", IAP_EVENT_13H_00H) \
__PMC_EV_ALIAS("Dtlb_Miss", IAP_EVENT_49H_00H) \
__PMC_EV_ALIAS("ESP_Uops", IAP_EVENT_D7H_00H) \
__PMC_EV_ALIAS("EST_Trans", IAP_EVENT_3AH) \
__PMC_EV_ALIAS("FP_Assist", IAP_EVENT_11H_00H) \
__PMC_EV_ALIAS("FP_Comp_Instr_Ret", IAP_EVENT_C1H_00H) \
__PMC_EV_ALIAS("FP_Comps_Op_Exe", IAP_EVENT_10H_00H) \
__PMC_EV_ALIAS("FP_MMX_Trans", IAP_EVENT_CCH_01H) \
__PMC_EV_ALIAS("Fused_Ld_Uops_Ret", IAP_EVENT_DAH_01H) \
__PMC_EV_ALIAS("Fused_St_Uops_Ret", IAP_EVENT_DAH_02H) \
__PMC_EV_ALIAS("Fused_Uops_Ret", IAP_EVENT_DAH_00H) \
__PMC_EV_ALIAS("HW_Int_Rx", IAP_EVENT_C8H_00H) \
__PMC_EV_ALIAS("ICache_Misses", IAP_EVENT_81H_00H) \
__PMC_EV_ALIAS("ICache_Reads", IAP_EVENT_80H_00H) \
__PMC_EV_ALIAS("IFU_Mem_Stall", IAP_EVENT_86H_00H) \
__PMC_EV_ALIAS("ILD_Stall", IAP_EVENT_87H_00H) \
__PMC_EV_ALIAS("ITLB_Misses", IAP_EVENT_85H_00H) \
__PMC_EV_ALIAS("Instr_Decoded", IAP_EVENT_D0H_00H) \
__PMC_EV_ALIAS("Instr_Ret", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("L1_Pref_Req", IAP_EVENT_4FH_00H) \
__PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \
__PMC_EV_ALIAS("L2_IFetch", IAP_EVENT_28H) \
__PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \
__PMC_EV_ALIAS("L2_Lines_In", IAP_EVENT_24H) \
__PMC_EV_ALIAS("L2_Lines_Out", IAP_EVENT_26H) \
__PMC_EV_ALIAS("L2_M_Lines_In", IAP_EVENT_25H) \
__PMC_EV_ALIAS("L2_M_Lines_Out", IAP_EVENT_27H) \
__PMC_EV_ALIAS("L2_No_Request_Cycles", IAP_EVENT_32H) \
__PMC_EV_ALIAS("L2_Reject_Cycles", IAP_EVENT_30H) \
__PMC_EV_ALIAS("L2_Rqsts", IAP_EVENT_2EH) \
__PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \
__PMC_EV_ALIAS("LD_Blocks", IAP_EVENT_03H_00H) \
__PMC_EV_ALIAS("LLC_Misses", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("LLC_Reference", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("MMX_Assist", IAP_EVENT_CDH_00H) \
__PMC_EV_ALIAS("MMX_FP_Trans", IAP_EVENT_CCH_00H) \
__PMC_EV_ALIAS("MMX_Instr_Exec", IAP_EVENT_B0H_00H) \
__PMC_EV_ALIAS("MMX_Instr_Ret", IAP_EVENT_CEH_00H) \
__PMC_EV_ALIAS("Misalign_Mem_Ref", IAP_EVENT_05H_00H) \
__PMC_EV_ALIAS("Mul", IAP_EVENT_12H_00H) \
__PMC_EV_ALIAS("NonHlt_Ref_Cycles", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("Pref_Rqsts_Dn", IAP_EVENT_F8H_00H) \
__PMC_EV_ALIAS("Pref_Rqsts_Up", IAP_EVENT_F0H_00H) \
__PMC_EV_ALIAS("Resource_Stall", IAP_EVENT_A2H_00H) \
__PMC_EV_ALIAS("SD_Drains", IAP_EVENT_04H_00H) \
__PMC_EV_ALIAS("SIMD_FP_DP_P_Comp_Ret", IAP_EVENT_D9H_02H) \
__PMC_EV_ALIAS("SIMD_FP_DP_P_Ret", IAP_EVENT_D8H_02H) \
__PMC_EV_ALIAS("SIMD_FP_DP_S_Comp_Ret", IAP_EVENT_D9H_03H) \
__PMC_EV_ALIAS("SIMD_FP_DP_S_Ret", IAP_EVENT_D8H_03H) \
__PMC_EV_ALIAS("SIMD_FP_SP_P_Comp_Ret", IAP_EVENT_D9H_00H) \
__PMC_EV_ALIAS("SIMD_FP_SP_Ret", IAP_EVENT_D8H_00H) \
__PMC_EV_ALIAS("SIMD_FP_SP_S_Comp_Ret", IAP_EVENT_D9H_01H) \
__PMC_EV_ALIAS("SIMD_FP_SP_S_Ret", IAP_EVENT_D8H_01H) \
__PMC_EV_ALIAS("SIMD_Int_128_Ret", IAP_EVENT_D8H_04H) \
__PMC_EV_ALIAS("SIMD_Int_Pari_Exec", IAP_EVENT_B3H_20H) \
__PMC_EV_ALIAS("SIMD_Int_Pck_Exec", IAP_EVENT_B3H_04H) \
__PMC_EV_ALIAS("SIMD_Int_Plog_Exec", IAP_EVENT_B3H_10H) \
__PMC_EV_ALIAS("SIMD_Int_Pmul_Exec", IAP_EVENT_B3H_01H) \
__PMC_EV_ALIAS("SIMD_Int_Psft_Exec", IAP_EVENT_B3H_02H) \
__PMC_EV_ALIAS("SIMD_Int_Sat_Exec", IAP_EVENT_B1H_00H) \
__PMC_EV_ALIAS("SIMD_Int_Upck_Exec", IAP_EVENT_B3H_08H) \
__PMC_EV_ALIAS("SMC_Detected", IAP_EVENT_C3H_00H) \
__PMC_EV_ALIAS("SSE_NTStores_Miss", IAP_EVENT_4BH_03H) \
__PMC_EV_ALIAS("SSE_NTStores_Ret", IAP_EVENT_07H_03H) \
__PMC_EV_ALIAS("SSE_PrefNta_Miss", IAP_EVENT_4BH_00H) \
__PMC_EV_ALIAS("SSE_PrefNta_Ret", IAP_EVENT_07H_00H) \
__PMC_EV_ALIAS("SSE_PrefT1_Miss", IAP_EVENT_4BH_01H) \
__PMC_EV_ALIAS("SSE_PrefT1_Ret", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("SSE_PrefT2_Miss", IAP_EVENT_4BH_02H) \
__PMC_EV_ALIAS("SSE_PrefT2_Ret", IAP_EVENT_07H_02H) \
__PMC_EV_ALIAS("Seg_Reg_Loads", IAP_EVENT_06H_00H) \
__PMC_EV_ALIAS("Serial_Execution_Cycles", IAP_EVENT_3CH_02H) \
__PMC_EV_ALIAS("Thermal_Trip", IAP_EVENT_3BH_C0H) \
__PMC_EV_ALIAS("Unfusion", IAP_EVENT_DBH_00H) \
__PMC_EV_ALIAS("Unhalted_Core_Cycles", IAP_EVENT_3CH_00H) \
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
2008-11-27 09:00:47 +00:00
__PMC_EV_ALIAS("Uops_Ret", IAP_EVENT_C2H_00H)
/*
* Aliases for Core2 PMC events.
*/
#define __PMC_EV_ALIAS_CORE2() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("BACLEARS", IAP_EVENT_E6H_00H) \
__PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_00H) \
__PMC_EV_ALIAS("BR_BAC_MISSP_EXEC", IAP_EVENT_8AH_00H) \
__PMC_EV_ALIAS("BR_CALL_EXEC", IAP_EVENT_92H_00H) \
__PMC_EV_ALIAS("BR_CALL_MISSP_EXEC", IAP_EVENT_93H_00H) \
__PMC_EV_ALIAS("BR_CND_EXEC", IAP_EVENT_8BH_00H) \
__PMC_EV_ALIAS("BR_CND_MISSP_EXEC", IAP_EVENT_8CH_00H) \
__PMC_EV_ALIAS("BR_IND_CALL_EXEC", IAP_EVENT_94H_00H) \
__PMC_EV_ALIAS("BR_IND_EXEC", IAP_EVENT_8DH_00H) \
__PMC_EV_ALIAS("BR_IND_MISSP_EXEC", IAP_EVENT_8EH_00H) \
__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_00H) \
__PMC_EV_ALIAS("BR_INST_EXEC", IAP_EVENT_88H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ANY", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN", \
IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN", \
IAP_EVENT_C4H_08H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN", \
IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN", \
IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN", IAP_EVENT_C4H_0CH) \
__PMC_EV_ALIAS("BR_MISSP_EXEC", IAP_EVENT_89H_00H) \
__PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC", IAP_EVENT_91H_00H) \
__PMC_EV_ALIAS("BR_RET_EXEC", IAP_EVENT_8FH_00H) \
__PMC_EV_ALIAS("BR_RET_MISSP_EXEC", IAP_EVENT_90H_00H) \
__PMC_EV_ALIAS("BR_TKN_BUBBLE_1", IAP_EVENT_97H_00H) \
__PMC_EV_ALIAS("BR_TKN_BUBBLE_2", IAP_EVENT_98H_00H) \
__PMC_EV_ALIAS("BUSQ_EMPTY", IAP_EVENT_7DH) \
__PMC_EV_ALIAS("BUS_BNR_DRV", IAP_EVENT_61H) \
__PMC_EV_ALIAS("BUS_DATA_RCV", IAP_EVENT_64H) \
__PMC_EV_ALIAS("BUS_DRDY_CLOCKS", IAP_EVENT_62H) \
__PMC_EV_ALIAS("BUS_HITM_DRV", IAP_EVENT_7BH) \
__PMC_EV_ALIAS("BUS_HIT_DRV", IAP_EVENT_7AH) \
__PMC_EV_ALIAS("BUS_IO_WAIT", IAP_EVENT_7FH) \
__PMC_EV_ALIAS("BUS_LOCK_CLOCKS", IAP_EVENT_63H) \
__PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING", \
IAP_EVENT_60H) \
__PMC_EV_ALIAS("BUS_TRANS_ANY", IAP_EVENT_70H) \
__PMC_EV_ALIAS("BUS_TRANS_BRD", IAP_EVENT_65H) \
__PMC_EV_ALIAS("BUS_TRANS_BURST", IAP_EVENT_6EH) \
__PMC_EV_ALIAS("BUS_TRANS_DEF", IAP_EVENT_6DH) \
__PMC_EV_ALIAS("BUS_TRANS_IFETCH", IAP_EVENT_68H) \
__PMC_EV_ALIAS("BUS_TRANS_INVAL", IAP_EVENT_69H) \
__PMC_EV_ALIAS("BUS_TRANS_IO", IAP_EVENT_6CH) \
__PMC_EV_ALIAS("BUS_TRANS_MEM", IAP_EVENT_6FH) \
__PMC_EV_ALIAS("BUS_TRANS_P", IAP_EVENT_6BH) \
__PMC_EV_ALIAS("BUS_TRANS_PWR", IAP_EVENT_6AH) \
__PMC_EV_ALIAS("BUS_TRANS_RFO", IAP_EVENT_66H) \
__PMC_EV_ALIAS("BUS_TRANS_WB", IAP_EVENT_67H) \
__PMC_EV_ALIAS("CMP_SNOOP", IAP_EVENT_78H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", \
IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER", \
IAP_EVENT_3CH_02H) \
__PMC_EV_ALIAS("CYCLES_DIV_BUSY", IAP_EVENT_14H_00H) \
__PMC_EV_ALIAS("CYCLES_INT_MASKED", IAP_EVENT_C6H_01H) \
__PMC_EV_ALIAS("CYCLES_INT_PENDING_AND_MASKED", \
IAP_EVENT_C6H_02H) \
__PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED", IAP_EVENT_86H_00H) \
__PMC_EV_ALIAS("DELAYED_BYPASS.FP", IAP_EVENT_19H_00H) \
__PMC_EV_ALIAS("DELAYED_BYPASS.LOAD", IAP_EVENT_19H_01H) \
__PMC_EV_ALIAS("DELAYED_BYPASS.SIMD", IAP_EVENT_19H_02H) \
__PMC_EV_ALIAS("DIV", IAP_EVENT_13H_00H) \
__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_08H_01H) \
__PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD", IAP_EVENT_08H_04H) \
__PMC_EV_ALIAS("DTLB_MISSES.MISS_LD", IAP_EVENT_08H_02H) \
__PMC_EV_ALIAS("DTLB_MISSES.MISS_ST", IAP_EVENT_08H_08H) \
__PMC_EV_ALIAS("EIST_TRANS", IAP_EVENT_3AH_00H) \
__PMC_EV_ALIAS("ESP.ADDITIONS", IAP_EVENT_ABH_02H) \
__PMC_EV_ALIAS("ESP.SYNCH", IAP_EVENT_ABH_01H) \
__PMC_EV_ALIAS("EXT_SNOOP", IAP_EVENT_77H) \
__PMC_EV_ALIAS("FP_ASSIST", IAP_EVENT_11H_00H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE", IAP_EVENT_10H_00H) \
__PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP", IAP_EVENT_CCH_02H) \
__PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX", IAP_EVENT_CCH_01H) \
__PMC_EV_ALIAS("HW_INT_RCV", IAP_EVENT_C8H_00H) \
__PMC_EV_ALIAS("IDLE_DURING_DIV", IAP_EVENT_18H_00H) \
__PMC_EV_ALIAS("ILD_STALL", IAP_EVENT_87H_00H) \
__PMC_EV_ALIAS("INST_QUEUE.FULL", IAP_EVENT_83H_02H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("INST_RETIRED.LOADS", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("INST_RETIRED.OTHER", IAP_EVENT_C0H_04H) \
__PMC_EV_ALIAS("INST_RETIRED.STORES", IAP_EVENT_C0H_02H) \
__PMC_EV_ALIAS("INST_RETIRED.VM_H", IAP_EVENT_C0H_08H) \
__PMC_EV_ALIAS("ITLB.FLUSH", IAP_EVENT_82H_40H) \
__PMC_EV_ALIAS("ITLB.LARGE_MISS", IAP_EVENT_82H_10H) \
__PMC_EV_ALIAS("ITLB.MISSES", IAP_EVENT_82H_12H) \
__PMC_EV_ALIAS("ITLB.SMALL_MISS", IAP_EVENT_82H_02H) \
__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C9H_00H) \
__PMC_EV_ALIAS("L1D_ALL_CACHE_REF", IAP_EVENT_43H_02H) \
__PMC_EV_ALIAS("L1D_ALL_REF", IAP_EVENT_43H_01H) \
__PMC_EV_ALIAS("L1D_CACHE_LD", IAP_EVENT_40H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK", IAP_EVENT_42H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION", IAP_EVENT_42H_10H) \
__PMC_EV_ALIAS("L1D_CACHE_ST", IAP_EVENT_41H) \
__PMC_EV_ALIAS("L1D_M_EVICT", IAP_EVENT_47H_00H) \
__PMC_EV_ALIAS("L1D_M_REPL", IAP_EVENT_46H_00H) \
__PMC_EV_ALIAS("L1D_PEND_MISS", IAP_EVENT_48H_00H) \
__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_10H) \
__PMC_EV_ALIAS("L1D_REPL", IAP_EVENT_45H_0FH) \
__PMC_EV_ALIAS("L1D_SPLIT.LOADS", IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("L1D_SPLIT.STORES", IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("L1I_MISSES", IAP_EVENT_81H_00H) \
__PMC_EV_ALIAS("L1I_READS", IAP_EVENT_80H_00H) \
__PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \
__PMC_EV_ALIAS("L2_DBUS_BUSY_RD", IAP_EVENT_23H) \
__PMC_EV_ALIAS("L2_IFETCH", IAP_EVENT_28H) \
__PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \
__PMC_EV_ALIAS("L2_LINES_IN", IAP_EVENT_24H) \
__PMC_EV_ALIAS("L2_LINES_OUT", IAP_EVENT_26H) \
__PMC_EV_ALIAS("L2_LOCK", IAP_EVENT_2BH) \
__PMC_EV_ALIAS("L2_M_LINES_IN", IAP_EVENT_25H) \
__PMC_EV_ALIAS("L2_M_LINES_OUT", IAP_EVENT_27H) \
__PMC_EV_ALIAS("L2_NO_REQ", IAP_EVENT_32H) \
__PMC_EV_ALIAS("L2_REJECT_BUSQ", IAP_EVENT_30H) \
__PMC_EV_ALIAS("L2_RQSTS", IAP_EVENT_2EH) \
__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE", \
IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI", \
IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \
__PMC_EV_ALIAS("LOAD_BLOCK.L1D", IAP_EVENT_03H_20H) \
__PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", \
IAP_EVENT_03H_08H) \
__PMC_EV_ALIAS("LOAD_BLOCK.STA", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_04H) \
__PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE", IAP_EVENT_03H_10H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_00H) \
__PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_NUKES.SMC", IAP_EVENT_C3H_01H) \
__PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED", IAP_EVENT_AAH_08H) \
__PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_AAH_01H) \
__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET", \
IAP_EVENT_09H_01H) \
__PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS", \
IAP_EVENT_09H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", \
IAP_EVENT_CBH_10H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_LINE_MISS", \
IAP_EVENT_CBH_02H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_MISS", \
IAP_EVENT_CBH_01H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS", \
IAP_EVENT_CBH_08H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS", \
IAP_EVENT_CBH_04H) \
__PMC_EV_ALIAS("MUL", IAP_EVENT_12H_00H) \
__PMC_EV_ALIAS("PAGE_WALKS.COUNT", IAP_EVENT_0CH_01H) \
__PMC_EV_ALIAS("PAGE_WALKS.CYCLES", IAP_EVENT_0CH_02H) \
__PMC_EV_ALIAS("PREF_RQSTS_DN", IAP_EVENT_F8H_00H) \
__PMC_EV_ALIAS("PREF_RQSTS_UP", IAP_EVENT_F0H_00H) \
__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \
__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("RAT_STALLS.FPSW", IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("RAT_STALLS.OTHER_SERIALIZATION_STALLS", \
IAP_EVENT_D2H_10H) \
__PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_DCH_1FH) \
__PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR", \
IAP_EVENT_DCH_10H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_DCH_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST", IAP_EVENT_DCH_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", \
IAP_EVENT_DCH_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_DCH_02H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED", IAP_EVENT_A0H_00H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("SB_DRAIN_CYCLES", IAP_EVENT_04H_01H) \
__PMC_EV_ALIAS("SEGMENT_REG_LOADS", IAP_EVENT_06H_00H) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.ANY", IAP_EVENT_D5H_0FH) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.DS", IAP_EVENT_D5H_02H) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.ES", IAP_EVENT_D5H_01H) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.FS", IAP_EVENT_D5H_04H) \
__PMC_EV_ALIAS("SEG_REG_RENAMES.GS", IAP_EVENT_D5H_08H) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY", IAP_EVENT_D4H_0FH) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.DS", IAP_EVENT_D4H_02H) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.ES", IAP_EVENT_D4H_01H) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.FS", IAP_EVENT_D4H_04H) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS.GS", IAP_EVENT_D4H_08H) \
__PMC_EV_ALIAS("SIMD_ASSIST", IAP_EVENT_CDH_00H) \
__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", \
IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE", \
IAP_EVENT_CAH_01H) \
__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", \
IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", \
IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("SIMD_INSTR_RETIRED", IAP_EVENT_CEH_00H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY", IAP_EVENT_C7H_1FH) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE", \
IAP_EVENT_C7H_04H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE", \
IAP_EVENT_C7H_01H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE", \
IAP_EVENT_C7H_08H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE", \
IAP_EVENT_C7H_02H) \
__PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR", IAP_EVENT_C7H_10H) \
__PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED", IAP_EVENT_CFH_00H) \
__PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC", IAP_EVENT_B1H_00H) \
__PMC_EV_ALIAS("SIMD_UOPS_EXEC", IAP_EVENT_B0H_00H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC", IAP_EVENT_B3H_20H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL", IAP_EVENT_B3H_10H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL", IAP_EVENT_B3H_01H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK", IAP_EVENT_B3H_04H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT", IAP_EVENT_B3H_02H) \
__PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK", IAP_EVENT_B3H_08H) \
__PMC_EV_ALIAS("SNOOP_STALL_DRV", IAP_EVENT_7EH) \
__PMC_EV_ALIAS("SSE_PRE_EXEC.L1", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("SSE_PRE_EXEC.L2", IAP_EVENT_07H_02H) \
__PMC_EV_ALIAS("SSE_PRE_EXEC.NTA", IAP_EVENT_07H_00H) \
__PMC_EV_ALIAS("SSE_PRE_EXEC.STORES", IAP_EVENT_07H_03H) \
__PMC_EV_ALIAS("SSE_PRE_MISS.L1", IAP_EVENT_4BH_01H) \
__PMC_EV_ALIAS("SSE_PRE_MISS.L2", IAP_EVENT_4BH_02H) \
__PMC_EV_ALIAS("SSE_PRE_MISS.NTA", IAP_EVENT_4BH_00H) \
__PMC_EV_ALIAS("STORE_BLOCK.ORDER", IAP_EVENT_04H_02H) \
__PMC_EV_ALIAS("STORE_BLOCK.SNOOP", IAP_EVENT_04H_08H) \
__PMC_EV_ALIAS("THERMAL_TRIP", IAP_EVENT_3BH_C0H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_0FH) \
__PMC_EV_ALIAS("UOPS_RETIRED.FUSED", IAP_EVENT_C2H_07H) \
__PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION", IAP_EVENT_C2H_04H) \
__PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED", IAP_EVENT_C2H_08H) \
__PMC_EV_ALIAS("UOPS_RETIRED.STD_STA", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("X87_OPS_RETIRED.ANY", IAP_EVENT_C1H_FEH) \
__PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH", IAP_EVENT_C1H_01H)
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
- Add support for nehalem/corei7 cpus. This supports all of the core counters defined in the reference manual. It does not support the 'uncore' events. Reviewed by: jkoshy Sponsored by: Nokia
2009-01-27 07:29:37 +00:00
/*
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
* Core i7 and Xeon 5500 events removed between 253669-031US June 2009
Update PMC events from October 2011 Intel documentation. Submitted by: Davide Italiano <davide.italiano@gmail.com> MFC after: 3 days
2012-01-04 07:58:36 +00:00
* and 253669-040US October 2011.
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
*/
#define __PMC_EV_ALIAS_COREI7_OLD() \
__PMC_EV_ALIAS("SB_FORWARD.ANY", IAP_EVENT_02H_01H) \
__PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_01H) \
__PMC_EV_ALIAS("LOAD_BLOCK.ADDRESS_OFFSET", IAP_EVENT_03H_04H) \
__PMC_EV_ALIAS("SB_DRAIN.CYCLES", IAP_EVENT_04H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOAD", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORE", IAP_EVENT_05H_02H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.ANY", IAP_EVENT_05H_03H) \
__PMC_EV_ALIAS("STORE_BLOCKS.NOT_STA", IAP_EVENT_06H_01H) \
__PMC_EV_ALIAS("STORE_BLOCKS.STA", IAP_EVENT_06H_02H) \
__PMC_EV_ALIAS("STORE_BLOCKS.ANY", IAP_EVENT_06H_0FH) \
Update PMC events from October 2011 Intel documentation. Submitted by: Davide Italiano <davide.italiano@gmail.com> MFC after: 3 days
2012-01-04 07:58:36 +00:00
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDP_MISS", IAP_EVENT_08H_40H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.RESET", IAP_EVENT_09H_01H) \
__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.SUCCESS", IAP_EVENT_09H_02H) \
__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCHDOG", IAP_EVENT_09H_04H) \
__PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCH_CYCLES", IAP_EVENT_09H_08H)\
__PMC_EV_ALIAS("HW_INT.RCV", IAP_EVENT_1DH_01H) \
__PMC_EV_ALIAS("HW_INT.CYCLES_MASKED", IAP_EVENT_1DH_02H) \
__PMC_EV_ALIAS("HW_INT.CYCLES_PENDING_AND_MASKED", IAP_EVENT_1DH_04H) \
__PMC_EV_ALIAS("L2_WRITE.RFO.E_STATE", IAP_EVENT_27H_04H) \
__PMC_EV_ALIAS("UOPS_DECODED.DEC0", IAP_EVENT_3DH_01H) \
__PMC_EV_ALIAS("L1D_CACHE_ST.I_STATE", IAP_EVENT_41H_01H) \
__PMC_EV_ALIAS("L1D_CACHE_ST.MESI", IAP_EVENT_41H_0FH) \
Update PMC events from October 2011 Intel documentation. Submitted by: Davide Italiano <davide.italiano@gmail.com> MFC after: 3 days
2012-01-04 07:58:36 +00:00
__PMC_EV_ALIAS("L1D_PEND_MISS.LOAD_BUFFERS_FULL", IAP_EVENT_48H_02H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("DTLB_MISSES.PDP_MISS", IAP_EVENT_49H_40H) \
__PMC_EV_ALIAS("SSE_MEM_EXEC.NTA", IAP_EVENT_4BH_01H) \
__PMC_EV_ALIAS("SSE_MEM_EXEC.STREAMING_STORES", IAP_EVENT_4BH_08H) \
__PMC_EV_ALIAS("SFENCE_CYCLES", IAP_EVENT_4DH_01H) \
__PMC_EV_ALIAS("EPT.EPDE_MISS", IAP_EVENT_4FH_02H) \
__PMC_EV_ALIAS("EPT.EPDPE_HIT", IAP_EVENT_4FH_04H) \
__PMC_EV_ALIAS("EPT.EPDPE_MISS", IAP_EVENT_4FH_08H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", \
IAP_EVENT_60H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", \
IAP_EVENT_60H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("IFU_IVC.FULL", IAP_EVENT_81H_01H) \
__PMC_EV_ALIAS("IFU_IVC.L1I_EVICTION", IAP_EVENT_81H_02H) \
__PMC_EV_ALIAS("L1I_OPPORTUNISTIC_HITS", IAP_EVENT_83H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H) \
__PMC_EV_ALIAS("ITLB_MISSES.PMH_BUSY_CYCLES", IAP_EVENT_85H_04H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ITLB_MISSES.PDE_MISS", IAP_EVENT_85H_20H) \
__PMC_EV_ALIAS("ITLB_MISSES.PDP_MISS", IAP_EVENT_85H_40H) \
__PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.UNCACHED_MEM", IAP_EVENT_B0H_20H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H) \
__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H) \
__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", \
IAP_EVENT_B3H_02H) \
__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H) \
__PMC_EV_ALIAS("PIC_ACCESSES.TPR_READS", IAP_EVENT_BAH_01H) \
__PMC_EV_ALIAS("PIC_ACCESSES.TPR_WRITES", IAP_EVENT_BAH_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.FUSION_ASSIST", IAP_EVENT_C3H_10H) \
__PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_01H) \
Update PMC events from October 2011 Intel documentation. Submitted by: Davide Italiano <davide.italiano@gmail.com> MFC after: 3 days
2012-01-04 07:58:36 +00:00
__PMC_EV_ALIAS("BPU_CLEARS.ANY", IAP_EVENT_E8H_03H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("L2_HW_PREFETCH.HIT", IAP_EVENT_F3H_01H) \
__PMC_EV_ALIAS("L2_HW_PREFETCH.ALLOC", IAP_EVENT_F3H_02H) \
__PMC_EV_ALIAS("L2_HW_PREFETCH.DATA_TRIGGER", IAP_EVENT_F3H_04H) \
__PMC_EV_ALIAS("L2_HW_PREFETCH.CODE_TRIGGER", IAP_EVENT_F3H_08H) \
__PMC_EV_ALIAS("L2_HW_PREFETCH.DCA_TRIGGER", IAP_EVENT_F3H_10H) \
__PMC_EV_ALIAS("L2_HW_PREFETCH.KICK_START", IAP_EVENT_F3H_20H) \
__PMC_EV_ALIAS("SQ_MISC.PROMOTION", IAP_EVENT_F4H_01H) \
__PMC_EV_ALIAS("SQ_MISC.PROMOTION_POST_GO", IAP_EVENT_F4H_02H) \
__PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H) \
__PMC_EV_ALIAS("SQ_MISC.FILL_DROPPED", IAP_EVENT_F4H_08H) \
__PMC_EV_ALIAS("SEGMENT_REG_LOADS", IAP_EVENT_F8H_01H)
/*
* Aliases for Core i7 and Xeon 5500 PMC events (253669-033US December 2009)
- Add support for nehalem/corei7 cpus. This supports all of the core counters defined in the reference manual. It does not support the 'uncore' events. Reviewed by: jkoshy Sponsored by: Nokia
2009-01-27 07:29:37 +00:00
*/
#define __PMC_EV_ALIAS_COREI7() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("SB_DRAIN.ANY", IAP_EVENT_04H_07H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H) \
__PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H) \
__PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
IAP_EVENT_08H_80H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H) \
__PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H) \
__PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD", \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
IAP_EVENT_0BH_10H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN", \
IAP_EVENT_0FH_01H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", \
IAP_EVENT_0FH_02H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", \
IAP_EVENT_0FH_08H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM", \
IAP_EVENT_0FH_10H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_20H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", \
IAP_EVENT_10H_40H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", \
IAP_EVENT_10H_80H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H) \
__PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H) \
__PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H) \
__PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H) \
__PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H) \
__PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H) \
__PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H) \
__PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \
__PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H) \
__PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H) \
__PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H) \
__PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H) \
__PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H) \
__PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H) \
__PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \
__PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH) \
__PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H) \
__PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H) \
__PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H) \
__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H) \
__PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H) \
__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH) \
__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH) \
__PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H) \
__PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H) \
__PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H) \
__PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH) \
__PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H) \
__PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H) \
__PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H) \
__PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H) \
__PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H) \
__PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH) \
__PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("L1D_CACHE_LD.I_STATE", IAP_EVENT_40H_01H) \
__PMC_EV_ALIAS("L1D_CACHE_LD.S_STATE", IAP_EVENT_40H_02H) \
__PMC_EV_ALIAS("L1D_CACHE_LD.E_STATE", IAP_EVENT_40H_04H) \
__PMC_EV_ALIAS("L1D_CACHE_LD.M_STATE", IAP_EVENT_40H_08H) \
__PMC_EV_ALIAS("L1D_CACHE_LD.MESI", IAP_EVENT_40H_0FH) \
__PMC_EV_ALIAS("L1D_CACHE_ST.S_STATE", IAP_EVENT_41H_02H) \
__PMC_EV_ALIAS("L1D_CACHE_ST.E_STATE", IAP_EVENT_41H_04H) \
__PMC_EV_ALIAS("L1D_CACHE_ST.M_STATE", IAP_EVENT_41H_08H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK.HIT", IAP_EVENT_42H_01H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK.S_STATE", IAP_EVENT_42H_02H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK.E_STATE", IAP_EVENT_42H_04H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK.M_STATE", IAP_EVENT_42H_08H) \
__PMC_EV_ALIAS("L1D_ALL_REF.ANY", IAP_EVENT_43H_01H) \
__PMC_EV_ALIAS("L1D_ALL_REF.CACHEABLE", IAP_EVENT_43H_02H) \
__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \
Update PMC events from October 2011 Intel documentation. Submitted by: Davide Italiano <davide.italiano@gmail.com> MFC after: 3 days
2012-01-04 07:58:36 +00:00
__PMC_EV_ALIAS("DTLB_MISSES.PDE_MISS", IAP_EVENT_49H_20H) \
__PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H) \
__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H) \
__PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H) \
__PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H) \
__PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H) \
__PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H) \
__PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H) \
__PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H) \
__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H) \
__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H) \
__PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H) \
__PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H) \
__PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H) \
__PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H) \
__PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H) \
__PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H) \
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
__PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H) \
__PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH) \
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \
__PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
__PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H) \
__PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH) \
__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \
__PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H) \
__PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H) \
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
__PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", \
IAP_EVENT_B1H_1FH) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H) \
__PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H) \
__PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \
__PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H) \
__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", \
IAP_EVENT_CBH_08H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H) \
__PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H) \
__PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H) \
__PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H) \
__PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H) \
__PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H) \
__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H) \
__PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H) \
__PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H) \
__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \
__PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H) \
__PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H) \
__PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H) \
__PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H) \
__PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H) \
__PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH) \
__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) \
__PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H) \
__PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H) \
__PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H) \
__PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H) \
__PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \
__PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H) \
__PMC_EV_ALIAS_COREI7_OLD()
/*
* Aliases for Westmere PMC events (253669-033US December 2009)
*/
#define __PMC_EV_ALIAS_WESTMERE() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("SB_DRAIN.ANY", IAP_EVENT_04H_07H) \
__PMC_EV_ALIAS("MISALIGN_MEMORY.STORE", IAP_EVENT_05H_02H) \
__PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H) \
__PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H) \
__PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_CYCLES", IAP_EVENT_08H_04H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H) \
__PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H) \
__PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H) \
__PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD", \
IAP_EVENT_0BH_10H) \
__PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_HITM", IAP_EVENT_0FH_02H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", \
IAP_EVENT_0FH_08H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_10H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM", IAP_EVENT_0FH_20H) \
__PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
IAP_EVENT_10H_40H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", \
IAP_EVENT_10H_80H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H) \
__PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H) \
__PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H) \
__PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H) \
__PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H) \
__PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H) \
__PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H) \
__PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H) \
__PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \
__PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H) \
__PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H) \
__PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H) \
__PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H) \
__PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H) \
__PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H) \
__PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \
__PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH) \
__PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H) \
__PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H) \
__PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H) \
__PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H) \
__PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H) \
__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH) \
__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H) \
__PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH) \
__PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H) \
__PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H) \
__PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H) \
__PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH) \
__PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H) \
__PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H) \
__PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H) \
__PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H) \
__PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H) \
__PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H) \
__PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH) \
__PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_02H) \
__PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_01H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_MISSES.WALK_CYCLES", IAP_EVENT_49H_04H) \
__PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H) \
__PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H) \
__PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H) \
__PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H) \
__PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \
__PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H) \
__PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H) \
__PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H) \
__PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H) \
__PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", \
IAP_EVENT_60H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", \
IAP_EVENT_60H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H) \
__PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H) \
__PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H) \
__PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H) \
__PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H) \
__PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H) \
__PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H) \
__PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H) \
__PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H) \
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
__PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H) \
__PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH) \
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \
__PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
__PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H) \
__PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH) \
__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \
__PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H) \
__PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H) \
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
__PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H) \
- Fix a typo OFFCORE_REQUESTS.ANY.RFO is B0H10H and not 80H10H. - Enable missing PARTIAL_ADDRESS_ALIAS for Core i7. MFC after: 3 days
2010-04-15 19:45:03 +00:00
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", \
IAP_EVENT_B1H_1FH) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H) \
__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H) \
__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", \
IAP_EVENT_B3H_02H) \
__PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H) \
__PMC_EV_ALIAS("SNOOPQ_REQUESTS.CODE", IAP_EVENT_B4H_01H) \
__PMC_EV_ALIAS("SNOOPQ_REQUESTS.DATA", IAP_EVENT_B4H_02H) \
__PMC_EV_ALIAS("SNOOPQ_REQUESTS.INVALIDATE", IAP_EVENT_B4H_04H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H) \
__PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H) \
__PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \
__PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.ANY_P", IAP_EVENT_C4H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.ANY_P", IAP_EVENT_C5H_00H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \
__PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H) \
__PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", \
IAP_EVENT_CBH_08H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H) \
__PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H) \
__PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H) \
__PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H) \
__PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H) \
__PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H) \
__PMC_EV_ALIAS("UOPS_DECODED.STALL_CYCLES", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H) \
__PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \
__PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H) \
__PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H) \
__PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H) \
__PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \
__PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H) \
__PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H) \
__PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H) \
__PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H) \
__PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H) \
__PMC_EV_ALIAS("THREAD_ACTIVE", IAP_EVENT_ECH_01H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H) \
__PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH) \
__PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H) \
__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) \
__PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H) \
__PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H) \
__PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H) \
__PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H) \
__PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \
__PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \
__PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H)
- Add support for nehalem/corei7 cpus. This supports all of the core counters defined in the reference manual. It does not support the 'uncore' events. Reviewed by: jkoshy Sponsored by: Nokia
2009-01-27 07:29:37 +00:00
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
/*
* Aliases for Haswell core PMC events
*/
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
#define __PMC_EV_ALIAS_HASWELL_XEON() \
Support architectural events on Haswell/Ivy Bridge Differential Revision: https://reviews.freebsd.org/D1589 MFC after: 1 month Sponsored by: Sandvine Inc
2015-03-10 01:24:02 +00:00
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \
Fix various bugs in Haswell counter definitions 1) The "WALK_COMPLETED_2M_4M" event incorrectly referenced 4K pages. 2) The umask for RING0 and RING123 events was reversed. Differential Revision: https://reviews.freebsd.org/D1585 MFC after: 1 month Sponsored by: Sandvine Inc
2015-03-10 01:23:34 +00:00
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
IAP_EVENT_08H_04H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_2M", IAP_EVENT_08H_40H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_60H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_CACHE_MISS", IAP_EVENT_08H_80H) \
__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_E7H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \
__PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \
__PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \
__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \
__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \
__PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \
IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \
IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", \
IAP_EVENT_49H_04H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_2M", IAP_EVENT_49H_40H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_60H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.PDE_CACHE_MISS", IAP_EVENT_49H_80H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \
IAP_EVENT_58H_04H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \
IAP_EVENT_58H_08H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \
Fix various bugs in Haswell counter definitions 1) The "WALK_COMPLETED_2M_4M" event incorrectly referenced 4K pages. 2) The umask for RING0 and RING123 events was reversed. Differential Revision: https://reviews.freebsd.org/D1585 MFC after: 1 month Sponsored by: Sandvine Inc
2015-03-10 01:23:34 +00:00
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
IAP_EVENT_60H_01H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
IAP_EVENT_60H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \
IAP_EVENT_63H_01H) \
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \
__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("TLB_MISSES.WALK_COMPLETED_2M_4M", IAP_EVENT_85H_04H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_2M", IAP_EVENT_85H_40H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_60H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_88H_84H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_89H_84H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_PENDING", IAP_EVENT_A3H_05H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L1D_PENDING", IAP_EVENT_A3H_0CH) \
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_MEMORY", IAP_EVENT_BCH_28H) \
__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
style(9) cleanup
2015-01-22 03:56:23 +00:00
__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV_ALIAS("BR_MISP_U_RETIRED.CONDITIONAL", IAP_EVENT_C5H_04H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_TAKEN", IAP_EVENT_C5H_20H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
Fix Ivy Bridge+ MEM_UOPS_RETIRED counters The MEM_UOPS_RETIRED actually work the same way as the Sandy Bridge counters, but the counters were documented in a different way and that seemed to cause the Ivy Bridge counters to be implemented incorrectly. Use the same counter definitions as Sandy Bridge. While I'm here, rename the counters to match what's documented in the datasheet. Differential Revision: https://reviews.freebsd.org/D1590 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:24:08 +00:00
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \
IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \
IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \
IAP_EVENT_D2H_0FH) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \
IAP_EVENT_D3H_01H) \
__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \
__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \
__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_06H)
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
#define __PMC_EV_ALIAS_HASWELL() \
Support architectural events on Haswell/Ivy Bridge Differential Revision: https://reviews.freebsd.org/D1589 MFC after: 1 month Sponsored by: Sandvine Inc
2015-03-10 01:24:02 +00:00
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \
Fix various bugs in Haswell counter definitions 1) The "WALK_COMPLETED_2M_4M" event incorrectly referenced 4K pages. 2) The umask for RING0 and RING123 events was reversed. Differential Revision: https://reviews.freebsd.org/D1585 MFC after: 1 month Sponsored by: Sandvine Inc
2015-03-10 01:23:34 +00:00
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
IAP_EVENT_08H_04H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_2M", IAP_EVENT_08H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_60H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_CACHE_MISS", IAP_EVENT_08H_80H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_E7H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \
__PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \
__PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \
__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \
__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \
__PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \
IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \
IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", \
IAP_EVENT_49H_04H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_2M", IAP_EVENT_49H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_60H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("DTLB_STORE_MISSES.PDE_CACHE_MISS", IAP_EVENT_49H_80H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \
IAP_EVENT_58H_04H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \
IAP_EVENT_58H_08H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \
Fix various bugs in Haswell counter definitions 1) The "WALK_COMPLETED_2M_4M" event incorrectly referenced 4K pages. 2) The umask for RING0 and RING123 events was reversed. Differential Revision: https://reviews.freebsd.org/D1585 MFC after: 1 month Sponsored by: Sandvine Inc
2015-03-10 01:23:34 +00:00
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
IAP_EVENT_60H_01H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
IAP_EVENT_60H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \
IAP_EVENT_63H_01H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \
__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("TLB_MISSES.WALK_COMPLETED_2M_4M", IAP_EVENT_85H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_2M", IAP_EVENT_85H_40H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_60H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_88H_84H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_89H_84H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_PENDING", IAP_EVENT_A3H_05H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L1D_PENDING", IAP_EVENT_A3H_0CH) \
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \
__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_MEMORY", IAP_EVENT_BCH_28H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
style(9) cleanup
2015-01-22 03:56:23 +00:00
__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV_ALIAS("BR_MISP_U_RETIRED.CONDITIONAL", IAP_EVENT_C5H_04H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_TAKEN", IAP_EVENT_C5H_20H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
Fix Ivy Bridge+ MEM_UOPS_RETIRED counters The MEM_UOPS_RETIRED actually work the same way as the Sandy Bridge counters, but the counters were documented in a different way and that seemed to cause the Ivy Bridge counters to be implemented incorrectly. Use the same counter definitions as Sandy Bridge. While I'm here, rename the counters to match what's documented in the datasheet. Differential Revision: https://reviews.freebsd.org/D1590 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:24:08 +00:00
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \
IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \
IAP_EVENT_D2H_08H) \
Add in missing events for Sandy Bridge Xeon. * Add in MEM_LOAD_UOPS_LLC_HIT_RETIRED for both sandy bridge and sandy bridge Xeon. Right now it only is enabled for Sandy Bridge. * D2/0F is actually a combination rather than a separate counter, so just flip that on for the CPU types that support it. There's an errata for using this on SB Xeon hardware - I've documented it in kern/181346. Tested: * Sandy Bridge * Sandy Bridge Xeon Sponsored by: Netflix, Inc.
2013-08-18 06:08:52 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \
IAP_EVENT_D2H_0FH) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \
IAP_EVENT_D3H_01H) \
__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \
__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \
__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_06H)
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
#define __PMC_EV_ALIAS_IVYBRIDGE() \
Support architectural events on Haswell/Ivy Bridge Differential Revision: https://reviews.freebsd.org/D1589 MFC after: 1 month Sponsored by: Sandvine Inc
2015-03-10 01:24:02 +00:00
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_81H)\
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_82H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_84H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_PG_WALK_DURATION", \
IAP_EVENT_08H_88H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \
IAP_EVENT_10H_10H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \
IAP_EVENT_10H_20H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \
__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \
__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \
IAP_EVENT_49H_01H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \
IAP_EVENT_58H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", \
IAP_EVENT_58H_02H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_04H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_ELIMINATED", IAP_EVENT_58H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_5FH_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
IAP_EVENT_60H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \
IAP_EVENT_60H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \
IAP_EVENT_63H_01H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \
__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("ICACHE.IFETCH_STALL", IAP_EVENT_80H_04H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_88H_84H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_89H_84H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", IAP_EVENT_A3H_04H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("OTHER_ASSISTS.WB", IAP_EVENT_C1H_80H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \
Fix Ivy Bridge+ MEM_UOPS_RETIRED counters The MEM_UOPS_RETIRED actually work the same way as the Sandy Bridge counters, but the counters were documented in a different way and that seemed to cause the Ivy Bridge counters to be implemented incorrectly. Use the same counter definitions as Sandy Bridge. While I'm here, rename the counters to match what's documented in the datasheet. Differential Revision: https://reviews.freebsd.org/D1590 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:24:08 +00:00
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \
IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \
IAP_EVENT_D2H_08H) \
Add in missing events for Sandy Bridge Xeon. * Add in MEM_LOAD_UOPS_LLC_HIT_RETIRED for both sandy bridge and sandy bridge Xeon. Right now it only is enabled for Sandy Bridge. * D2/0F is actually a combination rather than a separate counter, so just flip that on for the CPU types that support it. There's an errata for using this on SB Xeon hardware - I've documented it in kern/181346. Tested: * Sandy Bridge * Sandy Bridge Xeon Sponsored by: Netflix, Inc.
2013-08-18 06:08:52 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \
IAP_EVENT_D2H_0FH) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \
IAP_EVENT_D3H_01H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \
__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H)
Update hwpmc to support the Xeon class of Ivybridge processors. case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-01-31 22:09:53 +00:00
/*
* Aliases for Ivy Bridge Xeon PMC events (325462-045US January 2013)
*/
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
#define __PMC_EV_ALIAS_IVYBRIDGE_XEON() \
Support architectural events on Haswell/Ivy Bridge Differential Revision: https://reviews.freebsd.org/D1589 MFC after: 1 month Sponsored by: Sandvine Inc
2015-03-10 01:24:02 +00:00
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_81H)\
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_82H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_84H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_PG_WALK_DURATION", \
IAP_EVENT_08H_88H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \
__PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \
IAP_EVENT_10H_10H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \
IAP_EVENT_10H_20H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \
__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \
__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \
IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", IAP_EVENT_58H_01H)\
__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", \
IAP_EVENT_58H_02H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_04H) \
__PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_ELIMINATED", IAP_EVENT_58H_08H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_5FH_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
IAP_EVENT_60H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \
IAP_EVENT_60H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \
IAP_EVENT_63H_01H) \
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \
__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \
__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("ICACHE.IFETCH_STALL", IAP_EVENT_80H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_88H_84H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_89H_84H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", IAP_EVENT_A3H_04H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \
__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \
__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("OTHER_ASSISTS.WB", IAP_EVENT_C1H_80H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
__PMC_EV_ALIAS("BR_MISP_U_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \
Fix Ivy Bridge+ MEM_UOPS_RETIRED counters The MEM_UOPS_RETIRED actually work the same way as the Sandy Bridge counters, but the counters were documented in a different way and that seemed to cause the Ivy Bridge counters to be implemented incorrectly. Use the same counter definitions as Sandy Bridge. While I'm here, rename the counters to match what's documented in the datasheet. Differential Revision: https://reviews.freebsd.org/D1590 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:24:08 +00:00
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \
IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \
IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \
IAP_EVENT_D3H_01H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \
IAP_EVENT_D3H_03H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
IAP_EVENT_D3H_0CH) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", \
IAP_EVENT_D3H_10H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", \
IAP_EVENT_D3H_20H) \
__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \
__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \
__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \
Update hwpmc to support the Xeon class of Ivybridge processors. case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-01-31 22:09:53 +00:00
__PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH)
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
/*
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
* Aliases for Sandy Bridge PMC events (253669-039US May 2011)
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
*/
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
#define __PMC_EV_ALIAS_SANDYBRIDGE() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H) \
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
__PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \
__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \
__PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H) \
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \
IAP_EVENT_10H_10H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \
IAP_EVENT_10H_20H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \
__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \
__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \
__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \
__PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \
IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \
__PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H) \
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H) \
__PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H) \
__PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H) \
__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H) \
__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H) \
__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH) \
__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH) \
__PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H) \
__PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH) \
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
IAP_EVENT_60H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \
IAP_EVENT_63H_01H) \
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \
Correct a typo in the event mask mnemonic. Reviewed by: gnn MFC after: 3 days
2013-08-20 14:59:31 +00:00
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_88H_84H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_89H_84H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \
__PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H) \
__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \
__PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH) \
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \
__PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \
__PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \
Update the mis-predicted branch PMC names (for sandy bridge) to not clash. The SDM (June 2013) tables on these are rather confusing. Yes, they assign the same name (BR_MISP_RETIRED.ALL_BRANCHES) to two codes (C5H/00H and C5H/04H.) The latter however is the PEBS version. So, to make it easier to see the difference - and yes, we can use both without having to actually enable the PEBS specific bits! - just rename the PEBS one to _PS so there's no clashing. Tested: * Sandy bridge
2013-08-25 12:58:34 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES_PS", IAP_EVENT_C5H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \
Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandy bridge Xeon. Summary: These are PEBS events but they're also available as normal counter/sample events. The source table (Table 19-2) lists the base versions (LOAD, STLB_MISS, SPLIT, ALL) but it says they must be qualified with other values. This particular commit fleshes out those umask values. Source: * Linux; SDM June 2013, Volume 3B, Table 19-2 and 18-21. Tested: * Sandy Bridge (non-Xeon)
2013-08-25 02:07:28 +00:00
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \
IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \
IAP_EVENT_D2H_08H) \
Change the name of this particular event to reflect the name used in Linux and Intel examples. Sourced: * https://github.com/andikleen/pmu-tools/blob/master/snb-client.csv * http://software.intel.com/en-us/comment/1747932#comment-1747932 Note: * It's not currently in the Intel SDM; I need to chase down what's going on. Tested: * Sandy Bridge
2013-08-21 21:47:56 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
IAP_EVENT_D4H_02H) \
__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \
__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) \
__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H)
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
Update hwpmc to support the Xeon class of Sandybridge processors. (Model 0x2D /* Per Intel document 253669-044US 08/2012. */) Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ fabient@ Obtained from: Yahoo! Inc. MFC after: 2 weeks
2012-10-19 17:01:27 +00:00
/*
* Aliases for Sandy Bridge Xeon PMC events (253669-044US August 2012)
*/
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
#define __PMC_EV_ALIAS_SANDYBRIDGE_XEON() \
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
__PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H) \
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
__PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H) \
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \
__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \
__PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H) \
__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \
IAP_EVENT_10H_10H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \
IAP_EVENT_10H_20H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \
__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \
__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \
__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \
__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \
__PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \
__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \
__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \
__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \
__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \
__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_S", IAP_EVENT_28H_02H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \
__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \
__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \
__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \
__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \
__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \
IAP_EVENT_49H_01H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \
__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \
__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \
__PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H) \
__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \
__PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H) \
__PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H) \
__PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H) \
__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H) \
__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H) \
__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH) \
__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH) \
__PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H) \
__PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH) \
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
IAP_EVENT_60H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \
IAP_EVENT_60H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \
IAP_EVENT_60H_08H) \
__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \
IAP_EVENT_63H_01H) \
__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \
__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \
__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \
__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \
__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \
__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \
__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \
__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \
__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_88H_84H) \
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
Fix Sandy Bridge+ hwpmc branch counters On Sandy Bridge and later, to count branch-related events you have to or together a mask indicating the type of branch instruction to count (e.g. direct jump, branch, etc) and a bits indicating whether to count taken and not-taken branches. The current counter definitions where defining this bits individually, so the counters never worked and always just counted 0. Fix the counter definitions to instead contain the proper combination of masks. Also update the man pages to reflect the new counters. Differential Revision: https://reviews.freebsd.org/D1587 MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-10 01:23:47 +00:00
IAP_EVENT_89H_84H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_02H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \
__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_02H) \
__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", IAP_EVENT_A3H_04H) \
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
2015-01-14 12:46:58 +00:00
__PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \
__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \
__PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H) \
__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \
__PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH) \
__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H) \
__PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H) \
__PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \
__PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \
__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \
__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \
__PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H) \
__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \
__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \
__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \
__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \
__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \
__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \
__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \
Update the mis-predicted branch PMC names (for sandy bridge) to not clash. The SDM (June 2013) tables on these are rather confusing. Yes, they assign the same name (BR_MISP_RETIRED.ALL_BRANCHES) to two codes (C5H/00H and C5H/04H.) The latter however is the PEBS version. So, to make it easier to see the difference - and yes, we can use both without having to actually enable the PEBS specific bits! - just rename the PEBS one to _PS so there's no clashing. Tested: * Sandy bridge
2013-08-25 12:58:34 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES_PS", IAP_EVENT_C5H_04H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \
__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \
__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \
__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \
Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandy bridge Xeon. Summary: These are PEBS events but they're also available as normal counter/sample events. The source table (Table 19-2) lists the base versions (LOAD, STLB_MISS, SPLIT, ALL) but it says they must be qualified with other values. This particular commit fleshes out those umask values. Source: * Linux; SDM June 2013, Volume 3B, Table 19-2 and 18-21. Tested: * Sandy Bridge (non-Xeon)
2013-08-25 02:07:28 +00:00
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \
Add in missing events for Sandy Bridge Xeon. * Add in MEM_LOAD_UOPS_LLC_HIT_RETIRED for both sandy bridge and sandy bridge Xeon. Right now it only is enabled for Sandy Bridge. * D2/0F is actually a combination rather than a separate counter, so just flip that on for the CPU types that support it. There's an errata for using this on SB Xeon hardware - I've documented it in kern/181346. Tested: * Sandy Bridge * Sandy Bridge Xeon Sponsored by: Netflix, Inc.
2013-08-18 06:08:52 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \
IAP_EVENT_D2H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \
IAP_EVENT_D2H_02H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \
IAP_EVENT_D2H_04H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \
IAP_EVENT_D2H_08H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \
IAP_EVENT_D2H_0FH) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \
IAP_EVENT_D3H_01H) \
__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", \
IAP_EVENT_D3H_04H) \
Remove the duplicate LLC_MISS event and put it in the right order.
2013-08-29 13:52:51 +00:00
__PMC_EV_ALIAS("MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", \
IAP_EVENT_D4H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_01H) \
__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \
__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \
__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \
__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \
__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \
__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \
__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \
__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \
__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \
__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \
__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \
__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \
__PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) \
Update hwpmc to support the Xeon class of Sandybridge processors. (Model 0x2D /* Per Intel document 253669-044US 08/2012. */) Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ fabient@ Obtained from: Yahoo! Inc. MFC after: 2 weeks
2012-10-19 17:01:27 +00:00
__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H)
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
/* timestamp counters. */
#define __PMC_EV_TSC() \
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
__PMC_EV(TSC, TSC)
#define PMC_EV_TSC_FIRST PMC_EV_TSC_TSC
#define PMC_EV_TSC_LAST PMC_EV_TSC_TSC
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
Add software PMC support. New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
2012-03-28 20:58:30 +00:00
/*
sys/dev: minor spelling fixes. Most affect comments, very few have user-visible effects.
2016-05-03 03:41:25 +00:00
* Software events are dynamically defined.
Add software PMC support. New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
2012-03-28 20:58:30 +00:00
*/
#define PMC_EV_DYN_COUNT 0x1000
#define PMC_EV_SOFT_FIRST 0x20000
#define PMC_EV_SOFT_LAST (PMC_EV_SOFT_FIRST + PMC_EV_DYN_COUNT - 1)
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
#define __PMC_EV_UCF() \
__PMC_EV(UCF, UCLOCK)
#define PMC_EV_UCF_FIRST PMC_EV_UCF_UCLOCK
#define PMC_EV_UCF_LAST PMC_EV_UCF_UCLOCK
#define __PMC_EV_UCP() \
__PMC_EV(UCP, EVENT_00H_01H) \
__PMC_EV(UCP, EVENT_00H_02H) \
__PMC_EV(UCP, EVENT_00H_04H) \
__PMC_EV(UCP, EVENT_01H_01H) \
__PMC_EV(UCP, EVENT_01H_02H) \
__PMC_EV(UCP, EVENT_01H_04H) \
__PMC_EV(UCP, EVENT_02H_01H) \
__PMC_EV(UCP, EVENT_03H_01H) \
__PMC_EV(UCP, EVENT_03H_02H) \
__PMC_EV(UCP, EVENT_03H_04H) \
__PMC_EV(UCP, EVENT_03H_08H) \
__PMC_EV(UCP, EVENT_03H_10H) \
__PMC_EV(UCP, EVENT_03H_20H) \
__PMC_EV(UCP, EVENT_03H_40H) \
__PMC_EV(UCP, EVENT_04H_01H) \
__PMC_EV(UCP, EVENT_04H_02H) \
__PMC_EV(UCP, EVENT_04H_04H) \
__PMC_EV(UCP, EVENT_04H_08H) \
__PMC_EV(UCP, EVENT_04H_10H) \
__PMC_EV(UCP, EVENT_05H_01H) \
__PMC_EV(UCP, EVENT_05H_02H) \
__PMC_EV(UCP, EVENT_05H_04H) \
__PMC_EV(UCP, EVENT_06H_01H) \
__PMC_EV(UCP, EVENT_06H_02H) \
__PMC_EV(UCP, EVENT_06H_04H) \
__PMC_EV(UCP, EVENT_06H_08H) \
__PMC_EV(UCP, EVENT_06H_10H) \
__PMC_EV(UCP, EVENT_06H_20H) \
__PMC_EV(UCP, EVENT_07H_01H) \
__PMC_EV(UCP, EVENT_07H_02H) \
__PMC_EV(UCP, EVENT_07H_04H) \
__PMC_EV(UCP, EVENT_07H_08H) \
__PMC_EV(UCP, EVENT_07H_10H) \
__PMC_EV(UCP, EVENT_07H_20H) \
__PMC_EV(UCP, EVENT_07H_24H) \
__PMC_EV(UCP, EVENT_08H_01H) \
__PMC_EV(UCP, EVENT_08H_02H) \
__PMC_EV(UCP, EVENT_08H_04H) \
__PMC_EV(UCP, EVENT_08H_03H) \
__PMC_EV(UCP, EVENT_09H_01H) \
__PMC_EV(UCP, EVENT_09H_02H) \
__PMC_EV(UCP, EVENT_09H_04H) \
__PMC_EV(UCP, EVENT_09H_03H) \
__PMC_EV(UCP, EVENT_0AH_01H) \
__PMC_EV(UCP, EVENT_0AH_02H) \
__PMC_EV(UCP, EVENT_0AH_04H) \
__PMC_EV(UCP, EVENT_0AH_08H) \
__PMC_EV(UCP, EVENT_0AH_0FH) \
__PMC_EV(UCP, EVENT_0BH_01H) \
__PMC_EV(UCP, EVENT_0BH_02H) \
__PMC_EV(UCP, EVENT_0BH_04H) \
__PMC_EV(UCP, EVENT_0BH_08H) \
__PMC_EV(UCP, EVENT_0BH_10H) \
__PMC_EV(UCP, EVENT_0BH_1FH) \
__PMC_EV(UCP, EVENT_0CH_01H) \
__PMC_EV(UCP, EVENT_0CH_02H) \
Add missing MSR programming for some events. Submitted by: Davide Italiano <davide.italiano@gmail.com> MFC after: 3 days
2012-01-04 07:33:06 +00:00
__PMC_EV(UCP, EVENT_0CH_04H_E) \
__PMC_EV(UCP, EVENT_0CH_04H_F) \
__PMC_EV(UCP, EVENT_0CH_04H_M) \
__PMC_EV(UCP, EVENT_0CH_04H_S) \
__PMC_EV(UCP, EVENT_0CH_08H_E) \
__PMC_EV(UCP, EVENT_0CH_08H_F) \
__PMC_EV(UCP, EVENT_0CH_08H_M) \
__PMC_EV(UCP, EVENT_0CH_08H_S) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(UCP, EVENT_20H_01H) \
__PMC_EV(UCP, EVENT_20H_02H) \
__PMC_EV(UCP, EVENT_20H_04H) \
__PMC_EV(UCP, EVENT_20H_08H) \
__PMC_EV(UCP, EVENT_20H_10H) \
__PMC_EV(UCP, EVENT_20H_20H) \
__PMC_EV(UCP, EVENT_21H_01H) \
__PMC_EV(UCP, EVENT_21H_02H) \
__PMC_EV(UCP, EVENT_21H_04H) \
__PMC_EV(UCP, EVENT_22H_01H) \
__PMC_EV(UCP, EVENT_22H_02H) \
__PMC_EV(UCP, EVENT_22H_04H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(UCP, EVENT_22H_08H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(UCP, EVENT_22H_10H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(UCP, EVENT_22H_20H) \
__PMC_EV(UCP, EVENT_22H_40H) \
__PMC_EV(UCP, EVENT_22H_80H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(UCP, EVENT_23H_01H) \
__PMC_EV(UCP, EVENT_23H_02H) \
__PMC_EV(UCP, EVENT_23H_04H) \
__PMC_EV(UCP, EVENT_24H_02H) \
__PMC_EV(UCP, EVENT_24H_04H) \
__PMC_EV(UCP, EVENT_25H_01H) \
__PMC_EV(UCP, EVENT_25H_02H) \
__PMC_EV(UCP, EVENT_25H_04H) \
__PMC_EV(UCP, EVENT_26H_01H) \
__PMC_EV(UCP, EVENT_27H_01H) \
__PMC_EV(UCP, EVENT_27H_02H) \
__PMC_EV(UCP, EVENT_27H_04H) \
__PMC_EV(UCP, EVENT_27H_08H) \
__PMC_EV(UCP, EVENT_27H_10H) \
__PMC_EV(UCP, EVENT_27H_20H) \
__PMC_EV(UCP, EVENT_28H_01H) \
__PMC_EV(UCP, EVENT_28H_02H) \
__PMC_EV(UCP, EVENT_28H_04H) \
__PMC_EV(UCP, EVENT_28H_08H) \
__PMC_EV(UCP, EVENT_28H_10H) \
__PMC_EV(UCP, EVENT_28H_20H) \
__PMC_EV(UCP, EVENT_29H_01H) \
__PMC_EV(UCP, EVENT_29H_02H) \
__PMC_EV(UCP, EVENT_29H_04H) \
__PMC_EV(UCP, EVENT_29H_08H) \
__PMC_EV(UCP, EVENT_29H_10H) \
__PMC_EV(UCP, EVENT_29H_20H) \
__PMC_EV(UCP, EVENT_2AH_01H) \
__PMC_EV(UCP, EVENT_2AH_02H) \
__PMC_EV(UCP, EVENT_2AH_04H) \
__PMC_EV(UCP, EVENT_2AH_07H) \
__PMC_EV(UCP, EVENT_2BH_01H) \
__PMC_EV(UCP, EVENT_2BH_02H) \
__PMC_EV(UCP, EVENT_2BH_04H) \
__PMC_EV(UCP, EVENT_2BH_07H) \
__PMC_EV(UCP, EVENT_2CH_01H) \
__PMC_EV(UCP, EVENT_2CH_02H) \
__PMC_EV(UCP, EVENT_2CH_04H) \
__PMC_EV(UCP, EVENT_2CH_07H) \
__PMC_EV(UCP, EVENT_2DH_01H) \
__PMC_EV(UCP, EVENT_2DH_02H) \
__PMC_EV(UCP, EVENT_2DH_04H) \
__PMC_EV(UCP, EVENT_2DH_07H) \
__PMC_EV(UCP, EVENT_2EH_01H) \
__PMC_EV(UCP, EVENT_2EH_02H) \
__PMC_EV(UCP, EVENT_2EH_04H) \
__PMC_EV(UCP, EVENT_2EH_07H) \
__PMC_EV(UCP, EVENT_2FH_01H) \
__PMC_EV(UCP, EVENT_2FH_02H) \
__PMC_EV(UCP, EVENT_2FH_04H) \
__PMC_EV(UCP, EVENT_2FH_07H) \
__PMC_EV(UCP, EVENT_2FH_08H) \
__PMC_EV(UCP, EVENT_2FH_10H) \
__PMC_EV(UCP, EVENT_2FH_20H) \
__PMC_EV(UCP, EVENT_2FH_38H) \
__PMC_EV(UCP, EVENT_30H_01H) \
__PMC_EV(UCP, EVENT_30H_02H) \
__PMC_EV(UCP, EVENT_30H_04H) \
__PMC_EV(UCP, EVENT_30H_07H) \
__PMC_EV(UCP, EVENT_31H_01H) \
__PMC_EV(UCP, EVENT_31H_02H) \
__PMC_EV(UCP, EVENT_31H_04H) \
__PMC_EV(UCP, EVENT_31H_07H) \
__PMC_EV(UCP, EVENT_32H_01H) \
__PMC_EV(UCP, EVENT_32H_02H) \
__PMC_EV(UCP, EVENT_32H_04H) \
__PMC_EV(UCP, EVENT_32H_07H) \
__PMC_EV(UCP, EVENT_33H_01H) \
__PMC_EV(UCP, EVENT_33H_02H) \
__PMC_EV(UCP, EVENT_33H_04H) \
__PMC_EV(UCP, EVENT_33H_07H) \
__PMC_EV(UCP, EVENT_34H_01H) \
__PMC_EV(UCP, EVENT_34H_02H) \
__PMC_EV(UCP, EVENT_34H_04H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV(UCP, EVENT_34H_06H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(UCP, EVENT_34H_08H) \
__PMC_EV(UCP, EVENT_34H_10H) \
__PMC_EV(UCP, EVENT_34H_20H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(UCP, EVENT_34H_40H) \
__PMC_EV(UCP, EVENT_34H_80H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(UCP, EVENT_35H_01H) \
__PMC_EV(UCP, EVENT_35H_02H) \
__PMC_EV(UCP, EVENT_35H_04H) \
__PMC_EV(UCP, EVENT_40H_01H) \
__PMC_EV(UCP, EVENT_40H_02H) \
__PMC_EV(UCP, EVENT_40H_04H) \
__PMC_EV(UCP, EVENT_40H_08H) \
__PMC_EV(UCP, EVENT_40H_10H) \
__PMC_EV(UCP, EVENT_40H_20H) \
__PMC_EV(UCP, EVENT_40H_07H) \
__PMC_EV(UCP, EVENT_40H_38H) \
__PMC_EV(UCP, EVENT_41H_01H) \
__PMC_EV(UCP, EVENT_41H_02H) \
__PMC_EV(UCP, EVENT_41H_04H) \
__PMC_EV(UCP, EVENT_41H_08H) \
__PMC_EV(UCP, EVENT_41H_10H) \
__PMC_EV(UCP, EVENT_41H_20H) \
__PMC_EV(UCP, EVENT_41H_07H) \
__PMC_EV(UCP, EVENT_41H_38H) \
__PMC_EV(UCP, EVENT_42H_01H) \
__PMC_EV(UCP, EVENT_42H_02H) \
__PMC_EV(UCP, EVENT_42H_04H) \
__PMC_EV(UCP, EVENT_42H_08H) \
__PMC_EV(UCP, EVENT_43H_01H) \
__PMC_EV(UCP, EVENT_43H_02H) \
__PMC_EV(UCP, EVENT_60H_01H) \
__PMC_EV(UCP, EVENT_60H_02H) \
__PMC_EV(UCP, EVENT_60H_04H) \
__PMC_EV(UCP, EVENT_61H_01H) \
__PMC_EV(UCP, EVENT_61H_02H) \
__PMC_EV(UCP, EVENT_61H_04H) \
__PMC_EV(UCP, EVENT_62H_01H) \
__PMC_EV(UCP, EVENT_62H_02H) \
__PMC_EV(UCP, EVENT_62H_04H) \
__PMC_EV(UCP, EVENT_63H_01H) \
__PMC_EV(UCP, EVENT_63H_02H) \
__PMC_EV(UCP, EVENT_63H_04H) \
__PMC_EV(UCP, EVENT_63H_08H) \
__PMC_EV(UCP, EVENT_63H_10H) \
__PMC_EV(UCP, EVENT_63H_20H) \
__PMC_EV(UCP, EVENT_64H_01H) \
__PMC_EV(UCP, EVENT_64H_02H) \
__PMC_EV(UCP, EVENT_64H_04H) \
__PMC_EV(UCP, EVENT_64H_08H) \
__PMC_EV(UCP, EVENT_64H_10H) \
__PMC_EV(UCP, EVENT_64H_20H) \
__PMC_EV(UCP, EVENT_65H_01H) \
__PMC_EV(UCP, EVENT_65H_02H) \
__PMC_EV(UCP, EVENT_65H_04H) \
__PMC_EV(UCP, EVENT_66H_01H) \
__PMC_EV(UCP, EVENT_66H_02H) \
__PMC_EV(UCP, EVENT_66H_04H) \
__PMC_EV(UCP, EVENT_67H_01H) \
__PMC_EV(UCP, EVENT_80H_01H) \
__PMC_EV(UCP, EVENT_80H_02H) \
__PMC_EV(UCP, EVENT_80H_04H) \
__PMC_EV(UCP, EVENT_80H_08H) \
__PMC_EV(UCP, EVENT_81H_01H) \
__PMC_EV(UCP, EVENT_81H_02H) \
__PMC_EV(UCP, EVENT_81H_04H) \
__PMC_EV(UCP, EVENT_81H_08H) \
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
__PMC_EV(UCP, EVENT_81H_20H) \
__PMC_EV(UCP, EVENT_81H_80H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV(UCP, EVENT_82H_01H) \
__PMC_EV(UCP, EVENT_83H_01H) \
__PMC_EV(UCP, EVENT_83H_02H) \
__PMC_EV(UCP, EVENT_83H_04H) \
__PMC_EV(UCP, EVENT_83H_08H) \
__PMC_EV(UCP, EVENT_84H_01H) \
__PMC_EV(UCP, EVENT_84H_02H) \
__PMC_EV(UCP, EVENT_84H_04H) \
__PMC_EV(UCP, EVENT_84H_08H) \
__PMC_EV(UCP, EVENT_85H_02H) \
__PMC_EV(UCP, EVENT_86H_01H)
#define PMC_EV_UCP_FIRST PMC_EV_UCP_EVENT_00H_01H
#define PMC_EV_UCP_LAST PMC_EV_UCP_EVENT_86H_01H
hwpmc: add initial Intel Broadwell support. The full list of aliases and events will follow in a subsequent commit. MFC after: 1 month
2015-04-05 05:14:20 +00:00
/*
* Aliases for Broadwell uncore PMC events
*/
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
#define __PMC_EV_ALIAS_BROADWELLUC() \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.MISS", UCP_EVENT_22H_01H) \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL", UCP_EVENT_22H_02H) \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HIT", UCP_EVENT_22H_04H) \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HITM", UCP_EVENT_22H_08H) \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL_M", UCP_EVENT_22H_10H) \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", \
UCP_EVENT_22H_20H) \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", UCP_EVENT_22H_40H) \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", \
UCP_EVENT_22H_80H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ES", UCP_EVENT_34H_06H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.READ_FILTER", UCP_EVENT_34H_10H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", UCP_EVENT_34H_20H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", UCP_EVENT_34H_40H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", \
UCP_EVENT_34H_80H) \
__PMC_EV_ALIAS("UNC_ARB_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \
__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \
__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \
__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \
__PMC_EV_ALIAS("UNC_ARB_COH_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \
__PMC_EV_ALIAS("UNC_ARB_COH_TRK_REQUEST.ALL", UCP_EVENT_84H_01H)
hwpmc: add initial Intel Broadwell support. The full list of aliases and events will follow in a subsequent commit. MFC after: 1 month
2015-04-05 05:14:20 +00:00
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
#define __PMC_EV_ALIAS_COREI7UC() \
__PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \
__PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \
__PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H) \
__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H) \
__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", \
UCP_EVENT_01H_04H) \
__PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H) \
__PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H) \
__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H) \
__PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H) \
__PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H) \
__PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H) \
__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H) \
__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H) \
__PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H) \
__PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H) \
__PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H) \
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H) \
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H) \
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H) \
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H) \
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H)\
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H)\
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H) \
__PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H) \
__PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H) \
__PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H) \
__PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H) \
__PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H) \
__PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H) \
__PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H) \
__PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H) \
__PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H) \
__PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H) \
__PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H) \
__PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH) \
__PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H) \
__PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H) \
__PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H) \
__PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H) \
__PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H) \
__PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH) \
__PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H) \
__PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H) \
__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H) \
__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H) \
__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H) \
__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H) \
__PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H) \
__PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H) \
__PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H) \
__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H) \
__PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H) \
__PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H) \
__PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H) \
__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H) \
__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H) \
__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H) \
__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H) \
__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H) \
__PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H) \
__PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH0", UCP_EVENT_27H_01H) \
__PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH1", UCP_EVENT_27H_02H) \
__PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH2", UCP_EVENT_27H_04H) \
__PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH0", UCP_EVENT_27H_08H) \
__PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH1", UCP_EVENT_27H_10H) \
__PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH2", UCP_EVENT_27H_20H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H) \
__PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H) \
__PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H) \
__PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H) \
__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H) \
__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H) \
__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H) \
__PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H) \
__PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H) \
__PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H) \
__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H) \
__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H) \
__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H) \
__PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H) \
__PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H) \
__PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H) \
__PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H) \
__PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H) \
__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H) \
__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H) \
__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H) \
__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H) \
__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H) \
__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H) \
__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H) \
__PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H) \
__PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H) \
__PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H) \
__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H) \
__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H) \
__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H) \
__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H) \
__PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H) \
__PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H) \
__PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H) \
__PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H) \
__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H) \
__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H) \
__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H) \
__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H) \
__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", \
UCP_EVENT_40H_01H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", \
UCP_EVENT_40H_02H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", \
UCP_EVENT_40H_04H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", \
UCP_EVENT_40H_08H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", \
UCP_EVENT_40H_10H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", \
UCP_EVENT_40H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", \
UCP_EVENT_41H_01H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", \
UCP_EVENT_41H_02H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", \
UCP_EVENT_41H_04H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", \
UCP_EVENT_41H_08H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", \
UCP_EVENT_41H_10H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", \
UCP_EVENT_41H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H) \
__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H) \
__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H) \
__PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H) \
__PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H) \
__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H) \
__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H) \
__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H) \
__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H) \
__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H) \
__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H) \
__PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H) \
__PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H) \
__PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H) \
__PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H) \
__PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H)
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
/*
* Aliases for Haswell uncore PMC events
*/
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
#define __PMC_EV_ALIAS_HASWELLUC() \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.MISS", UCP_EVENT_22H_01H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL", UCP_EVENT_22H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HIT", UCP_EVENT_22H_04H) \
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HITM", UCP_EVENT_22H_08H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL_M", UCP_EVENT_22H_10H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", \
UCP_EVENT_22H_20H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", UCP_EVENT_22H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", \
UCP_EVENT_22H_80H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ES", UCP_EVENT_34H_06H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.READ_FILTER", UCP_EVENT_34H_10H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", UCP_EVENT_34H_20H) \
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", UCP_EVENT_34H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", \
UCP_EVENT_34H_80H) \
__PMC_EV_ALIAS("UNC_ARB_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \
__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \
__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-03-28 19:15:54 +00:00
__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \
__PMC_EV_ALIAS("UNC_ARB_COH_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \
__PMC_EV_ALIAS("UNC_ARB_COH_TRK_REQUEST.ALL", UCP_EVENT_84H_01H)
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
#define __PMC_EV_ALIAS_WESTMEREUC() \
__PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \
__PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \
__PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H) \
__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H) \
__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", \
UCP_EVENT_01H_04H) \
__PMC_EV_ALIAS("GQ_OCCUPANCY.READ_TRACKER", UCP_EVENT_02H_01H) \
__PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H) \
__PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H) \
__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H) \
__PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H) \
__PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H) \
__PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H) \
__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H) \
__PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H) \
__PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H) \
__PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H) \
__PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H) \
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H) \
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H) \
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H) \
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H) \
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H)\
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H)\
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H) \
__PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H) \
__PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H) \
__PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H) \
__PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H) \
__PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H) \
__PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H) \
__PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H) \
__PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H) \
__PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H) \
__PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H) \
__PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H) \
__PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH) \
__PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H) \
__PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H) \
__PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H) \
__PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H) \
__PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H) \
__PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S", UCP_EVENT_0CH_01H) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I", UCP_EVENT_0CH_02H) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_E", UCP_EVENT_0CH_04H_E) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_F", UCP_EVENT_0CH_04H_F) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_M", UCP_EVENT_0CH_04H_M) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_S", UCP_EVENT_0CH_04H_S) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_E", UCP_EVENT_0CH_08H_E) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_F", UCP_EVENT_0CH_08H_F) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_M", UCP_EVENT_0CH_08H_M) \
__PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_S", UCP_EVENT_0CH_08H_S) \
__PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H) \
__PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H) \
__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H) \
__PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H) \
__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H) \
__PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H) \
__PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H) \
__PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H) \
__PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H) \
__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H) \
__PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H) \
__PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H) \
__PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H) \
__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H) \
__PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H) \
__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H) \
__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H) \
__PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H) \
__PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H) \
__PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H) \
__PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H) \
__PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H) \
__PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H) \
__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H) \
__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H) \
__PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H) \
__PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H) \
__PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H) \
__PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H) \
__PMC_EV_ALIAS("QMC_OCCUPANCY.ANY", UCP_EVENT_2AH_07H) \
__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H) \
__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H) \
__PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H) \
__PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H) \
__PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H) \
__PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H) \
__PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H) \
__PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H) \
__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H) \
__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H) \
__PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H) \
__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H) \
__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H) \
__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H) \
__PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H) \
__PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H) \
__PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H) \
__PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H) \
__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H) \
__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H) \
__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H) \
__PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H) \
__PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H) \
__PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H) \
__PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H) \
__PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H) \
__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H) \
__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H) \
__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H) \
__PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H) \
__PMC_EV_ALIAS("IMC_RETRY.CH0", UCP_EVENT_32H_01H) \
__PMC_EV_ALIAS("IMC_RETRY.CH1", UCP_EVENT_32H_02H) \
__PMC_EV_ALIAS("IMC_RETRY.CH2", UCP_EVENT_32H_04H) \
__PMC_EV_ALIAS("IMC_RETRY.ANY", UCP_EVENT_32H_07H) \
__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.IOH", UCP_EVENT_33H_01H) \
__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.REMOTE", UCP_EVENT_33H_02H) \
__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H) \
__PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.ANY", UCP_EVENT_33H_07H) \
__PMC_EV_ALIAS("QHL_SLEEPS.IOH_ORDER", UCP_EVENT_34H_01H) \
__PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_ORDER", UCP_EVENT_34H_02H) \
__PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_ORDER", UCP_EVENT_34H_04H) \
__PMC_EV_ALIAS("QHL_SLEEPS.IOH_CONFLICT", UCP_EVENT_34H_08H) \
__PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_CONFLICT", UCP_EVENT_34H_10H) \
__PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_CONFLICT", UCP_EVENT_34H_20H) \
__PMC_EV_ALIAS("ADDR_OPCODE_MATCH.IOH", UCP_EVENT_35H_01H) \
__PMC_EV_ALIAS("ADDR_OPCODE_MATCH.REMOTE", UCP_EVENT_35H_02H) \
__PMC_EV_ALIAS("ADDR_OPCODE_MATCH.LOCAL", UCP_EVENT_35H_04H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", \
UCP_EVENT_40H_01H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", \
UCP_EVENT_40H_02H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", \
UCP_EVENT_40H_04H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", \
UCP_EVENT_40H_08H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", \
UCP_EVENT_40H_10H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", \
UCP_EVENT_40H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", \
UCP_EVENT_41H_01H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", \
UCP_EVENT_41H_02H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", \
UCP_EVENT_41H_04H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", \
UCP_EVENT_41H_08H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", \
UCP_EVENT_41H_10H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", \
UCP_EVENT_41H_20H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H) \
__PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_0", UCP_EVENT_42H_01H) \
__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H) \
__PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_1", UCP_EVENT_42H_04H) \
__PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H) \
__PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H) \
__PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H) \
__PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H) \
__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H) \
__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H) \
__PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H) \
__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H) \
__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H) \
__PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H) \
__PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H) \
__PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H) \
__PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H) \
__PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H) \
__PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H) \
__PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H) \
__PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H) \
__PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H) \
__PMC_EV_ALIAS("DRAM_THERMAL_THROTTLED", UCP_EVENT_67H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_0", UCP_EVENT_80H_01H) \
__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_1", UCP_EVENT_80H_02H) \
__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_2", UCP_EVENT_80H_04H) \
__PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_3", UCP_EVENT_80H_08H) \
__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_0", UCP_EVENT_81H_01H) \
__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_1", UCP_EVENT_81H_02H) \
__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_2", UCP_EVENT_81H_04H) \
__PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_3", UCP_EVENT_81H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("PROCHOT_ASSERTION", UCP_EVENT_82H_01H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_0", UCP_EVENT_83H_01H) \
__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_1", UCP_EVENT_83H_02H) \
__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_2", UCP_EVENT_83H_04H) \
__PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_3", UCP_EVENT_83H_08H) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV_ALIAS("TURBO_MODE.CORE_0", UCP_EVENT_84H_01H) \
__PMC_EV_ALIAS("TURBO_MODE.CORE_1", UCP_EVENT_84H_02H) \
__PMC_EV_ALIAS("TURBO_MODE.CORE_2", UCP_EVENT_84H_04H) \
__PMC_EV_ALIAS("TURBO_MODE.CORE_3", UCP_EVENT_84H_08H) \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_ENABLE", UCP_EVENT_85H_02H) \
__PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_DISABLE", UCP_EVENT_86H_01H)
Reserve events for XScale. Reviewed by: jkoshy, gnn MFC after: 1 week
2009-09-22 17:45:28 +00:00
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
#define __PMC_EV_ALIAS_SANDYBRIDGEUC() \
__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITI", UCP_EVENT_22H_01H) \
__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITFSE", UCP_EVENT_22H_02H) \
__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSHITFSE", UCP_EVENT_22H_04H) \
__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSFWDM", UCP_EVENT_22H_08H) \
__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_EXTERNAL", UCP_EVENT_22H_20H) \
__PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_XCORE", UCP_EVENT_22H_40H) \
__PMC_EV_ALIAS("CB0_XSNP_RESPONSE_AND_XCORE2", UCP_EVENT_22H_80H) \
__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \
__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.E", UCP_EVENT_34H_02H) \
__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.S", UCP_EVENT_34H_04H) \
__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \
__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_READ", UCP_EVENT_34H_10H) \
__PMC_EV_ALIAS("CB0_CACHE_LOOKUP_AND_READ2", UCP_EVENT_34H_20H) \
__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_EXTSNP", UCP_EVENT_34H_40H) \
__PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_ANY", UCP_EVENT_34H_80H) \
__PMC_EV_ALIAS("IMPH_CB0_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \
__PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \
__PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \
__PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \
__PMC_EV_ALIAS("IMPH_C0H_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \
__PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_84H_01H)
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
2012-03-01 21:23:26 +00:00
Reserve events for XScale. Reviewed by: jkoshy, gnn MFC after: 1 week
2009-09-22 17:45:28 +00:00
/*
Intel XScale hwpmc(4) support. This brings hwpmc(4) support for 2nd and 3rd generation XScale cores. Right now it's enabled by default to make sure we test this a bit. When the time comes it can be disabled by default. Tested on Gateworks boards. A man page is coming. Obtained from: //depot/user/rpaulo/xscalepmc/...
2009-12-23 23:16:54 +00:00
* Intel XScale events from:
*
* Intel XScale Core Developer's Manual
* January, 2004, #27347302
*
* 3rd Generation Intel XScale Microarchitecture
* Developer's Manual
* May 2007, #31628302
*
* First 14 events are for 1st and 2nd Generation Intel XScale cores. The
* remaining are available only on 3rd Generation Intel XScale cores.
Reserve events for XScale. Reviewed by: jkoshy, gnn MFC after: 1 week
2009-09-22 17:45:28 +00:00
*/
Intel XScale hwpmc(4) support. This brings hwpmc(4) support for 2nd and 3rd generation XScale cores. Right now it's enabled by default to make sure we test this a bit. When the time comes it can be disabled by default. Tested on Gateworks boards. A man page is coming. Obtained from: //depot/user/rpaulo/xscalepmc/...
2009-12-23 23:16:54 +00:00
#define __PMC_EV_XSCALE() \
__PMC_EV(XSCALE, IC_FETCH) \
__PMC_EV(XSCALE, IC_MISS) \
__PMC_EV(XSCALE, DATA_DEPENDENCY_STALLED) \
__PMC_EV(XSCALE, ITLB_MISS) \
__PMC_EV(XSCALE, DTLB_MISS) \
__PMC_EV(XSCALE, BRANCH_RETIRED) \
__PMC_EV(XSCALE, BRANCH_MISPRED) \
__PMC_EV(XSCALE, INSTR_RETIRED) \
__PMC_EV(XSCALE, DC_FULL_CYCLE) \
__PMC_EV(XSCALE, DC_FULL_CONTIG) \
__PMC_EV(XSCALE, DC_ACCESS) \
__PMC_EV(XSCALE, DC_MISS) \
__PMC_EV(XSCALE, DC_WRITEBACK) \
__PMC_EV(XSCALE, PC_CHANGE) \
__PMC_EV(XSCALE, BRANCH_RETIRED_ALL) \
__PMC_EV(XSCALE, INSTR_CYCLE) \
__PMC_EV(XSCALE, CP_STALL) \
__PMC_EV(XSCALE, PC_CHANGE_ALL) \
__PMC_EV(XSCALE, PIPELINE_FLUSH) \
__PMC_EV(XSCALE, BACKEND_STALL) \
__PMC_EV(XSCALE, MULTIPLIER_USE) \
__PMC_EV(XSCALE, MULTIPLIER_STALLED) \
__PMC_EV(XSCALE, DATA_CACHE_STALLED) \
__PMC_EV(XSCALE, L2_CACHE_REQ) \
__PMC_EV(XSCALE, L2_CACHE_MISS) \
__PMC_EV(XSCALE, ADDRESS_BUS_TRANS) \
__PMC_EV(XSCALE, SELF_ADDRESS_BUS_TRANS) \
__PMC_EV(XSCALE, DATA_BUS_TRANS)
Reserve events for XScale. Reviewed by: jkoshy, gnn MFC after: 1 week
2009-09-22 17:45:28 +00:00
#define PMC_EV_XSCALE_FIRST PMC_EV_XSCALE_IC_FETCH
Intel XScale hwpmc(4) support. This brings hwpmc(4) support for 2nd and 3rd generation XScale cores. Right now it's enabled by default to make sure we test this a bit. When the time comes it can be disabled by default. Tested on Gateworks boards. A man page is coming. Obtained from: //depot/user/rpaulo/xscalepmc/...
2009-12-23 23:16:54 +00:00
#define PMC_EV_XSCALE_LAST PMC_EV_XSCALE_DATA_BUS_TRANS
Reserve events for XScale. Reviewed by: jkoshy, gnn MFC after: 1 week
2009-09-22 17:45:28 +00:00
Add ARMv7 performance monitoring counters. Differential Revision: https://reviews.freebsd.org/D1687 Reviewed by: rpaulo Sponsored by: DARPA, AFRL
2015-01-28 16:08:07 +00:00
/*
* ARMv7 Events
*/
o Rework ARMv7 events list using aliases - same way as we have for arm64. o Extend it with Cortex A9-specific events.
2015-06-10 12:42:30 +00:00
#define __PMC_EV_ARMV7() \
__PMC_EV(ARMV7, EVENT_00H) \
__PMC_EV(ARMV7, EVENT_01H) \
__PMC_EV(ARMV7, EVENT_02H) \
__PMC_EV(ARMV7, EVENT_03H) \
__PMC_EV(ARMV7, EVENT_04H) \
__PMC_EV(ARMV7, EVENT_05H) \
__PMC_EV(ARMV7, EVENT_06H) \
__PMC_EV(ARMV7, EVENT_07H) \
__PMC_EV(ARMV7, EVENT_08H) \
__PMC_EV(ARMV7, EVENT_09H) \
__PMC_EV(ARMV7, EVENT_0AH) \
__PMC_EV(ARMV7, EVENT_0BH) \
__PMC_EV(ARMV7, EVENT_0CH) \
__PMC_EV(ARMV7, EVENT_0DH) \
__PMC_EV(ARMV7, EVENT_0EH) \
__PMC_EV(ARMV7, EVENT_0FH) \
__PMC_EV(ARMV7, EVENT_10H) \
__PMC_EV(ARMV7, EVENT_11H) \
__PMC_EV(ARMV7, EVENT_12H) \
__PMC_EV(ARMV7, EVENT_13H) \
__PMC_EV(ARMV7, EVENT_14H) \
__PMC_EV(ARMV7, EVENT_15H) \
__PMC_EV(ARMV7, EVENT_16H) \
__PMC_EV(ARMV7, EVENT_17H) \
__PMC_EV(ARMV7, EVENT_18H) \
__PMC_EV(ARMV7, EVENT_19H) \
__PMC_EV(ARMV7, EVENT_1AH) \
__PMC_EV(ARMV7, EVENT_1BH) \
__PMC_EV(ARMV7, EVENT_1CH) \
__PMC_EV(ARMV7, EVENT_1DH) \
__PMC_EV(ARMV7, EVENT_1EH) \
__PMC_EV(ARMV7, EVENT_1FH) \
__PMC_EV(ARMV7, EVENT_20H) \
__PMC_EV(ARMV7, EVENT_21H) \
__PMC_EV(ARMV7, EVENT_22H) \
__PMC_EV(ARMV7, EVENT_23H) \
__PMC_EV(ARMV7, EVENT_24H) \
__PMC_EV(ARMV7, EVENT_25H) \
__PMC_EV(ARMV7, EVENT_26H) \
__PMC_EV(ARMV7, EVENT_27H) \
__PMC_EV(ARMV7, EVENT_28H) \
__PMC_EV(ARMV7, EVENT_29H) \
__PMC_EV(ARMV7, EVENT_2AH) \
__PMC_EV(ARMV7, EVENT_2BH) \
__PMC_EV(ARMV7, EVENT_2CH) \
__PMC_EV(ARMV7, EVENT_2DH) \
__PMC_EV(ARMV7, EVENT_2EH) \
__PMC_EV(ARMV7, EVENT_2FH) \
__PMC_EV(ARMV7, EVENT_30H) \
__PMC_EV(ARMV7, EVENT_31H) \
__PMC_EV(ARMV7, EVENT_32H) \
__PMC_EV(ARMV7, EVENT_33H) \
__PMC_EV(ARMV7, EVENT_34H) \
__PMC_EV(ARMV7, EVENT_35H) \
__PMC_EV(ARMV7, EVENT_36H) \
__PMC_EV(ARMV7, EVENT_37H) \
__PMC_EV(ARMV7, EVENT_38H) \
__PMC_EV(ARMV7, EVENT_39H) \
__PMC_EV(ARMV7, EVENT_3AH) \
__PMC_EV(ARMV7, EVENT_3BH) \
__PMC_EV(ARMV7, EVENT_3CH) \
__PMC_EV(ARMV7, EVENT_3DH) \
__PMC_EV(ARMV7, EVENT_3EH) \
__PMC_EV(ARMV7, EVENT_3FH) \
__PMC_EV(ARMV7, EVENT_40H) \
__PMC_EV(ARMV7, EVENT_41H) \
__PMC_EV(ARMV7, EVENT_42H) \
__PMC_EV(ARMV7, EVENT_43H) \
__PMC_EV(ARMV7, EVENT_44H) \
__PMC_EV(ARMV7, EVENT_45H) \
__PMC_EV(ARMV7, EVENT_46H) \
__PMC_EV(ARMV7, EVENT_47H) \
__PMC_EV(ARMV7, EVENT_48H) \
__PMC_EV(ARMV7, EVENT_49H) \
__PMC_EV(ARMV7, EVENT_4AH) \
__PMC_EV(ARMV7, EVENT_4BH) \
__PMC_EV(ARMV7, EVENT_4CH) \
__PMC_EV(ARMV7, EVENT_4DH) \
__PMC_EV(ARMV7, EVENT_4EH) \
__PMC_EV(ARMV7, EVENT_4FH) \
__PMC_EV(ARMV7, EVENT_50H) \
__PMC_EV(ARMV7, EVENT_51H) \
__PMC_EV(ARMV7, EVENT_52H) \
__PMC_EV(ARMV7, EVENT_53H) \
__PMC_EV(ARMV7, EVENT_54H) \
__PMC_EV(ARMV7, EVENT_55H) \
__PMC_EV(ARMV7, EVENT_56H) \
__PMC_EV(ARMV7, EVENT_57H) \
__PMC_EV(ARMV7, EVENT_58H) \
__PMC_EV(ARMV7, EVENT_59H) \
__PMC_EV(ARMV7, EVENT_5AH) \
__PMC_EV(ARMV7, EVENT_5BH) \
__PMC_EV(ARMV7, EVENT_5CH) \
__PMC_EV(ARMV7, EVENT_5DH) \
__PMC_EV(ARMV7, EVENT_5EH) \
__PMC_EV(ARMV7, EVENT_5FH) \
__PMC_EV(ARMV7, EVENT_60H) \
__PMC_EV(ARMV7, EVENT_61H) \
__PMC_EV(ARMV7, EVENT_62H) \
__PMC_EV(ARMV7, EVENT_63H) \
__PMC_EV(ARMV7, EVENT_64H) \
__PMC_EV(ARMV7, EVENT_65H) \
__PMC_EV(ARMV7, EVENT_66H) \
__PMC_EV(ARMV7, EVENT_67H) \
__PMC_EV(ARMV7, EVENT_68H) \
__PMC_EV(ARMV7, EVENT_69H) \
__PMC_EV(ARMV7, EVENT_6AH) \
__PMC_EV(ARMV7, EVENT_6BH) \
__PMC_EV(ARMV7, EVENT_6CH) \
__PMC_EV(ARMV7, EVENT_6DH) \
__PMC_EV(ARMV7, EVENT_6EH) \
__PMC_EV(ARMV7, EVENT_6FH) \
__PMC_EV(ARMV7, EVENT_70H) \
__PMC_EV(ARMV7, EVENT_71H) \
__PMC_EV(ARMV7, EVENT_72H) \
__PMC_EV(ARMV7, EVENT_73H) \
__PMC_EV(ARMV7, EVENT_74H) \
__PMC_EV(ARMV7, EVENT_75H) \
__PMC_EV(ARMV7, EVENT_76H) \
__PMC_EV(ARMV7, EVENT_77H) \
__PMC_EV(ARMV7, EVENT_78H) \
__PMC_EV(ARMV7, EVENT_79H) \
__PMC_EV(ARMV7, EVENT_7AH) \
__PMC_EV(ARMV7, EVENT_7BH) \
__PMC_EV(ARMV7, EVENT_7CH) \
__PMC_EV(ARMV7, EVENT_7DH) \
__PMC_EV(ARMV7, EVENT_7EH) \
__PMC_EV(ARMV7, EVENT_7FH) \
__PMC_EV(ARMV7, EVENT_80H) \
__PMC_EV(ARMV7, EVENT_81H) \
__PMC_EV(ARMV7, EVENT_82H) \
__PMC_EV(ARMV7, EVENT_83H) \
__PMC_EV(ARMV7, EVENT_84H) \
__PMC_EV(ARMV7, EVENT_85H) \
__PMC_EV(ARMV7, EVENT_86H) \
__PMC_EV(ARMV7, EVENT_87H) \
__PMC_EV(ARMV7, EVENT_88H) \
__PMC_EV(ARMV7, EVENT_89H) \
__PMC_EV(ARMV7, EVENT_8AH) \
__PMC_EV(ARMV7, EVENT_8BH) \
__PMC_EV(ARMV7, EVENT_8CH) \
__PMC_EV(ARMV7, EVENT_8DH) \
__PMC_EV(ARMV7, EVENT_8EH) \
__PMC_EV(ARMV7, EVENT_8FH) \
__PMC_EV(ARMV7, EVENT_90H) \
__PMC_EV(ARMV7, EVENT_91H) \
__PMC_EV(ARMV7, EVENT_92H) \
__PMC_EV(ARMV7, EVENT_93H) \
__PMC_EV(ARMV7, EVENT_94H) \
__PMC_EV(ARMV7, EVENT_95H) \
__PMC_EV(ARMV7, EVENT_96H) \
__PMC_EV(ARMV7, EVENT_97H) \
__PMC_EV(ARMV7, EVENT_98H) \
__PMC_EV(ARMV7, EVENT_99H) \
__PMC_EV(ARMV7, EVENT_9AH) \
__PMC_EV(ARMV7, EVENT_9BH) \
__PMC_EV(ARMV7, EVENT_9CH) \
__PMC_EV(ARMV7, EVENT_9DH) \
__PMC_EV(ARMV7, EVENT_9EH) \
__PMC_EV(ARMV7, EVENT_9FH) \
__PMC_EV(ARMV7, EVENT_A0H) \
__PMC_EV(ARMV7, EVENT_A1H) \
__PMC_EV(ARMV7, EVENT_A2H) \
__PMC_EV(ARMV7, EVENT_A3H) \
__PMC_EV(ARMV7, EVENT_A4H) \
__PMC_EV(ARMV7, EVENT_A5H) \
__PMC_EV(ARMV7, EVENT_A6H) \
__PMC_EV(ARMV7, EVENT_A7H) \
__PMC_EV(ARMV7, EVENT_A8H) \
__PMC_EV(ARMV7, EVENT_A9H) \
__PMC_EV(ARMV7, EVENT_AAH) \
__PMC_EV(ARMV7, EVENT_ABH) \
__PMC_EV(ARMV7, EVENT_ACH) \
__PMC_EV(ARMV7, EVENT_ADH) \
__PMC_EV(ARMV7, EVENT_AEH) \
__PMC_EV(ARMV7, EVENT_AFH) \
__PMC_EV(ARMV7, EVENT_B0H) \
__PMC_EV(ARMV7, EVENT_B1H) \
__PMC_EV(ARMV7, EVENT_B2H) \
__PMC_EV(ARMV7, EVENT_B3H) \
__PMC_EV(ARMV7, EVENT_B4H) \
__PMC_EV(ARMV7, EVENT_B5H) \
__PMC_EV(ARMV7, EVENT_B6H) \
__PMC_EV(ARMV7, EVENT_B7H) \
__PMC_EV(ARMV7, EVENT_B8H) \
__PMC_EV(ARMV7, EVENT_B9H) \
__PMC_EV(ARMV7, EVENT_BAH) \
__PMC_EV(ARMV7, EVENT_BBH) \
__PMC_EV(ARMV7, EVENT_BCH) \
__PMC_EV(ARMV7, EVENT_BDH) \
__PMC_EV(ARMV7, EVENT_BEH) \
__PMC_EV(ARMV7, EVENT_BFH) \
__PMC_EV(ARMV7, EVENT_C0H) \
__PMC_EV(ARMV7, EVENT_C1H) \
__PMC_EV(ARMV7, EVENT_C2H) \
__PMC_EV(ARMV7, EVENT_C3H) \
__PMC_EV(ARMV7, EVENT_C4H) \
__PMC_EV(ARMV7, EVENT_C5H) \
__PMC_EV(ARMV7, EVENT_C6H) \
__PMC_EV(ARMV7, EVENT_C7H) \
__PMC_EV(ARMV7, EVENT_C8H) \
__PMC_EV(ARMV7, EVENT_C9H) \
__PMC_EV(ARMV7, EVENT_CAH) \
__PMC_EV(ARMV7, EVENT_CBH) \
__PMC_EV(ARMV7, EVENT_CCH) \
__PMC_EV(ARMV7, EVENT_CDH) \
__PMC_EV(ARMV7, EVENT_CEH) \
__PMC_EV(ARMV7, EVENT_CFH) \
__PMC_EV(ARMV7, EVENT_D0H) \
__PMC_EV(ARMV7, EVENT_D1H) \
__PMC_EV(ARMV7, EVENT_D2H) \
__PMC_EV(ARMV7, EVENT_D3H) \
__PMC_EV(ARMV7, EVENT_D4H) \
__PMC_EV(ARMV7, EVENT_D5H) \
__PMC_EV(ARMV7, EVENT_D6H) \
__PMC_EV(ARMV7, EVENT_D7H) \
__PMC_EV(ARMV7, EVENT_D8H) \
__PMC_EV(ARMV7, EVENT_D9H) \
__PMC_EV(ARMV7, EVENT_DAH) \
__PMC_EV(ARMV7, EVENT_DBH) \
__PMC_EV(ARMV7, EVENT_DCH) \
__PMC_EV(ARMV7, EVENT_DDH) \
__PMC_EV(ARMV7, EVENT_DEH) \
__PMC_EV(ARMV7, EVENT_DFH) \
__PMC_EV(ARMV7, EVENT_E0H) \
__PMC_EV(ARMV7, EVENT_E1H) \
__PMC_EV(ARMV7, EVENT_E2H) \
__PMC_EV(ARMV7, EVENT_E3H) \
__PMC_EV(ARMV7, EVENT_E4H) \
__PMC_EV(ARMV7, EVENT_E5H) \
__PMC_EV(ARMV7, EVENT_E6H) \
__PMC_EV(ARMV7, EVENT_E7H) \
__PMC_EV(ARMV7, EVENT_E8H) \
__PMC_EV(ARMV7, EVENT_E9H) \
__PMC_EV(ARMV7, EVENT_EAH) \
__PMC_EV(ARMV7, EVENT_EBH) \
__PMC_EV(ARMV7, EVENT_ECH) \
__PMC_EV(ARMV7, EVENT_EDH) \
__PMC_EV(ARMV7, EVENT_EEH) \
__PMC_EV(ARMV7, EVENT_EFH) \
__PMC_EV(ARMV7, EVENT_F0H) \
__PMC_EV(ARMV7, EVENT_F1H) \
__PMC_EV(ARMV7, EVENT_F2H) \
__PMC_EV(ARMV7, EVENT_F3H) \
__PMC_EV(ARMV7, EVENT_F4H) \
__PMC_EV(ARMV7, EVENT_F5H) \
__PMC_EV(ARMV7, EVENT_F6H) \
__PMC_EV(ARMV7, EVENT_F7H) \
__PMC_EV(ARMV7, EVENT_F8H) \
__PMC_EV(ARMV7, EVENT_F9H) \
__PMC_EV(ARMV7, EVENT_FAH) \
__PMC_EV(ARMV7, EVENT_FBH) \
__PMC_EV(ARMV7, EVENT_FCH) \
__PMC_EV(ARMV7, EVENT_FDH) \
__PMC_EV(ARMV7, EVENT_FEH) \
__PMC_EV(ARMV7, EVENT_FFH)
Add ARMv7 performance monitoring counters. Differential Revision: https://reviews.freebsd.org/D1687 Reviewed by: rpaulo Sponsored by: DARPA, AFRL
2015-01-28 16:08:07 +00:00
o Rework ARMv7 events list using aliases - same way as we have for arm64. o Extend it with Cortex A9-specific events.
2015-06-10 12:42:30 +00:00
#define PMC_EV_ARMV7_FIRST PMC_EV_ARMV7_EVENT_00H
#define PMC_EV_ARMV7_LAST PMC_EV_ARMV7_EVENT_FFH
Now that we can detect the Cortex-A8 properly, fix the event list according to the Cortex-A8 TRM r3p2 section 3.2.49. The A8 list differs from the "ARM-v7 common" list, given the A8 was an earlier model. There is still more work to be done for other Cortex-Ax version as andrew points out, but I am just trying to fix A8 for now for teaching. MFC after: 2 weeks Sponsored by: DARPA/AFRL Obtained from: Cambridge/L41 Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D3876
2015-10-14 17:20:19 +00:00
#define __PMC_EV_ALIAS_ARMV7_COMMON_A8() \
o Rework ARMv7 events list using aliases - same way as we have for arm64. o Extend it with Cortex A9-specific events.
2015-06-10 12:42:30 +00:00
__PMC_EV_ALIAS("PMNC_SW_INCR", ARMV7_EVENT_00H) \
__PMC_EV_ALIAS("L1_ICACHE_REFILL", ARMV7_EVENT_01H) \
__PMC_EV_ALIAS("ITLB_REFILL", ARMV7_EVENT_02H) \
__PMC_EV_ALIAS("L1_DCACHE_REFILL", ARMV7_EVENT_03H) \
__PMC_EV_ALIAS("L1_DCACHE_ACCESS", ARMV7_EVENT_04H) \
__PMC_EV_ALIAS("DTLB_REFILL", ARMV7_EVENT_05H) \
__PMC_EV_ALIAS("MEM_READ", ARMV7_EVENT_06H) \
__PMC_EV_ALIAS("MEM_WRITE", ARMV7_EVENT_07H) \
__PMC_EV_ALIAS("INSTR_EXECUTED", ARMV7_EVENT_08H) \
__PMC_EV_ALIAS("EXC_TAKEN", ARMV7_EVENT_09H) \
__PMC_EV_ALIAS("EXC_EXECUTED", ARMV7_EVENT_0AH) \
__PMC_EV_ALIAS("CID_WRITE", ARMV7_EVENT_0BH) \
__PMC_EV_ALIAS("PC_WRITE", ARMV7_EVENT_0CH) \
__PMC_EV_ALIAS("PC_IMM_BRANCH", ARMV7_EVENT_0DH) \
__PMC_EV_ALIAS("PC_PROC_RETURN", ARMV7_EVENT_0EH) \
__PMC_EV_ALIAS("MEM_UNALIGNED_ACCESS", ARMV7_EVENT_0FH) \
__PMC_EV_ALIAS("PC_BRANCH_MIS_PRED", ARMV7_EVENT_10H) \
__PMC_EV_ALIAS("CLOCK_CYCLES", ARMV7_EVENT_11H) \
Now that we can detect the Cortex-A8 properly, fix the event list according to the Cortex-A8 TRM r3p2 section 3.2.49. The A8 list differs from the "ARM-v7 common" list, given the A8 was an earlier model. There is still more work to be done for other Cortex-Ax version as andrew points out, but I am just trying to fix A8 for now for teaching. MFC after: 2 weeks Sponsored by: DARPA/AFRL Obtained from: Cambridge/L41 Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D3876
2015-10-14 17:20:19 +00:00
__PMC_EV_ALIAS("PC_BRANCH_PRED", ARMV7_EVENT_12H)
#define __PMC_EV_ALIAS_ARMV7_COMMON() \
__PMC_EV_ALIAS_ARMV7_COMMON_A8() \
o Rework ARMv7 events list using aliases - same way as we have for arm64. o Extend it with Cortex A9-specific events.
2015-06-10 12:42:30 +00:00
__PMC_EV_ALIAS("MEM_ACCESS", ARMV7_EVENT_13H) \
__PMC_EV_ALIAS("L1_ICACHE_ACCESS", ARMV7_EVENT_14H) \
__PMC_EV_ALIAS("L1_DCACHE_WB", ARMV7_EVENT_15H) \
__PMC_EV_ALIAS("L2_CACHE_ACCESS", ARMV7_EVENT_16H) \
__PMC_EV_ALIAS("L2_CACHE_REFILL", ARMV7_EVENT_17H) \
__PMC_EV_ALIAS("L2_CACHE_WB", ARMV7_EVENT_18H) \
__PMC_EV_ALIAS("BUS_ACCESS", ARMV7_EVENT_19H) \
__PMC_EV_ALIAS("MEM_ERROR", ARMV7_EVENT_1AH) \
__PMC_EV_ALIAS("INSTR_SPEC", ARMV7_EVENT_1BH) \
__PMC_EV_ALIAS("TTBR_WRITE", ARMV7_EVENT_1CH) \
__PMC_EV_ALIAS("BUS_CYCLES", ARMV7_EVENT_1DH) \
__PMC_EV_ALIAS("CPU_CYCLES", ARMV7_EVENT_FFH)
Now that we can detect the Cortex-A8 properly, fix the event list according to the Cortex-A8 TRM r3p2 section 3.2.49. The A8 list differs from the "ARM-v7 common" list, given the A8 was an earlier model. There is still more work to be done for other Cortex-Ax version as andrew points out, but I am just trying to fix A8 for now for teaching. MFC after: 2 weeks Sponsored by: DARPA/AFRL Obtained from: Cambridge/L41 Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D3876
2015-10-14 17:20:19 +00:00
#define __PMC_EV_ALIAS_ARMV7_CORTEX_A8() \
__PMC_EV_ALIAS_ARMV7_COMMON_A8() \
__PMC_EV_ALIAS("WRITE_BUF_FULL", ARMV7_EVENT_40H) \
__PMC_EV_ALIAS("L2_STORE_MERGED", ARMV7_EVENT_41H) \
__PMC_EV_ALIAS("L2_STORE_BUFFERABLE", ARMV7_EVENT_42H) \
__PMC_EV_ALIAS("L2_ACCESS", ARMV7_EVENT_43H) \
__PMC_EV_ALIAS("L2_CACHE_MISS", ARMV7_EVENT_44H) \
__PMC_EV_ALIAS("AXI_READ", ARMV7_EVENT_45H) \
__PMC_EV_ALIAS("AXI_WRITE", ARMV7_EVENT_46H) \
__PMC_EV_ALIAS("MEM_REPLAY_EVT", ARMV7_EVENT_47H) \
__PMC_EV_ALIAS("MEM_UNALIGNED_ACCESS_REPLAY", ARMV7_EVENT_48H) \
__PMC_EV_ALIAS("L1_DCACHE_HASH_MISS", ARMV7_EVENT_49H) \
__PMC_EV_ALIAS("L1_ICACHE_HASH_MISS", ARMV7_EVENT_4AH) \
__PMC_EV_ALIAS("L1_CACHE_PAGECOL_ALIAS", ARMV7_EVENT_4BH) \
__PMC_EV_ALIAS("L1_DCACHE_NEON_ACCESS", ARMV7_EVENT_4CH) \
__PMC_EV_ALIAS("L1_DCACHE_NEON_CACHEABLE", ARMV7_EVENT_4DH) \
__PMC_EV_ALIAS("L2_CACHE_NEON_MEM_ACCESS", ARMV7_EVENT_4EH) \
__PMC_EV_ALIAS("L2_CACHE_NEON_HIT", ARMV7_EVENT_4FH) \
__PMC_EV_ALIAS("L1_CACHE_ACCESS_NOCP15", ARMV7_EVENT_50H) \
__PMC_EV_ALIAS("RET_STACK_MISPREDICT", ARMV7_EVENT_51H) \
__PMC_EV_ALIAS("BRANCH_DIR_MISPREDICT", ARMV7_EVENT_52H) \
__PMC_EV_ALIAS("PRED_BRANCH_PRED_TAKEN", ARMV7_EVENT_53H) \
__PMC_EV_ALIAS("PRED_BRANCH_EXEC_TAKEN", ARMV7_EVENT_54H) \
__PMC_EV_ALIAS("OPS_ISSUED", ARMV7_EVENT_55H) \
__PMC_EV_ALIAS("CYCLES_NO_INSTRUCTION", ARMV7_EVENT_56H) \
__PMC_EV_ALIAS("INSTRUCTIONS_ISSUED_CYCLE", ARMV7_EVENT_57H) \
__PMC_EV_ALIAS("CYCLES_STALLED_NEON_MRC", ARMV7_EVENT_58H) \
__PMC_EV_ALIAS("CYCLES_STALLED_NEON_FULLQ", ARMV7_EVENT_59H) \
__PMC_EV_ALIAS("CYCLES_NONIDLE_NEON_INT", ARMV7_EVENT_5AH) \
__PMC_EV_ALIAS("PMUEXTIN0_EVT", ARMV7_EVENT_70H) \
__PMC_EV_ALIAS("PMUEXTIN1_EVT", ARMV7_EVENT_71H) \
__PMC_EV_ALIAS("PMUEXTIN_EVT", ARMV7_EVENT_72H)
#define PMC_EV_ARMV7_CORTEX_A8_FIRST PMC_EV_ARMV7_PMNC_SW_INCR
#define PMC_EV_ARMV7_CORTEX_A8_LAST PMC_EV_ARMV7_PMUEXTIN_EVT
o Rework ARMv7 events list using aliases - same way as we have for arm64. o Extend it with Cortex A9-specific events.
2015-06-10 12:42:30 +00:00
#define __PMC_EV_ALIAS_ARMV7_CORTEX_A9() \
__PMC_EV_ALIAS_ARMV7_COMMON() \
__PMC_EV_ALIAS("JAVA_BYTECODE", ARMV7_EVENT_40H) \
__PMC_EV_ALIAS("SOFTWARE_JAVA_BYTECODE", ARMV7_EVENT_41H) \
__PMC_EV_ALIAS("JAZELLE_BACKWARD_BRANCH", ARMV7_EVENT_42H) \
__PMC_EV_ALIAS("COHERENT_LINEFILL_MISSC", ARMV7_EVENT_50H) \
__PMC_EV_ALIAS("COHERENT_LINEFILL_HITC", ARMV7_EVENT_51H) \
__PMC_EV_ALIAS("INSTR_CACHE_DEPENDENT_STALL", ARMV7_EVENT_60H) \
__PMC_EV_ALIAS("DATA_CACHE_DEPENDENT_STALL", ARMV7_EVENT_61H) \
__PMC_EV_ALIAS("MAIN_TLB_MISS_STALL", ARMV7_EVENT_62H) \
__PMC_EV_ALIAS("STREX_PASSED", ARMV7_EVENT_63H) \
__PMC_EV_ALIAS("STREX_FAILED", ARMV7_EVENT_64H) \
__PMC_EV_ALIAS("DATA_EVICTION", ARMV7_EVENT_65H) \
__PMC_EV_ALIAS("ISSUE_DNOT_DISPATCH_ANY_INSTR", ARMV7_EVENT_66H) \
__PMC_EV_ALIAS("ISSUE_IS_EMPTY", ARMV7_EVENT_67H) \
__PMC_EV_ALIAS("MAIN_EXECUTION_UNIT_PIPE", ARMV7_EVENT_70H) \
__PMC_EV_ALIAS("SECOND_EXECUTION_UNIT_PIPE", ARMV7_EVENT_71H) \
__PMC_EV_ALIAS("LOAD_STORE_PIPE", ARMV7_EVENT_72H) \
__PMC_EV_ALIAS("FLOATING_POINT_INSTR_RENAMED", ARMV7_EVENT_73H) \
__PMC_EV_ALIAS("NEON_INSTRS_RENAMED", ARMV7_EVENT_74H) \
__PMC_EV_ALIAS("PLD_STALL", ARMV7_EVENT_80H) \
__PMC_EV_ALIAS("WRITE_STALL", ARMV7_EVENT_81H) \
__PMC_EV_ALIAS("INSTR_MAIN_TLB_MISS_STALL", ARMV7_EVENT_82H) \
__PMC_EV_ALIAS("DATA_MAIN_TLB_MISS_STALL", ARMV7_EVENT_83H) \
__PMC_EV_ALIAS("INSTR_MICRO_TLB_MISS_STALL", ARMV7_EVENT_84H) \
__PMC_EV_ALIAS("DATA_MICRO_TLB_MISS_STALL", ARMV7_EVENT_85H) \
__PMC_EV_ALIAS("DMB_STALL", ARMV7_EVENT_86H) \
__PMC_EV_ALIAS("INTEGER_CORE_CLOCK_ENABLED", ARMV7_EVENT_8AH) \
__PMC_EV_ALIAS("DATA_ENGINE_CLOCK_ENABLED", ARMV7_EVENT_8BH) \
__PMC_EV_ALIAS("ISB", ARMV7_EVENT_90H) \
__PMC_EV_ALIAS("DSB", ARMV7_EVENT_91H) \
__PMC_EV_ALIAS("DMB", ARMV7_EVENT_92H) \
__PMC_EV_ALIAS("EXTERNAL_INTERRUPT", ARMV7_EVENT_93H) \
__PMC_EV_ALIAS("PLE_CACHE_LINE_REQ_COMPLETED", ARMV7_EVENT_A0H) \
__PMC_EV_ALIAS("PLE_CACHE_LINE_REQ_SKIPPED", ARMV7_EVENT_A1H) \
__PMC_EV_ALIAS("PLE_FIFO_FLUSH", ARMV7_EVENT_A2H) \
__PMC_EV_ALIAS("PLE_REQUEST_COMPLETED", ARMV7_EVENT_A3H) \
__PMC_EV_ALIAS("PLE_FIFO_OVERFLOW", ARMV7_EVENT_A4H) \
__PMC_EV_ALIAS("PLE_REQUEST_PROGRAMMED", ARMV7_EVENT_A5H)
Add ARMv7 performance monitoring counters. Differential Revision: https://reviews.freebsd.org/D1687 Reviewed by: rpaulo Sponsored by: DARPA, AFRL
2015-01-28 16:08:07 +00:00
Add Performance Monitoring Counters support for AArch64. Family-common and CPU-specific counters implemented. Supported CPUs: ARM Cortex A53/57/72. Reviewed by: andrew, bz, emaste, gnn, jhb Sponsored by: ARM Limited Differential Revision: https://reviews.freebsd.org/D2555
2015-05-19 15:25:47 +00:00
/*
* ARMv8 Events
*/
#define __PMC_EV_ARMV8() \
__PMC_EV(ARMV8, EVENT_00H) \
__PMC_EV(ARMV8, EVENT_01H) \
__PMC_EV(ARMV8, EVENT_02H) \
__PMC_EV(ARMV8, EVENT_03H) \
__PMC_EV(ARMV8, EVENT_04H) \
__PMC_EV(ARMV8, EVENT_05H) \
__PMC_EV(ARMV8, EVENT_06H) \
__PMC_EV(ARMV8, EVENT_07H) \
__PMC_EV(ARMV8, EVENT_08H) \
__PMC_EV(ARMV8, EVENT_09H) \
__PMC_EV(ARMV8, EVENT_0AH) \
__PMC_EV(ARMV8, EVENT_0BH) \
__PMC_EV(ARMV8, EVENT_0CH) \
__PMC_EV(ARMV8, EVENT_0DH) \
__PMC_EV(ARMV8, EVENT_0EH) \
__PMC_EV(ARMV8, EVENT_0FH) \
__PMC_EV(ARMV8, EVENT_10H) \
__PMC_EV(ARMV8, EVENT_11H) \
__PMC_EV(ARMV8, EVENT_12H) \
__PMC_EV(ARMV8, EVENT_13H) \
__PMC_EV(ARMV8, EVENT_14H) \
__PMC_EV(ARMV8, EVENT_15H) \
__PMC_EV(ARMV8, EVENT_16H) \
__PMC_EV(ARMV8, EVENT_17H) \
__PMC_EV(ARMV8, EVENT_18H) \
__PMC_EV(ARMV8, EVENT_19H) \
__PMC_EV(ARMV8, EVENT_1AH) \
__PMC_EV(ARMV8, EVENT_1BH) \
__PMC_EV(ARMV8, EVENT_1CH) \
__PMC_EV(ARMV8, EVENT_1DH) \
__PMC_EV(ARMV8, EVENT_1EH) \
__PMC_EV(ARMV8, EVENT_1FH) \
__PMC_EV(ARMV8, EVENT_20H) \
__PMC_EV(ARMV8, EVENT_21H) \
__PMC_EV(ARMV8, EVENT_22H) \
__PMC_EV(ARMV8, EVENT_23H) \
__PMC_EV(ARMV8, EVENT_24H) \
__PMC_EV(ARMV8, EVENT_25H) \
__PMC_EV(ARMV8, EVENT_26H) \
__PMC_EV(ARMV8, EVENT_27H) \
__PMC_EV(ARMV8, EVENT_28H) \
__PMC_EV(ARMV8, EVENT_29H) \
__PMC_EV(ARMV8, EVENT_2AH) \
__PMC_EV(ARMV8, EVENT_2BH) \
__PMC_EV(ARMV8, EVENT_2CH) \
__PMC_EV(ARMV8, EVENT_2DH) \
__PMC_EV(ARMV8, EVENT_2EH) \
__PMC_EV(ARMV8, EVENT_2FH) \
__PMC_EV(ARMV8, EVENT_30H) \
__PMC_EV(ARMV8, EVENT_31H) \
__PMC_EV(ARMV8, EVENT_32H) \
__PMC_EV(ARMV8, EVENT_33H) \
__PMC_EV(ARMV8, EVENT_34H) \
__PMC_EV(ARMV8, EVENT_35H) \
__PMC_EV(ARMV8, EVENT_36H) \
__PMC_EV(ARMV8, EVENT_37H) \
__PMC_EV(ARMV8, EVENT_38H) \
__PMC_EV(ARMV8, EVENT_39H) \
__PMC_EV(ARMV8, EVENT_3AH) \
__PMC_EV(ARMV8, EVENT_3BH) \
__PMC_EV(ARMV8, EVENT_3CH) \
__PMC_EV(ARMV8, EVENT_3DH) \
__PMC_EV(ARMV8, EVENT_3EH) \
__PMC_EV(ARMV8, EVENT_3FH) \
__PMC_EV(ARMV8, EVENT_40H) \
__PMC_EV(ARMV8, EVENT_41H) \
__PMC_EV(ARMV8, EVENT_42H) \
__PMC_EV(ARMV8, EVENT_43H) \
__PMC_EV(ARMV8, EVENT_44H) \
__PMC_EV(ARMV8, EVENT_45H) \
__PMC_EV(ARMV8, EVENT_46H) \
__PMC_EV(ARMV8, EVENT_47H) \
__PMC_EV(ARMV8, EVENT_48H) \
__PMC_EV(ARMV8, EVENT_49H) \
__PMC_EV(ARMV8, EVENT_4AH) \
__PMC_EV(ARMV8, EVENT_4BH) \
__PMC_EV(ARMV8, EVENT_4CH) \
__PMC_EV(ARMV8, EVENT_4DH) \
__PMC_EV(ARMV8, EVENT_4EH) \
__PMC_EV(ARMV8, EVENT_4FH) \
__PMC_EV(ARMV8, EVENT_50H) \
__PMC_EV(ARMV8, EVENT_51H) \
__PMC_EV(ARMV8, EVENT_52H) \
__PMC_EV(ARMV8, EVENT_53H) \
__PMC_EV(ARMV8, EVENT_54H) \
__PMC_EV(ARMV8, EVENT_55H) \
__PMC_EV(ARMV8, EVENT_56H) \
__PMC_EV(ARMV8, EVENT_57H) \
__PMC_EV(ARMV8, EVENT_58H) \
__PMC_EV(ARMV8, EVENT_59H) \
__PMC_EV(ARMV8, EVENT_5AH) \
__PMC_EV(ARMV8, EVENT_5BH) \
__PMC_EV(ARMV8, EVENT_5CH) \
__PMC_EV(ARMV8, EVENT_5DH) \
__PMC_EV(ARMV8, EVENT_5EH) \
__PMC_EV(ARMV8, EVENT_5FH) \
__PMC_EV(ARMV8, EVENT_60H) \
__PMC_EV(ARMV8, EVENT_61H) \
__PMC_EV(ARMV8, EVENT_62H) \
__PMC_EV(ARMV8, EVENT_63H) \
__PMC_EV(ARMV8, EVENT_64H) \
__PMC_EV(ARMV8, EVENT_65H) \
__PMC_EV(ARMV8, EVENT_66H) \
__PMC_EV(ARMV8, EVENT_67H) \
__PMC_EV(ARMV8, EVENT_68H) \
__PMC_EV(ARMV8, EVENT_69H) \
__PMC_EV(ARMV8, EVENT_6AH) \
__PMC_EV(ARMV8, EVENT_6BH) \
__PMC_EV(ARMV8, EVENT_6CH) \
__PMC_EV(ARMV8, EVENT_6DH) \
__PMC_EV(ARMV8, EVENT_6EH) \
__PMC_EV(ARMV8, EVENT_6FH) \
__PMC_EV(ARMV8, EVENT_70H) \
__PMC_EV(ARMV8, EVENT_71H) \
__PMC_EV(ARMV8, EVENT_72H) \
__PMC_EV(ARMV8, EVENT_73H) \
__PMC_EV(ARMV8, EVENT_74H) \
__PMC_EV(ARMV8, EVENT_75H) \
__PMC_EV(ARMV8, EVENT_76H) \
__PMC_EV(ARMV8, EVENT_77H) \
__PMC_EV(ARMV8, EVENT_78H) \
__PMC_EV(ARMV8, EVENT_79H) \
__PMC_EV(ARMV8, EVENT_7AH) \
__PMC_EV(ARMV8, EVENT_7BH) \
__PMC_EV(ARMV8, EVENT_7CH) \
__PMC_EV(ARMV8, EVENT_7DH) \
__PMC_EV(ARMV8, EVENT_7EH) \
__PMC_EV(ARMV8, EVENT_7FH) \
__PMC_EV(ARMV8, EVENT_80H) \
__PMC_EV(ARMV8, EVENT_81H) \
__PMC_EV(ARMV8, EVENT_82H) \
__PMC_EV(ARMV8, EVENT_83H) \
__PMC_EV(ARMV8, EVENT_84H) \
__PMC_EV(ARMV8, EVENT_85H) \
__PMC_EV(ARMV8, EVENT_86H) \
__PMC_EV(ARMV8, EVENT_87H) \
__PMC_EV(ARMV8, EVENT_88H) \
__PMC_EV(ARMV8, EVENT_89H) \
__PMC_EV(ARMV8, EVENT_8AH) \
__PMC_EV(ARMV8, EVENT_8BH) \
__PMC_EV(ARMV8, EVENT_8CH) \
__PMC_EV(ARMV8, EVENT_8DH) \
__PMC_EV(ARMV8, EVENT_8EH) \
__PMC_EV(ARMV8, EVENT_8FH) \
__PMC_EV(ARMV8, EVENT_90H) \
__PMC_EV(ARMV8, EVENT_91H) \
__PMC_EV(ARMV8, EVENT_92H) \
__PMC_EV(ARMV8, EVENT_93H) \
__PMC_EV(ARMV8, EVENT_94H) \
__PMC_EV(ARMV8, EVENT_95H) \
__PMC_EV(ARMV8, EVENT_96H) \
__PMC_EV(ARMV8, EVENT_97H) \
__PMC_EV(ARMV8, EVENT_98H) \
__PMC_EV(ARMV8, EVENT_99H) \
__PMC_EV(ARMV8, EVENT_9AH) \
__PMC_EV(ARMV8, EVENT_9BH) \
__PMC_EV(ARMV8, EVENT_9CH) \
__PMC_EV(ARMV8, EVENT_9DH) \
__PMC_EV(ARMV8, EVENT_9EH) \
__PMC_EV(ARMV8, EVENT_9FH) \
__PMC_EV(ARMV8, EVENT_A0H) \
__PMC_EV(ARMV8, EVENT_A1H) \
__PMC_EV(ARMV8, EVENT_A2H) \
__PMC_EV(ARMV8, EVENT_A3H) \
__PMC_EV(ARMV8, EVENT_A4H) \
__PMC_EV(ARMV8, EVENT_A5H) \
__PMC_EV(ARMV8, EVENT_A6H) \
__PMC_EV(ARMV8, EVENT_A7H) \
__PMC_EV(ARMV8, EVENT_A8H) \
__PMC_EV(ARMV8, EVENT_A9H) \
__PMC_EV(ARMV8, EVENT_AAH) \
__PMC_EV(ARMV8, EVENT_ABH) \
__PMC_EV(ARMV8, EVENT_ACH) \
__PMC_EV(ARMV8, EVENT_ADH) \
__PMC_EV(ARMV8, EVENT_AEH) \
__PMC_EV(ARMV8, EVENT_AFH) \
__PMC_EV(ARMV8, EVENT_B0H) \
__PMC_EV(ARMV8, EVENT_B1H) \
__PMC_EV(ARMV8, EVENT_B2H) \
__PMC_EV(ARMV8, EVENT_B3H) \
__PMC_EV(ARMV8, EVENT_B4H) \
__PMC_EV(ARMV8, EVENT_B5H) \
__PMC_EV(ARMV8, EVENT_B6H) \
__PMC_EV(ARMV8, EVENT_B7H) \
__PMC_EV(ARMV8, EVENT_B8H) \
__PMC_EV(ARMV8, EVENT_B9H) \
__PMC_EV(ARMV8, EVENT_BAH) \
__PMC_EV(ARMV8, EVENT_BBH) \
__PMC_EV(ARMV8, EVENT_BCH) \
__PMC_EV(ARMV8, EVENT_BDH) \
__PMC_EV(ARMV8, EVENT_BEH) \
__PMC_EV(ARMV8, EVENT_BFH) \
__PMC_EV(ARMV8, EVENT_C0H) \
__PMC_EV(ARMV8, EVENT_C1H) \
__PMC_EV(ARMV8, EVENT_C2H) \
__PMC_EV(ARMV8, EVENT_C3H) \
__PMC_EV(ARMV8, EVENT_C4H) \
__PMC_EV(ARMV8, EVENT_C5H) \
__PMC_EV(ARMV8, EVENT_C6H) \
__PMC_EV(ARMV8, EVENT_C7H) \
__PMC_EV(ARMV8, EVENT_C8H) \
__PMC_EV(ARMV8, EVENT_C9H) \
__PMC_EV(ARMV8, EVENT_CAH) \
__PMC_EV(ARMV8, EVENT_CBH) \
__PMC_EV(ARMV8, EVENT_CCH) \
__PMC_EV(ARMV8, EVENT_CDH) \
__PMC_EV(ARMV8, EVENT_CEH) \
__PMC_EV(ARMV8, EVENT_CFH) \
__PMC_EV(ARMV8, EVENT_D0H) \
__PMC_EV(ARMV8, EVENT_D1H) \
__PMC_EV(ARMV8, EVENT_D2H) \
__PMC_EV(ARMV8, EVENT_D3H) \
__PMC_EV(ARMV8, EVENT_D4H) \
__PMC_EV(ARMV8, EVENT_D5H) \
__PMC_EV(ARMV8, EVENT_D6H) \
__PMC_EV(ARMV8, EVENT_D7H) \
__PMC_EV(ARMV8, EVENT_D8H) \
__PMC_EV(ARMV8, EVENT_D9H) \
__PMC_EV(ARMV8, EVENT_DAH) \
__PMC_EV(ARMV8, EVENT_DBH) \
__PMC_EV(ARMV8, EVENT_DCH) \
__PMC_EV(ARMV8, EVENT_DDH) \
__PMC_EV(ARMV8, EVENT_DEH) \
__PMC_EV(ARMV8, EVENT_DFH) \
__PMC_EV(ARMV8, EVENT_E0H) \
__PMC_EV(ARMV8, EVENT_E1H) \
__PMC_EV(ARMV8, EVENT_E2H) \
__PMC_EV(ARMV8, EVENT_E3H) \
__PMC_EV(ARMV8, EVENT_E4H) \
__PMC_EV(ARMV8, EVENT_E5H) \
__PMC_EV(ARMV8, EVENT_E6H) \
__PMC_EV(ARMV8, EVENT_E7H) \
__PMC_EV(ARMV8, EVENT_E8H) \
__PMC_EV(ARMV8, EVENT_E9H) \
__PMC_EV(ARMV8, EVENT_EAH) \
__PMC_EV(ARMV8, EVENT_EBH) \
__PMC_EV(ARMV8, EVENT_ECH) \
__PMC_EV(ARMV8, EVENT_EDH) \
__PMC_EV(ARMV8, EVENT_EEH) \
__PMC_EV(ARMV8, EVENT_EFH) \
__PMC_EV(ARMV8, EVENT_F0H) \
__PMC_EV(ARMV8, EVENT_F1H) \
__PMC_EV(ARMV8, EVENT_F2H) \
__PMC_EV(ARMV8, EVENT_F3H) \
__PMC_EV(ARMV8, EVENT_F4H) \
__PMC_EV(ARMV8, EVENT_F5H) \
__PMC_EV(ARMV8, EVENT_F6H) \
__PMC_EV(ARMV8, EVENT_F7H) \
__PMC_EV(ARMV8, EVENT_F8H) \
__PMC_EV(ARMV8, EVENT_F9H) \
__PMC_EV(ARMV8, EVENT_FAH) \
__PMC_EV(ARMV8, EVENT_FBH) \
__PMC_EV(ARMV8, EVENT_FCH) \
__PMC_EV(ARMV8, EVENT_FDH) \
__PMC_EV(ARMV8, EVENT_FEH) \
__PMC_EV(ARMV8, EVENT_FFH)
#define PMC_EV_ARMV8_FIRST PMC_EV_ARMV8_EVENT_00H
#define PMC_EV_ARMV8_LAST PMC_EV_ARMV8_EVENT_FFH
#define __PMC_EV_ALIAS_ARMV8_COMMON() \
__PMC_EV_ALIAS("SW_INCR", ARMV8_EVENT_00H) \
__PMC_EV_ALIAS("L1I_CACHE_REFILL", ARMV8_EVENT_01H) \
__PMC_EV_ALIAS("L1I_TLB_REFILL", ARMV8_EVENT_02H) \
__PMC_EV_ALIAS("L1D_CACHE_REFILL", ARMV8_EVENT_03H) \
__PMC_EV_ALIAS("L1D_CACHE", ARMV8_EVENT_04H) \
__PMC_EV_ALIAS("L1D_TLB_REFILL", ARMV8_EVENT_05H) \
__PMC_EV_ALIAS("INST_RETIRED", ARMV8_EVENT_08H) \
__PMC_EV_ALIAS("EXC_TAKEN", ARMV8_EVENT_09H) \
__PMC_EV_ALIAS("EXC_RETURN", ARMV8_EVENT_0AH) \
__PMC_EV_ALIAS("CID_WRITE_RETIRED", ARMV8_EVENT_0BH) \
__PMC_EV_ALIAS("BR_MIS_PRED", ARMV8_EVENT_10H) \
__PMC_EV_ALIAS("CPU_CYCLES", ARMV8_EVENT_11H) \
__PMC_EV_ALIAS("BR_PRED", ARMV8_EVENT_12H) \
__PMC_EV_ALIAS("MEM_ACCESS", ARMV8_EVENT_13H) \
__PMC_EV_ALIAS("L1I_CACHE", ARMV8_EVENT_14H) \
__PMC_EV_ALIAS("L1D_CACHE_WB", ARMV8_EVENT_15H) \
__PMC_EV_ALIAS("L2D_CACHE", ARMV8_EVENT_16H) \
__PMC_EV_ALIAS("L2D_CACHE_REFILL", ARMV8_EVENT_17H) \
__PMC_EV_ALIAS("L2D_CACHE_WB", ARMV8_EVENT_18H) \
__PMC_EV_ALIAS("BUS_ACCESS", ARMV8_EVENT_19H) \
__PMC_EV_ALIAS("MEMORY_ERROR", ARMV8_EVENT_1AH) \
__PMC_EV_ALIAS("BUS_CYCLES", ARMV8_EVENT_1DH) \
__PMC_EV_ALIAS("CHAIN", ARMV8_EVENT_1EH) \
__PMC_EV_ALIAS("BUS_ACCESS_LD", ARMV8_EVENT_60H) \
__PMC_EV_ALIAS("BUS_ACCESS_ST", ARMV8_EVENT_61H) \
__PMC_EV_ALIAS("BR_INDIRECT_SPEC", ARMV8_EVENT_7AH) \
__PMC_EV_ALIAS("EXC_IRQ", ARMV8_EVENT_86H) \
__PMC_EV_ALIAS("EXC_FIQ", ARMV8_EVENT_87H)
#define __PMC_EV_ALIAS_ARMV8_CORTEX_A53() \
__PMC_EV_ALIAS_ARMV8_COMMON() \
__PMC_EV_ALIAS("LD_RETIRED", ARMV8_EVENT_06H) \
__PMC_EV_ALIAS("ST_RETIRED", ARMV8_EVENT_07H) \
__PMC_EV_ALIAS("PC_WRITE_RETIRED", ARMV8_EVENT_0CH) \
__PMC_EV_ALIAS("BR_IMMED_RETIRED", ARMV8_EVENT_0DH) \
__PMC_EV_ALIAS("BR_RETURN_RETIRED", ARMV8_EVENT_0EH) \
__PMC_EV_ALIAS("UNALIGNED_LDST_RETIRED",ARMV8_EVENT_0FH)
#define __PMC_EV_ALIAS_ARMV8_CORTEX_A57() \
__PMC_EV_ALIAS_ARMV8_COMMON() \
__PMC_EV_ALIAS("INST_SPEC", ARMV8_EVENT_1BH) \
__PMC_EV_ALIAS("TTBR_WRITE_RETIRED", ARMV8_EVENT_1CH) \
__PMC_EV_ALIAS("L1D_CACHE_LD", ARMV8_EVENT_40H) \
__PMC_EV_ALIAS("L1D_CACHE_ST", ARMV8_EVENT_41H) \
__PMC_EV_ALIAS("L1D_CACHE_REFILL_LD", ARMV8_EVENT_42H) \
__PMC_EV_ALIAS("L1D_CACHE_REFILL_ST", ARMV8_EVENT_43H) \
__PMC_EV_ALIAS("L1D_CACHE_WB_VICTIM", ARMV8_EVENT_46H) \
__PMC_EV_ALIAS("L1D_CACHE_WB_CLEAN", ARMV8_EVENT_47H) \
__PMC_EV_ALIAS("L1D_CACHE_INVAL", ARMV8_EVENT_48H) \
__PMC_EV_ALIAS("L1D_TLB_REFILL_LD", ARMV8_EVENT_4CH) \
__PMC_EV_ALIAS("L1D_TLB_REFILL_ST", ARMV8_EVENT_4DH) \
__PMC_EV_ALIAS("L2D_CACHE_LD", ARMV8_EVENT_50H) \
__PMC_EV_ALIAS("L2D_CACHE_ST", ARMV8_EVENT_51H) \
__PMC_EV_ALIAS("L2D_CACHE_REFILL_LD", ARMV8_EVENT_52H) \
__PMC_EV_ALIAS("L2D_CACHE_REFILL_ST", ARMV8_EVENT_53H) \
__PMC_EV_ALIAS("L2D_CACHE_WB_VICTIM", ARMV8_EVENT_56H) \
__PMC_EV_ALIAS("L2D_CACHE_WB_CLEAN", ARMV8_EVENT_57H) \
__PMC_EV_ALIAS("L2D_CACHE_INVAL", ARMV8_EVENT_58H) \
__PMC_EV_ALIAS("BUS_ACCESS_SHARED", ARMV8_EVENT_62H) \
__PMC_EV_ALIAS("BUS_ACCESS_NOT_SHARED", ARMV8_EVENT_63H) \
__PMC_EV_ALIAS("BUS_ACCESS_NORMAL", ARMV8_EVENT_64H) \
__PMC_EV_ALIAS("BUS_ACCESS_PERIPH", ARMV8_EVENT_65H) \
__PMC_EV_ALIAS("MEM_ACCESS_LD", ARMV8_EVENT_66H) \
__PMC_EV_ALIAS("MEM_ACCESS_ST", ARMV8_EVENT_67H) \
__PMC_EV_ALIAS("UNALIGNED_LD_SPEC", ARMV8_EVENT_68H) \
__PMC_EV_ALIAS("UNALIGNED_ST_SPEC", ARMV8_EVENT_69H) \
__PMC_EV_ALIAS("UNALIGNED_LDST_SPEC", ARMV8_EVENT_6AH) \
__PMC_EV_ALIAS("LDREX_SPEC", ARMV8_EVENT_6CH) \
__PMC_EV_ALIAS("STREX_PASS_SPEC", ARMV8_EVENT_6DH) \
__PMC_EV_ALIAS("STREX_FAIL_SPEC", ARMV8_EVENT_6EH) \
__PMC_EV_ALIAS("LD_SPEC", ARMV8_EVENT_70H) \
__PMC_EV_ALIAS("ST_SPEC", ARMV8_EVENT_71H) \
__PMC_EV_ALIAS("LDST_SPEC", ARMV8_EVENT_72H) \
__PMC_EV_ALIAS("DP_SPEC", ARMV8_EVENT_73H) \
__PMC_EV_ALIAS("ASE_SPEC", ARMV8_EVENT_74H) \
__PMC_EV_ALIAS("VFP_SPEC", ARMV8_EVENT_75H) \
__PMC_EV_ALIAS("PC_WRITE_SPEC", ARMV8_EVENT_76H) \
__PMC_EV_ALIAS("CRYPTO_SPEC", ARMV8_EVENT_77H) \
__PMC_EV_ALIAS("BR_IMMED_SPEC", ARMV8_EVENT_78H) \
__PMC_EV_ALIAS("BR_RETURN_SPEC", ARMV8_EVENT_79H) \
__PMC_EV_ALIAS("ISB_SPEC", ARMV8_EVENT_7CH) \
__PMC_EV_ALIAS("DSB_SPEC", ARMV8_EVENT_7DH) \
__PMC_EV_ALIAS("DMB_SPEC", ARMV8_EVENT_7EH) \
__PMC_EV_ALIAS("EXC_UNDEF", ARMV8_EVENT_81H) \
__PMC_EV_ALIAS("EXC_SVC", ARMV8_EVENT_82H) \
__PMC_EV_ALIAS("EXC_PABORT", ARMV8_EVENT_83H) \
__PMC_EV_ALIAS("EXC_DABORT", ARMV8_EVENT_84H) \
__PMC_EV_ALIAS("EXC_SMC", ARMV8_EVENT_88H) \
__PMC_EV_ALIAS("EXC_HVC", ARMV8_EVENT_8AH) \
__PMC_EV_ALIAS("EXC_TRAP_PABORT", ARMV8_EVENT_8BH) \
__PMC_EV_ALIAS("EXC_TRAP_DABORT", ARMV8_EVENT_8CH) \
__PMC_EV_ALIAS("EXC_TRAP_OTHER", ARMV8_EVENT_8DH) \
__PMC_EV_ALIAS("EXC_TRAP_IRQ", ARMV8_EVENT_8EH) \
__PMC_EV_ALIAS("EXC_TRAP_FIQ", ARMV8_EVENT_8FH) \
__PMC_EV_ALIAS("RC_LD_SPEC", ARMV8_EVENT_90H) \
__PMC_EV_ALIAS("RC_ST_SPEC", ARMV8_EVENT_91H)
Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor. Add macros for properly accessing coprocessor 0 registers that support performance counters. Reviewed by: jkoshy rpaulo fabien imp MFC after: 1 month
2010-03-03 15:05:58 +00:00
/*
* MIPS Events from "Programming the MIPS32 24K Core Family",
* Document Number: MD00355 Revision 04.63 December 19, 2008
* These events are kept in the order found in Table 7.4.
* For counters which are different between the left hand
* column (0/2) and the right hand column (1/3) the left
* hand is given first, e.g. BRANCH_COMPLETED and BRANCH_MISPRED
* in the definition below.
*/
#define __PMC_EV_MIPS24K() \
__PMC_EV(MIPS24K, CYCLE) \
__PMC_EV(MIPS24K, INSTR_EXECUTED) \
__PMC_EV(MIPS24K, BRANCH_COMPLETED) \
__PMC_EV(MIPS24K, BRANCH_MISPRED) \
__PMC_EV(MIPS24K, RETURN) \
__PMC_EV(MIPS24K, RETURN_MISPRED) \
__PMC_EV(MIPS24K, RETURN_NOT_31) \
__PMC_EV(MIPS24K, RETURN_NOTPRED) \
__PMC_EV(MIPS24K, ITLB_ACCESS) \
__PMC_EV(MIPS24K, ITLB_MISS) \
__PMC_EV(MIPS24K, DTLB_ACCESS) \
__PMC_EV(MIPS24K, DTLB_MISS) \
__PMC_EV(MIPS24K, JTLB_IACCESS) \
__PMC_EV(MIPS24K, JTLB_IMISS) \
__PMC_EV(MIPS24K, JTLB_DACCESS) \
__PMC_EV(MIPS24K, JTLB_DMISS) \
__PMC_EV(MIPS24K, IC_FETCH) \
__PMC_EV(MIPS24K, IC_MISS) \
__PMC_EV(MIPS24K, DC_LOADSTORE) \
__PMC_EV(MIPS24K, DC_WRITEBACK) \
__PMC_EV(MIPS24K, DC_MISS) \
__PMC_EV(MIPS24K, STORE_MISS) \
__PMC_EV(MIPS24K, LOAD_MISS) \
__PMC_EV(MIPS24K, INTEGER_COMPLETED) \
__PMC_EV(MIPS24K, FP_COMPLETED) \
__PMC_EV(MIPS24K, LOAD_COMPLETED) \
__PMC_EV(MIPS24K, STORE_COMPLETED) \
__PMC_EV(MIPS24K, BARRIER_COMPLETED) \
__PMC_EV(MIPS24K, MIPS16_COMPLETED) \
__PMC_EV(MIPS24K, NOP_COMPLETED) \
__PMC_EV(MIPS24K, INTEGER_MULDIV_COMPLETED)\
__PMC_EV(MIPS24K, RF_STALL) \
__PMC_EV(MIPS24K, INSTR_REFETCH) \
__PMC_EV(MIPS24K, STORE_COND_COMPLETED) \
__PMC_EV(MIPS24K, STORE_COND_FAILED) \
__PMC_EV(MIPS24K, ICACHE_REQUESTS) \
__PMC_EV(MIPS24K, ICACHE_HIT) \
__PMC_EV(MIPS24K, L2_WRITEBACK) \
__PMC_EV(MIPS24K, L2_ACCESS) \
__PMC_EV(MIPS24K, L2_MISS) \
__PMC_EV(MIPS24K, L2_ERR_CORRECTED) \
__PMC_EV(MIPS24K, EXCEPTIONS) \
__PMC_EV(MIPS24K, RF_CYCLES_STALLED) \
__PMC_EV(MIPS24K, IFU_CYCLES_STALLED) \
__PMC_EV(MIPS24K, ALU_CYCLES_STALLED) \
__PMC_EV(MIPS24K, UNCACHED_LOAD) \
__PMC_EV(MIPS24K, UNCACHED_STORE) \
__PMC_EV(MIPS24K, CP2_REG_TO_REG_COMPLETED)\
__PMC_EV(MIPS24K, MFTC_COMPLETED) \
__PMC_EV(MIPS24K, IC_BLOCKED_CYCLES) \
__PMC_EV(MIPS24K, DC_BLOCKED_CYCLES) \
__PMC_EV(MIPS24K, L2_IMISS_STALL_CYCLES) \
__PMC_EV(MIPS24K, L2_DMISS_STALL_CYCLES) \
__PMC_EV(MIPS24K, DMISS_CYCLES) \
__PMC_EV(MIPS24K, L2_MISS_CYCLES) \
__PMC_EV(MIPS24K, UNCACHED_BLOCK_CYCLES) \
__PMC_EV(MIPS24K, MDU_STALL_CYCLES) \
__PMC_EV(MIPS24K, FPU_STALL_CYCLES) \
__PMC_EV(MIPS24K, CP2_STALL_CYCLES) \
__PMC_EV(MIPS24K, COREXTEND_STALL_CYCLES) \
__PMC_EV(MIPS24K, ISPRAM_STALL_CYCLES) \
__PMC_EV(MIPS24K, DSPRAM_STALL_CYCLES) \
__PMC_EV(MIPS24K, CACHE_STALL_CYCLES) \
__PMC_EV(MIPS24K, LOAD_TO_USE_STALLS) \
__PMC_EV(MIPS24K, BASE_MISPRED_STALLS) \
__PMC_EV(MIPS24K, CPO_READ_STALLS) \
__PMC_EV(MIPS24K, BRANCH_MISPRED_CYCLES) \
__PMC_EV(MIPS24K, IFETCH_BUFFER_FULL) \
__PMC_EV(MIPS24K, FETCH_BUFFER_ALLOCATED) \
__PMC_EV(MIPS24K, EJTAG_ITRIGGER) \
__PMC_EV(MIPS24K, EJTAG_DTRIGGER) \
__PMC_EV(MIPS24K, FSB_LT_QUARTER) \
__PMC_EV(MIPS24K, FSB_QUARTER_TO_HALF) \
__PMC_EV(MIPS24K, FSB_GT_HALF) \
__PMC_EV(MIPS24K, FSB_FULL_PIPELINE_STALLS)\
__PMC_EV(MIPS24K, LDQ_LT_QUARTER) \
__PMC_EV(MIPS24K, LDQ_QUARTER_TO_HALF) \
__PMC_EV(MIPS24K, LDQ_GT_HALF) \
__PMC_EV(MIPS24K, LDQ_FULL_PIPELINE_STALLS)\
__PMC_EV(MIPS24K, WBB_LT_QUARTER) \
__PMC_EV(MIPS24K, WBB_QUARTER_TO_HALF) \
__PMC_EV(MIPS24K, WBB_GT_HALF) \
__PMC_EV(MIPS24K, WBB_FULL_PIPELINE_STALLS) \
__PMC_EV(MIPS24K, REQUEST_LATENCY) \
__PMC_EV(MIPS24K, REQUEST_COUNT)
#define PMC_EV_MIPS24K_FIRST PMC_EV_MIPS24K_CYCLE
#define PMC_EV_MIPS24K_LAST PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS
Add support for the MIPS74K SoC family performance counters events. These are similar to the mips24k performance counters - some are available on perfcnt0/3, some are available on perfcnt1/4. However, the events aren't all the same. * Add the events, named the same as from Linux oprofile. * Verify they're the same as "MIPS32(R) 74KTM Processor Core Family Software User's Manual"; Document Number: MD00519; Revision 01.05. * Rename INSTRUCTIONS to something else, so it doesn't clash with the alias INSTRUCTIONS. I'll try to tidy this up later; there are a few other aliases to add and shuffle around. Tested: * QCA9558 SoC (AP135 board) - MIPS74Kc core (no FPU.) * make universe; where it didn't fail for other reasons. TODO: * It'd be nice to support the four performance counters in at least this hardware, rather than just two. Reviewed by: bsdimp ("looks good; don't break world".)
2015-04-05 02:57:02 +00:00
/*
* MIPS74k events. Similar to MIPS24k, the arrangement
* is (0,2) then (1,3) events.
*/
#define __PMC_EV_MIPS74K() \
__PMC_EV(MIPS74K, CYCLES) \
__PMC_EV(MIPS74K, INSTR_EXECUTED) \
__PMC_EV(MIPS74K, PREDICTED_JR_31) \
__PMC_EV(MIPS74K, JR_31_MISPREDICTIONS) \
__PMC_EV(MIPS74K, REDIRECT_STALLS) \
__PMC_EV(MIPS74K, JR_31_NO_PREDICTIONS) \
__PMC_EV(MIPS74K, ITLB_ACCESSES) \
__PMC_EV(MIPS74K, ITLB_MISSES) \
__PMC_EV(MIPS74K, JTLB_INSN_MISSES) \
__PMC_EV(MIPS74K, ICACHE_ACCESSES) \
__PMC_EV(MIPS74K, ICACHE_MISSES) \
__PMC_EV(MIPS74K, ICACHE_MISS_STALLS) \
__PMC_EV(MIPS74K, UNCACHED_IFETCH_STALLS) \
__PMC_EV(MIPS74K, PDTRACE_BACK_STALLS) \
__PMC_EV(MIPS74K, IFU_REPLAYS) \
__PMC_EV(MIPS74K, KILLED_FETCH_SLOTS) \
__PMC_EV(MIPS74K, IFU_IDU_MISS_PRED_UPSTREAM_CYCLES) \
__PMC_EV(MIPS74K, IFU_IDU_NO_FETCH_CYCLES) \
__PMC_EV(MIPS74K, IFU_IDU_CLOGED_DOWNSTREAM_CYCLES) \
__PMC_EV(MIPS74K, DDQ0_FULL_DR_STALLS) \
__PMC_EV(MIPS74K, DDQ1_FULL_DR_STALLS) \
__PMC_EV(MIPS74K, ALCB_FULL_DR_STALLS) \
__PMC_EV(MIPS74K, AGCB_FULL_DR_STALLS) \
__PMC_EV(MIPS74K, CLDQ_FULL_DR_STALLS) \
__PMC_EV(MIPS74K, IODQ_FULL_DR_STALLS) \
__PMC_EV(MIPS74K, ALU_EMPTY_CYCLES) \
__PMC_EV(MIPS74K, AGEN_EMPTY_CYCLES) \
__PMC_EV(MIPS74K, ALU_OPERANDS_NOT_READY_CYCLES) \
__PMC_EV(MIPS74K, AGEN_OPERANDS_NOT_READY_CYCLES) \
__PMC_EV(MIPS74K, ALU_NO_ISSUES_CYCLES) \
__PMC_EV(MIPS74K, AGEN_NO_ISSUES_CYCLES) \
__PMC_EV(MIPS74K, ALU_BUBBLE_CYCLES) \
__PMC_EV(MIPS74K, AGEN_BUBBLE_CYCLES) \
__PMC_EV(MIPS74K, SINGLE_ISSUE_CYCLES) \
__PMC_EV(MIPS74K, DUAL_ISSUE_CYCLES) \
__PMC_EV(MIPS74K, OOO_ALU_ISSUE_CYCLES) \
__PMC_EV(MIPS74K, OOO_AGEN_ISSUE_CYCLES) \
__PMC_EV(MIPS74K, JALR_JALR_HB_INSNS) \
__PMC_EV(MIPS74K, DCACHE_LINE_REFILL_REQUESTS) \
__PMC_EV(MIPS74K, DCACHE_LOAD_ACCESSES) \
__PMC_EV(MIPS74K, DCACHE_ACCESSES) \
__PMC_EV(MIPS74K, DCACHE_WRITEBACKS) \
__PMC_EV(MIPS74K, DCACHE_MISSES) \
__PMC_EV(MIPS74K, JTLB_DATA_ACCESSES) \
__PMC_EV(MIPS74K, JTLB_DATA_MISSES) \
__PMC_EV(MIPS74K, LOAD_STORE_REPLAYS) \
__PMC_EV(MIPS74K, VA_TRANSALTION_CORNER_CASES) \
__PMC_EV(MIPS74K, LOAD_STORE_BLOCKED_CYCLES) \
__PMC_EV(MIPS74K, LOAD_STORE_NO_FILL_REQUESTS) \
__PMC_EV(MIPS74K, L2_CACHE_WRITEBACKS) \
__PMC_EV(MIPS74K, L2_CACHE_ACCESSES) \
__PMC_EV(MIPS74K, L2_CACHE_MISSES) \
__PMC_EV(MIPS74K, L2_CACHE_MISS_CYCLES) \
__PMC_EV(MIPS74K, FSB_FULL_STALLS) \
__PMC_EV(MIPS74K, FSB_OVER_50_FULL) \
__PMC_EV(MIPS74K, LDQ_FULL_STALLS) \
__PMC_EV(MIPS74K, LDQ_OVER_50_FULL) \
__PMC_EV(MIPS74K, WBB_FULL_STALLS) \
__PMC_EV(MIPS74K, WBB_OVER_50_FULL) \
__PMC_EV(MIPS74K, LOAD_MISS_CONSUMER_REPLAYS) \
__PMC_EV(MIPS74K, CP1_CP2_LOAD_INSNS) \
__PMC_EV(MIPS74K, JR_NON_31_INSNS) \
__PMC_EV(MIPS74K, MISPREDICTED_JR_31_INSNS) \
__PMC_EV(MIPS74K, BRANCH_INSNS) \
__PMC_EV(MIPS74K, CP1_CP2_COND_BRANCH_INSNS) \
__PMC_EV(MIPS74K, BRANCH_LIKELY_INSNS) \
__PMC_EV(MIPS74K, MISPREDICTED_BRANCH_LIKELY_INSNS) \
__PMC_EV(MIPS74K, COND_BRANCH_INSNS) \
__PMC_EV(MIPS74K, MISPREDICTED_BRANCH_INSNS) \
__PMC_EV(MIPS74K, INTEGER_INSNS) \
__PMC_EV(MIPS74K, FPU_INSNS) \
__PMC_EV(MIPS74K, LOAD_INSNS) \
__PMC_EV(MIPS74K, STORE_INSNS) \
__PMC_EV(MIPS74K, J_JAL_INSNS) \
__PMC_EV(MIPS74K, MIPS16_INSNS) \
__PMC_EV(MIPS74K, NOP_INSNS) \
__PMC_EV(MIPS74K, NT_MUL_DIV_INSNS) \
__PMC_EV(MIPS74K, DSP_INSNS) \
__PMC_EV(MIPS74K, ALU_DSP_SATURATION_INSNS) \
__PMC_EV(MIPS74K, DSP_BRANCH_INSNS) \
__PMC_EV(MIPS74K, MDU_DSP_SATURATION_INSNS) \
__PMC_EV(MIPS74K, UNCACHED_LOAD_INSNS) \
__PMC_EV(MIPS74K, UNCACHED_STORE_INSNS) \
__PMC_EV(MIPS74K, EJTAG_INSN_TRIGGERS) \
__PMC_EV(MIPS74K, CP1_BRANCH_MISPREDICTIONS) \
__PMC_EV(MIPS74K, SC_INSNS) \
__PMC_EV(MIPS74K, FAILED_SC_INSNS) \
__PMC_EV(MIPS74K, PREFETCH_INSNS) \
__PMC_EV(MIPS74K, CACHE_HIT_PREFETCH_INSNS) \
__PMC_EV(MIPS74K, NO_INSN_CYCLES) \
__PMC_EV(MIPS74K, LOAD_MISS_INSNS) \
__PMC_EV(MIPS74K, ONE_INSN_CYCLES) \
__PMC_EV(MIPS74K, TWO_INSNS_CYCLES) \
__PMC_EV(MIPS74K, GFIFO_BLOCKED_CYCLES) \
__PMC_EV(MIPS74K, CP1_CP2_STORE_INSNS) \
__PMC_EV(MIPS74K, MISPREDICTION_STALLS) \
__PMC_EV(MIPS74K, MISPREDICTED_BRANCH_INSNS_CYCLES) \
__PMC_EV(MIPS74K, EXCEPTIONS_TAKEN) \
__PMC_EV(MIPS74K, GRADUATION_REPLAYS) \
__PMC_EV(MIPS74K, COREEXTEND_EVENTS) \
__PMC_EV(MIPS74K, ISPRAM_EVENTS) \
__PMC_EV(MIPS74K, DSPRAM_EVENTS) \
__PMC_EV(MIPS74K, L2_CACHE_SINGLE_BIT_ERRORS) \
__PMC_EV(MIPS74K, SYSTEM_EVENT_0) \
__PMC_EV(MIPS74K, SYSTEM_EVENT_1) \
__PMC_EV(MIPS74K, SYSTEM_EVENT_2) \
__PMC_EV(MIPS74K, SYSTEM_EVENT_3) \
__PMC_EV(MIPS74K, SYSTEM_EVENT_4) \
__PMC_EV(MIPS74K, SYSTEM_EVENT_5) \
__PMC_EV(MIPS74K, SYSTEM_EVENT_6) \
__PMC_EV(MIPS74K, SYSTEM_EVENT_7) \
__PMC_EV(MIPS74K, OCP_ALL_REQUESTS) \
__PMC_EV(MIPS74K, OCP_ALL_CACHEABLE_REQUESTS) \
__PMC_EV(MIPS74K, OCP_READ_REQUESTS) \
__PMC_EV(MIPS74K, OCP_READ_CACHEABLE_REQUESTS) \
__PMC_EV(MIPS74K, OCP_WRITE_REQUESTS) \
__PMC_EV(MIPS74K, OCP_WRITE_CACHEABLE_REQUESTS) \
__PMC_EV(MIPS74K, FSB_LESS_25_FULL) \
__PMC_EV(MIPS74K, FSB_25_50_FULL) \
__PMC_EV(MIPS74K, LDQ_LESS_25_FULL) \
__PMC_EV(MIPS74K, LDQ_25_50_FULL) \
__PMC_EV(MIPS74K, WBB_LESS_25_FULL) \
__PMC_EV(MIPS74K, WBB_25_50_FULL)
#define PMC_EV_MIPS74K_FIRST PMC_EV_MIPS74K_CYCLES
#define PMC_EV_MIPS74K_LAST PMC_EV_MIPS74K_WBB_25_50_FULL
Add list of Octeon's PMC counters obtained from cvmx-core.h
2012-03-23 00:04:09 +00:00
/*
* Cavium Octeon counters. Obtained from cvmx-core.h
*/
#define __PMC_EV_OCTEON() \
__PMC_EV(OCTEON, CLK) \
__PMC_EV(OCTEON, ISSUE) \
__PMC_EV(OCTEON, RET) \
__PMC_EV(OCTEON, NISSUE) \
__PMC_EV(OCTEON, SISSUE) \
__PMC_EV(OCTEON, DISSUE) \
__PMC_EV(OCTEON, IFI) \
__PMC_EV(OCTEON, BR) \
__PMC_EV(OCTEON, BRMIS) \
__PMC_EV(OCTEON, J) \
__PMC_EV(OCTEON, JMIS) \
__PMC_EV(OCTEON, REPLAY) \
__PMC_EV(OCTEON, IUNA) \
__PMC_EV(OCTEON, TRAP) \
__PMC_EV(OCTEON, UULOAD) \
__PMC_EV(OCTEON, UUSTORE) \
__PMC_EV(OCTEON, ULOAD) \
__PMC_EV(OCTEON, USTORE) \
__PMC_EV(OCTEON, EC) \
__PMC_EV(OCTEON, MC) \
__PMC_EV(OCTEON, CC) \
__PMC_EV(OCTEON, CSRC) \
__PMC_EV(OCTEON, CFETCH) \
__PMC_EV(OCTEON, CPREF) \
__PMC_EV(OCTEON, ICA) \
__PMC_EV(OCTEON, II) \
__PMC_EV(OCTEON, IP) \
__PMC_EV(OCTEON, CIMISS) \
__PMC_EV(OCTEON, WBUF) \
__PMC_EV(OCTEON, WDAT) \
__PMC_EV(OCTEON, WBUFLD) \
__PMC_EV(OCTEON, WBUFFL) \
__PMC_EV(OCTEON, WBUFTR) \
__PMC_EV(OCTEON, BADD) \
__PMC_EV(OCTEON, BADDL2) \
__PMC_EV(OCTEON, BFILL) \
__PMC_EV(OCTEON, DDIDS) \
__PMC_EV(OCTEON, IDIDS) \
__PMC_EV(OCTEON, DIDNA) \
__PMC_EV(OCTEON, LDS) \
__PMC_EV(OCTEON, LMLDS) \
__PMC_EV(OCTEON, IOLDS) \
__PMC_EV(OCTEON, DMLDS) \
__PMC_EV(OCTEON, STS) \
__PMC_EV(OCTEON, LMSTS) \
__PMC_EV(OCTEON, IOSTS) \
__PMC_EV(OCTEON, IOBDMA) \
__PMC_EV(OCTEON, DTLB) \
__PMC_EV(OCTEON, DTLBAD) \
__PMC_EV(OCTEON, ITLB) \
__PMC_EV(OCTEON, SYNC) \
__PMC_EV(OCTEON, SYNCIOB) \
__PMC_EV(OCTEON, SYNCW)
#define PMC_EV_OCTEON_FIRST PMC_EV_OCTEON_CLK
#define PMC_EV_OCTEON_LAST PMC_EV_OCTEON_SYNCW
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
#define __PMC_EV_PPC7450() \
__PMC_EV(PPC7450, CYCLE) \
__PMC_EV(PPC7450, INSTR_COMPLETED) \
__PMC_EV(PPC7450, TLB_BIT_TRANSITIONS) \
__PMC_EV(PPC7450, INSTR_DISPATCHED) \
__PMC_EV(PPC7450, PMON_EXCEPT) \
__PMC_EV(PPC7450, PMON_SIG) \
__PMC_EV(PPC7450, VPU_INSTR_COMPLETED) \
__PMC_EV(PPC7450, VFPU_INSTR_COMPLETED) \
__PMC_EV(PPC7450, VIU1_INSTR_COMPLETED) \
__PMC_EV(PPC7450, VIU2_INSTR_COMPLETED) \
__PMC_EV(PPC7450, MTVSCR_INSTR_COMPLETED) \
__PMC_EV(PPC7450, MTVRSAVE_INSTR_COMPLETED) \
__PMC_EV(PPC7450, VPU_INSTR_WAIT_CYCLES) \
__PMC_EV(PPC7450, VFPU_INSTR_WAIT_CYCLES) \
__PMC_EV(PPC7450, VIU1_INSTR_WAIT_CYCLES) \
__PMC_EV(PPC7450, VIU2_INSTR_WAIT_CYCLES) \
__PMC_EV(PPC7450, MFVSCR_SYNC_CYCLES) \
__PMC_EV(PPC7450, VSCR_SAT_SET) \
__PMC_EV(PPC7450, STORE_INSTR_COMPLETED) \
__PMC_EV(PPC7450, L1_INSTR_CACHE_MISSES) \
__PMC_EV(PPC7450, L1_DATA_SNOOPS) \
__PMC_EV(PPC7450, UNRESOLVED_BRANCHES) \
__PMC_EV(PPC7450, SPEC_BUFFER_CYCLES) \
__PMC_EV(PPC7450, BRANCH_UNIT_STALL_CYCLES) \
__PMC_EV(PPC7450, TRUE_BRANCH_TARGET_HITS) \
__PMC_EV(PPC7450, BRANCH_LINK_STAC_PREDICTED) \
__PMC_EV(PPC7450, GPR_ISSUE_QUEUE_DISPATCHES) \
__PMC_EV(PPC7450, CYCLES_THREE_INSTR_DISPATCHED) \
__PMC_EV(PPC7450, THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES) \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV(PPC7450, THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(PPC7450, CYCLES_NO_COMPLETED_INSTRS) \
__PMC_EV(PPC7450, IU2_INSTR_COMPLETED) \
__PMC_EV(PPC7450, BRANCHES_COMPLETED) \
__PMC_EV(PPC7450, EIEIO_INSTR_COMPLETED) \
__PMC_EV(PPC7450, MTSPR_INSTR_COMPLETED) \
__PMC_EV(PPC7450, SC_INSTR_COMPLETED) \
__PMC_EV(PPC7450, LS_LM_COMPLETED) \
__PMC_EV(PPC7450, ITLB_HW_TABLE_SEARCH_CYCLES) \
__PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD) \
__PMC_EV(PPC7450, L1_INSTR_CACHE_ACCESSES) \
__PMC_EV(PPC7450, INSTR_BKPT_MATCHES) \
__PMC_EV(PPC7450, L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD)\
__PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_ON_MODIFIED) \
__PMC_EV(PPC7450, LOAD_MISS_ALIAS) \
__PMC_EV(PPC7450, LOAD_MISS_ALIAS_ON_TOUCH) \
__PMC_EV(PPC7450, TOUCH_ALIAS) \
__PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT_QUEUE) \
__PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT) \
__PMC_EV(PPC7450, L1_DATA_SNOOP_HITS) \
__PMC_EV(PPC7450, WRITE_THROUGH_STORES) \
__PMC_EV(PPC7450, CACHE_INHIBITED_STORES) \
__PMC_EV(PPC7450, L1_DATA_LOAD_HIT) \
__PMC_EV(PPC7450, L1_DATA_TOUCH_HIT) \
__PMC_EV(PPC7450, L1_DATA_STORE_HIT) \
__PMC_EV(PPC7450, L1_DATA_TOTAL_HITS) \
__PMC_EV(PPC7450, DST_INSTR_DISPATCHED) \
__PMC_EV(PPC7450, REFRESHED_DSTS) \
__PMC_EV(PPC7450, SUCCESSFUL_DST_TABLE_SEARCHES) \
__PMC_EV(PPC7450, DSS_INSTR_COMPLETED) \
__PMC_EV(PPC7450, DST_STREAM_0_CACHE_LINE_FETCHES) \
__PMC_EV(PPC7450, VTQ_SUSPENDS_DUE_TO_CTX_CHANGE) \
__PMC_EV(PPC7450, VTQ_LINE_FETCH_HIT) \
__PMC_EV(PPC7450, VEC_LOAD_INSTR_COMPLETED) \
__PMC_EV(PPC7450, FP_STORE_INSTR_COMPLETED_IN_LSU) \
__PMC_EV(PPC7450, FPU_RENORMALIZATION) \
__PMC_EV(PPC7450, FPU_DENORMALIZATION) \
__PMC_EV(PPC7450, FP_STORE_CAUSES_STALL_IN_LSU) \
__PMC_EV(PPC7450, LD_ST_TRUE_ALIAS_STALL) \
__PMC_EV(PPC7450, LSU_INDEXED_ALIAS_STALL) \
__PMC_EV(PPC7450, LSU_ALIAS_VS_FSQ_WB0_WB1) \
__PMC_EV(PPC7450, LSU_ALIAS_VS_CSQ) \
__PMC_EV(PPC7450, LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0) \
__PMC_EV(PPC7450, LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0) \
__PMC_EV(PPC7450, LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1) \
__PMC_EV(PPC7450, LSU_TOUCH_ALIAS_VS_CSQ) \
__PMC_EV(PPC7450, LSU_LMQ_FULL_STALL) \
__PMC_EV(PPC7450, FP_LOAD_INSTR_COMPLETED_IN_LSU) \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV(PPC7450, FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(PPC7450, FP_LOAD_DOUBLE_COMPLETED_IN_LSU) \
__PMC_EV(PPC7450, LSU_RA_LATCH_STALL) \
__PMC_EV(PPC7450, LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL) \
__PMC_EV(PPC7450, LSU_LMQ_INDEX_ALIAS) \
__PMC_EV(PPC7450, LSU_STORE_QUEUE_INDEX_ALIAS) \
__PMC_EV(PPC7450, LSU_CSQ_FORWARDING) \
__PMC_EV(PPC7450, LSU_MISALIGNED_LOAD_FINISH) \
__PMC_EV(PPC7450, LSU_MISALIGN_STORE_COMPLETED) \
__PMC_EV(PPC7450, LSU_MISALIGN_STALL) \
__PMC_EV(PPC7450, FP_ONE_QUARTER_FPSCR_RENAMES_BUSY) \
__PMC_EV(PPC7450, FP_ONE_HALF_FPSCR_RENAMES_BUSY) \
__PMC_EV(PPC7450, FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY) \
__PMC_EV(PPC7450, FP_ALL_FPSCR_RENAMES_BUSY) \
__PMC_EV(PPC7450, FP_DENORMALIZED_RESULT) \
__PMC_EV(PPC7450, L1_DATA_TOTAL_MISSES) \
__PMC_EV(PPC7450, DISPATCHES_TO_FPR_ISSUE_QUEUE) \
__PMC_EV(PPC7450, LSU_INSTR_COMPLETED) \
__PMC_EV(PPC7450, LOAD_INSTR_COMPLETED) \
__PMC_EV(PPC7450, SS_SM_INSTR_COMPLETED) \
__PMC_EV(PPC7450, TLBIE_INSTR_COMPLETED) \
__PMC_EV(PPC7450, LWARX_INSTR_COMPLETED) \
__PMC_EV(PPC7450, MFSPR_INSTR_COMPLETED) \
__PMC_EV(PPC7450, REFETCH_SERIALIZATION) \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV(PPC7450, COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(PPC7450, CYCLES_ONE_INSTR_DISPATCHED) \
__PMC_EV(PPC7450, CYCLES_TWO_INSTR_COMPLETED) \
__PMC_EV(PPC7450, ITLB_NON_SPECULATIVE_MISSES) \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV(PPC7450, CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(PPC7450, L1_DATA_LOAD_ACCESS_MISS) \
__PMC_EV(PPC7450, L1_DATA_TOUCH_MISS) \
__PMC_EV(PPC7450, L1_DATA_STORE_MISS) \
__PMC_EV(PPC7450, L1_DATA_TOUCH_MISS_CYCLES) \
__PMC_EV(PPC7450, L1_DATA_CYCLES_USED) \
__PMC_EV(PPC7450, DST_STREAM_1_CACHE_LINE_FETCHES) \
__PMC_EV(PPC7450, VTQ_STREAM_CANCELED_PREMATURELY) \
__PMC_EV(PPC7450, VTQ_RESUMES_DUE_TO_CTX_CHANGE) \
__PMC_EV(PPC7450, VTQ_LINE_FETCH_MISS) \
__PMC_EV(PPC7450, VTQ_LINE_FETCH) \
__PMC_EV(PPC7450, TLBIE_SNOOPS) \
__PMC_EV(PPC7450, L1_INSTR_CACHE_RELOADS) \
__PMC_EV(PPC7450, L1_DATA_CACHE_RELOADS) \
__PMC_EV(PPC7450, L1_DATA_CACHE_CASTOUTS_TO_L2) \
__PMC_EV(PPC7450, STORE_MERGE_GATHER) \
__PMC_EV(PPC7450, CACHEABLE_STORE_MERGE_TO_32_BYTES) \
__PMC_EV(PPC7450, DATA_BKPT_MATCHES) \
__PMC_EV(PPC7450, FALL_THROUGH_BRANCHES_PROCESSED) \
__PMC_EV(PPC7450, \
FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \
__PMC_EV(PPC7450, SECOND_SPECULATION_BUFFER_ACTIVE) \
__PMC_EV(PPC7450, BPU_STALL_ON_LR_DEPENDENCY) \
__PMC_EV(PPC7450, BTIC_MISS) \
__PMC_EV(PPC7450, BRANCH_LINK_STACK_CORRECTLY_RESOLVED) \
__PMC_EV(PPC7450, FPR_ISSUE_STALLED) \
__PMC_EV(PPC7450, SWITCHES_BETWEEN_PRIV_USER) \
__PMC_EV(PPC7450, LSU_COMPLETES_FP_STORE_SINGLE) \
__PMC_EV(PPC7450, VR_ISSUE_QUEUE_DISPATCHES) \
__PMC_EV(PPC7450, VR_STALLS) \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV(PPC7450, GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(PPC7450, FPR_ISSUE_QUEUE_ENTRIES) \
__PMC_EV(PPC7450, FPU_INSTR_COMPLETED) \
__PMC_EV(PPC7450, STWCX_INSTR_COMPLETED) \
__PMC_EV(PPC7450, LS_LM_INSTR_PIECES) \
__PMC_EV(PPC7450, ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD) \
__PMC_EV(PPC7450, DTLB_MISSES) \
__PMC_EV(PPC7450, CANCELLED_L1_INSTR_CACHE_MISSES) \
__PMC_EV(PPC7450, L1_DATA_CACHE_OP_HIT) \
__PMC_EV(PPC7450, L1_DATA_LOAD_MISS_CYCLES) \
__PMC_EV(PPC7450, L1_DATA_PUSHES) \
__PMC_EV(PPC7450, L1_DATA_TOTAL_MISS) \
__PMC_EV(PPC7450, VT2_FETCHES) \
__PMC_EV(PPC7450, TAKEN_BRANCHES_PROCESSED) \
__PMC_EV(PPC7450, BRANCH_FLUSHES) \
__PMC_EV(PPC7450, \
SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \
__PMC_EV(PPC7450, THIRD_SPECULATION_BUFFER_ACTIVE) \
__PMC_EV(PPC7450, BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY) \
__PMC_EV(PPC7450, FAST_BTIC_HIT) \
__PMC_EV(PPC7450, BRANCH_LINK_STACK_MISPREDICTED) \
__PMC_EV(PPC7450, CYCLES_THREE_INSTR_COMPLETED) \
__PMC_EV(PPC7450, CYCLES_NO_INSTR_DISPATCHED) \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV(PPC7450, GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(PPC7450, GPR_ISSUE_QUEUE_STALLED) \
__PMC_EV(PPC7450, IU1_INSTR_COMPLETED) \
__PMC_EV(PPC7450, DSSALL_INSTR_COMPLETED) \
__PMC_EV(PPC7450, TLBSYNC_INSTR_COMPLETED) \
__PMC_EV(PPC7450, SYNC_INSTR_COMPLETED) \
__PMC_EV(PPC7450, SS_SM_INSTR_PIECES) \
__PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES) \
__PMC_EV(PPC7450, SNOOP_RETRIES) \
__PMC_EV(PPC7450, SUCCESSFUL_STWCX) \
__PMC_EV(PPC7450, DST_STREAM_3_CACHE_LINE_FETCHES) \
__PMC_EV(PPC7450, \
THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \
__PMC_EV(PPC7450, MISPREDICTED_BRANCHES) \
__PMC_EV(PPC7450, FOLDED_BRANCHES) \
__PMC_EV(PPC7450, FP_STORE_DOUBLE_COMPLETES_IN_LSU) \
__PMC_EV(PPC7450, L2_CACHE_HITS) \
__PMC_EV(PPC7450, L3_CACHE_HITS) \
__PMC_EV(PPC7450, L2_INSTR_CACHE_MISSES) \
__PMC_EV(PPC7450, L3_INSTR_CACHE_MISSES) \
__PMC_EV(PPC7450, L2_DATA_CACHE_MISSES) \
__PMC_EV(PPC7450, L3_DATA_CACHE_MISSES) \
__PMC_EV(PPC7450, L2_LOAD_HITS) \
__PMC_EV(PPC7450, L2_STORE_HITS) \
__PMC_EV(PPC7450, L3_LOAD_HITS) \
__PMC_EV(PPC7450, L3_STORE_HITS) \
__PMC_EV(PPC7450, L2_TOUCH_HITS) \
__PMC_EV(PPC7450, L3_TOUCH_HITS) \
__PMC_EV(PPC7450, SNOOP_MODIFIED) \
__PMC_EV(PPC7450, SNOOP_VALID) \
__PMC_EV(PPC7450, INTERVENTION) \
__PMC_EV(PPC7450, L2_CACHE_MISSES) \
__PMC_EV(PPC7450, L3_CACHE_MISSES) \
__PMC_EV(PPC7450, L2_CACHE_CASTOUTS) \
__PMC_EV(PPC7450, L3_CACHE_CASTOUTS) \
__PMC_EV(PPC7450, L2SQ_FULL_CYCLES) \
__PMC_EV(PPC7450, L3SQ_FULL_CYCLES) \
__PMC_EV(PPC7450, RAQ_FULL_CYCLES) \
__PMC_EV(PPC7450, WAQ_FULL_CYCLES) \
__PMC_EV(PPC7450, L1_EXTERNAL_INTERVENTIONS) \
__PMC_EV(PPC7450, L2_EXTERNAL_INTERVENTIONS) \
__PMC_EV(PPC7450, L3_EXTERNAL_INTERVENTIONS) \
__PMC_EV(PPC7450, EXTERNAL_INTERVENTIONS) \
__PMC_EV(PPC7450, EXTERNAL_PUSHES) \
__PMC_EV(PPC7450, EXTERNAL_SNOOP_RETRY) \
__PMC_EV(PPC7450, DTQ_FULL_CYCLES) \
__PMC_EV(PPC7450, BUS_RETRY) \
__PMC_EV(PPC7450, L2_VALID_REQUEST) \
__PMC_EV(PPC7450, BORDQ_FULL) \
__PMC_EV(PPC7450, BUS_TAS_FOR_READS) \
__PMC_EV(PPC7450, BUS_TAS_FOR_WRITES) \
__PMC_EV(PPC7450, BUS_READS_NOT_RETRIED) \
__PMC_EV(PPC7450, BUS_WRITES_NOT_RETRIED) \
__PMC_EV(PPC7450, BUS_READS_WRITES_NOT_RETRIED) \
__PMC_EV(PPC7450, BUS_RETRY_DUE_TO_L1_RETRY) \
__PMC_EV(PPC7450, BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT) \
__PMC_EV(PPC7450, BUS_RETRY_DUE_TO_COLLISION) \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV(PPC7450, BUS_RETRY_DUE_TO_INTERVENTION_ORDERING) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(PPC7450, SNOOP_REQUESTS) \
__PMC_EV(PPC7450, PREFETCH_ENGINE_REQUEST) \
__PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_LOAD) \
__PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_STORE) \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH) \
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
2013-04-03 21:34:35 +00:00
__PMC_EV(PPC7450, \
PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH) \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV(PPC7450, PREFETCH_ENGINE_FULL)
#define PMC_EV_PPC7450_FIRST PMC_EV_PPC7450_CYCLE
#define PMC_EV_PPC7450_LAST PMC_EV_PPC7450_PREFETCH_ENGINE_FULL
Add hwpmc(4) support for the PowerPC 970 class processors, direct events. This also fixes asserts on removal of the module for the mpc74xx. The PowerPC 970 processors have two different types of events: direct events and indirect events. Thus far only direct events are supported. I included some documentation in the driver on how indirect events work, but support is for the future. MFC after: 1 month
2014-02-01 02:03:50 +00:00
#define __PMC_EV_PPC970() \
__PMC_EV(PPC970, INSTR_COMPLETED) \
__PMC_EV(PPC970, MARKED_GROUP_DISPATCH) \
__PMC_EV(PPC970, MARKED_STORE_COMPLETED) \
__PMC_EV(PPC970, GCT_EMPTY) \
__PMC_EV(PPC970, RUN_CYCLES) \
__PMC_EV(PPC970, OVERFLOW) \
__PMC_EV(PPC970, CYCLES) \
__PMC_EV(PPC970, THRESHOLD_TIMEOUT) \
__PMC_EV(PPC970, GROUP_DISPATCH) \
__PMC_EV(PPC970, BR_MARKED_INSTR_FINISH) \
__PMC_EV(PPC970, GCT_EMPTY_BY_SRQ_FULL) \
__PMC_EV(PPC970, STOP_COMPLETION) \
__PMC_EV(PPC970, LSU_EMPTY) \
__PMC_EV(PPC970, MARKED_STORE_WITH_INTR) \
__PMC_EV(PPC970, CYCLES_IN_SUPER) \
__PMC_EV(PPC970, VPU_MARKED_INSTR_COMPLETED) \
__PMC_EV(PPC970, FXU0_IDLE_FXU1_BUSY) \
__PMC_EV(PPC970, SRQ_EMPTY) \
__PMC_EV(PPC970, MARKED_GROUP_COMPLETED) \
__PMC_EV(PPC970, CR_MARKED_INSTR_FINISH) \
__PMC_EV(PPC970, DISPATCH_SUCCESS) \
__PMC_EV(PPC970, FXU0_IDLE_FXU1_IDLE) \
__PMC_EV(PPC970, ONE_PLUS_INSTR_COMPLETED) \
__PMC_EV(PPC970, GROUP_MARKED_IDU) \
__PMC_EV(PPC970, MARKED_GROUP_COMPLETE_TIMEOUT) \
__PMC_EV(PPC970, FXU0_BUSY_FXU1_BUSY) \
__PMC_EV(PPC970, MARKED_STORE_SENT_TO_STS) \
__PMC_EV(PPC970, FXU_MARKED_INSTR_FINISHED) \
__PMC_EV(PPC970, MARKED_GROUP_ISSUED) \
__PMC_EV(PPC970, FXU0_BUSY_FXU1_IDLE) \
__PMC_EV(PPC970, GROUP_COMPLETED) \
__PMC_EV(PPC970, FPU_MARKED_INSTR_COMPLETED) \
__PMC_EV(PPC970, MARKED_INSTR_FINISH_ANY_UNIT) \
__PMC_EV(PPC970, EXTERNAL_INTERRUPT) \
__PMC_EV(PPC970, GROUP_DISPATCH_REJECT) \
__PMC_EV(PPC970, LSU_MARKED_INSTR_FINISH) \
__PMC_EV(PPC970, TIMEBASE_EVENT) \
__PMC_EV(PPC970, LSU_COMPLETION_STALL) \
__PMC_EV(PPC970, FXU_COMPLETION_STALL) \
__PMC_EV(PPC970, DCACHE_MISS_COMPLETION_STALL) \
__PMC_EV(PPC970, FPU_COMPLETION_STALL) \
__PMC_EV(PPC970, FXU_LONG_INSTR_COMPLETION_STALL) \
__PMC_EV(PPC970, REJECT_COMPLETION_STALL) \
__PMC_EV(PPC970, FPU_LONG_INSTR_COMPLETION_STALL) \
__PMC_EV(PPC970, GCT_EMPTY_BY_ICACHE_MISS) \
__PMC_EV(PPC970, REJECT_COMPLETION_STALL_ERAT_MISS) \
__PMC_EV(PPC970, GCT_EMPTY_BY_BRANCH_MISS_PREDICT) \
__PMC_EV(PPC970, BUS_HIGH) \
__PMC_EV(PPC970, BUS_LOW) \
__PMC_EV(PPC970, ADDER)
#define PMC_EV_PPC970_FIRST PMC_EV_PPC970_INSTR_COMPLETED
#define PMC_EV_PPC970_LAST PMC_EV_PPC970_ADDER
Implement hwpmc(4) for Freescale e500 core. This supports e500v1, e500v2, and e500mc. Tested only on e500v2, but the performance counters are identical across all, with e500mc having some additional events. Relnotes: Yes
2015-04-18 21:39:17 +00:00
#define __PMC_EV_E500() \
__PMC_EV(E500, CYCLES) \
__PMC_EV(E500, INSTR_COMPLETED) \
__PMC_EV(E500, UOPS_COMPLETED) \
__PMC_EV(E500, INSTR_FETCHED) \
__PMC_EV(E500, UOPS_DECODED) \
__PMC_EV(E500, PM_EVENT_TRANSITIONS) \
__PMC_EV(E500, PM_EVENT_CYCLES) \
__PMC_EV(E500, BRANCH_INSTRS_COMPLETED) \
__PMC_EV(E500, LOAD_UOPS_COMPLETED) \
__PMC_EV(E500, STORE_UOPS_COMPLETED) \
__PMC_EV(E500, CQ_REDIRECTS) \
__PMC_EV(E500, BRANCHES_FINISHED) \
__PMC_EV(E500, TAKEN_BRANCHES_FINISHED) \
__PMC_EV(E500, FINISHED_UNCOND_BRANCHES_MISS_BTB) \
__PMC_EV(E500, BRANCH_MISPRED) \
__PMC_EV(E500, BTB_BRANCH_MISPRED_FROM_DIRECTION) \
__PMC_EV(E500, BTB_HITS_PSEUDO_HITS) \
__PMC_EV(E500, CYCLES_DECODE_STALLED) \
__PMC_EV(E500, CYCLES_ISSUE_STALLED) \
__PMC_EV(E500, CYCLES_BRANCH_ISSUE_STALLED) \
__PMC_EV(E500, CYCLES_SU1_SCHED_STALLED) \
__PMC_EV(E500, CYCLES_SU2_SCHED_STALLED) \
__PMC_EV(E500, CYCLES_MU_SCHED_STALLED) \
__PMC_EV(E500, CYCLES_LRU_SCHED_STALLED) \
__PMC_EV(E500, CYCLES_BU_SCHED_STALLED) \
__PMC_EV(E500, TOTAL_TRANSLATED) \
__PMC_EV(E500, LOADS_TRANSLATED) \
__PMC_EV(E500, STORES_TRANSLATED) \
__PMC_EV(E500, TOUCHES_TRANSLATED) \
__PMC_EV(E500, CACHEOPS_TRANSLATED) \
__PMC_EV(E500, CACHE_INHIBITED_ACCESS_TRANSLATED) \
__PMC_EV(E500, GUARDED_LOADS_TRANSLATED) \
__PMC_EV(E500, WRITE_THROUGH_STORES_TRANSLATED) \
__PMC_EV(E500, MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED) \
__PMC_EV(E500, TOTAL_ALLOCATED_TO_DLFB) \
__PMC_EV(E500, LOADS_TRANSLATED_ALLOCATED_TO_DLFB) \
__PMC_EV(E500, STORES_COMPLETED_ALLOCATED_TO_DLFB) \
__PMC_EV(E500, TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB) \
__PMC_EV(E500, STORES_COMPLETED) \
__PMC_EV(E500, DATA_L1_CACHE_LOCKS) \
__PMC_EV(E500, DATA_L1_CACHE_RELOADS) \
__PMC_EV(E500, DATA_L1_CACHE_CASTOUTS) \
__PMC_EV(E500, LOAD_MISS_DLFB_FULL) \
__PMC_EV(E500, LOAD_MISS_LDQ_FULL) \
__PMC_EV(E500, LOAD_GUARDED_MISS) \
__PMC_EV(E500, STORE_TRANSLATE_WHEN_QUEUE_FULL) \
__PMC_EV(E500, ADDRESS_COLLISION) \
__PMC_EV(E500, DATA_MMU_MISS) \
__PMC_EV(E500, DATA_MMU_BUSY) \
__PMC_EV(E500, PART2_MISALIGNED_CACHE_ACCESS) \
__PMC_EV(E500, LOAD_MISS_DLFB_FULL_CYCLES) \
__PMC_EV(E500, LOAD_MISS_LDQ_FULL_CYCLES) \
__PMC_EV(E500, LOAD_GUARDED_MISS_CYCLES) \
__PMC_EV(E500, STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES) \
__PMC_EV(E500, ADDRESS_COLLISION_CYCLES) \
__PMC_EV(E500, DATA_MMU_MISS_CYCLES) \
__PMC_EV(E500, DATA_MMU_BUSY_CYCLES) \
__PMC_EV(E500, PART2_MISALIGNED_CACHE_ACCESS_CYCLES) \
__PMC_EV(E500, INSTR_L1_CACHE_LOCKS) \
__PMC_EV(E500, INSTR_L1_CACHE_RELOADS) \
__PMC_EV(E500, INSTR_L1_CACHE_FETCHES) \
__PMC_EV(E500, INSTR_MMU_TLB4K_RELOADS) \
__PMC_EV(E500, INSTR_MMU_VSP_RELOADS) \
__PMC_EV(E500, DATA_MMU_TLB4K_RELOADS) \
__PMC_EV(E500, DATA_MMU_VSP_RELOADS) \
__PMC_EV(E500, L2MMU_MISSES) \
__PMC_EV(E500, BIU_MASTER_REQUESTS) \
__PMC_EV(E500, BIU_MASTER_INSTR_SIDE_REQUESTS) \
__PMC_EV(E500, BIU_MASTER_DATA_SIDE_REQUESTS) \
__PMC_EV(E500, BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS) \
__PMC_EV(E500, BIU_MASTER_RETRIES) \
__PMC_EV(E500, SNOOP_REQUESTS) \
__PMC_EV(E500, SNOOP_HITS) \
__PMC_EV(E500, SNOOP_PUSHES) \
__PMC_EV(E500, SNOOP_RETRIES) \
__PMC_EV(E500, DLFB_LOAD_MISS_CYCLES) \
__PMC_EV(E500, ILFB_FETCH_MISS_CYCLES) \
__PMC_EV(E500, EXT_INPU_INTR_LATENCY_CYCLES) \
__PMC_EV(E500, CRIT_INPUT_INTR_LATENCY_CYCLES) \
__PMC_EV(E500, EXT_INPUT_INTR_PENDING_LATENCY_CYCLES) \
__PMC_EV(E500, CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES) \
__PMC_EV(E500, PMC0_OVERFLOW) \
__PMC_EV(E500, PMC1_OVERFLOW) \
__PMC_EV(E500, PMC2_OVERFLOW) \
__PMC_EV(E500, PMC3_OVERFLOW) \
__PMC_EV(E500, INTERRUPTS_TAKEN) \
__PMC_EV(E500, EXT_INPUT_INTR_TAKEN) \
__PMC_EV(E500, CRIT_INPUT_INTR_TAKEN) \
__PMC_EV(E500, SYSCALL_TRAP_INTR) \
__PMC_EV(E500, TLB_BIT_TRANSITIONS) \
__PMC_EV(E500, L2_LINEFILL_BUFFER) \
__PMC_EV(E500, LV2_VS) \
__PMC_EV(E500, CASTOUTS_RELEASED) \
__PMC_EV(E500, INTV_ALLOCATIONS) \
__PMC_EV(E500, DLFB_RETRIES_TO_MBAR) \
__PMC_EV(E500, STORE_RETRIES) \
__PMC_EV(E500, STASH_L1_HITS) \
__PMC_EV(E500, STASH_L2_HITS) \
__PMC_EV(E500, STASH_BUSY_1) \
__PMC_EV(E500, STASH_BUSY_2) \
__PMC_EV(E500, STASH_BUSY_3) \
__PMC_EV(E500, STASH_HITS) \
__PMC_EV(E500, STASH_HIT_DLFB) \
__PMC_EV(E500, STASH_REQUESTS) \
__PMC_EV(E500, STASH_REQUESTS_L1) \
__PMC_EV(E500, STASH_REQUESTS_L2) \
__PMC_EV(E500, STALLS_NO_CAQ_OR_COB) \
__PMC_EV(E500, L2_CACHE_ACCESSES) \
__PMC_EV(E500, L2_HIT_CACHE_ACCESSES) \
__PMC_EV(E500, L2_CACHE_DATA_ACCESSES) \
__PMC_EV(E500, L2_CACHE_DATA_HITS) \
__PMC_EV(E500, L2_CACHE_INSTR_ACCESSES) \
__PMC_EV(E500, L2_CACHE_INSTR_HITS) \
__PMC_EV(E500, L2_CACHE_ALLOCATIONS) \
__PMC_EV(E500, L2_CACHE_DATA_ALLOCATIONS) \
__PMC_EV(E500, L2_CACHE_DIRTY_DATA_ALLOCATIONS) \
__PMC_EV(E500, L2_CACHE_INSTR_ALLOCATIONS) \
__PMC_EV(E500, L2_CACHE_UPDATES) \
__PMC_EV(E500, L2_CACHE_CLEAN_UPDATES) \
__PMC_EV(E500, L2_CACHE_DIRTY_UPDATES) \
__PMC_EV(E500, L2_CACHE_CLEAN_REDUNDANT_UPDATES) \
__PMC_EV(E500, L2_CACHE_DIRTY_REDUNDANT_UPDATES) \
__PMC_EV(E500, L2_CACHE_LOCKS) \
__PMC_EV(E500, L2_CACHE_CASTOUTS) \
__PMC_EV(E500, L2_CACHE_DATA_DIRTY_HITS) \
__PMC_EV(E500, INSTR_LFB_WENT_HIGH_PRIORITY) \
__PMC_EV(E500, SNOOP_THROTTLING_TURNED_ON) \
__PMC_EV(E500, L2_CLEAN_LINE_INVALIDATIONS) \
__PMC_EV(E500, L2_INCOHERENT_LINE_INVALIDATIONS) \
__PMC_EV(E500, L2_COHERENT_LINE_INVALIDATIONS) \
__PMC_EV(E500, COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES) \
__PMC_EV(E500, IAC1S_DETECTED) \
__PMC_EV(E500, IAC2S_DETECTED) \
__PMC_EV(E500, DAC1S_DTECTED) \
__PMC_EV(E500, DAC2S_DTECTED) \
__PMC_EV(E500, DVT0_DETECTED) \
__PMC_EV(E500, DVT1_DETECTED) \
__PMC_EV(E500, DVT2_DETECTED) \
__PMC_EV(E500, DVT3_DETECTED) \
__PMC_EV(E500, DVT4_DETECTED) \
__PMC_EV(E500, DVT5_DETECTED) \
__PMC_EV(E500, DVT6_DETECTED) \
__PMC_EV(E500, DVT7_DETECTED) \
__PMC_EV(E500, CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL) \
__PMC_EV(E500, FPU_DOUBLE_PUMP) \
__PMC_EV(E500, FPU_FINISH) \
__PMC_EV(E500, FPU_DIVIDE_CYCLES) \
__PMC_EV(E500, FPU_DENORM_INPUT_CYCLES) \
__PMC_EV(E500, FPU_RESULT_STALL_CYCLES) \
__PMC_EV(E500, FPU_FPSCR_FULL_STALL) \
__PMC_EV(E500, FPU_PIPE_SYNC_STALLS) \
__PMC_EV(E500, FPU_INPUT_DATA_STALLS) \
__PMC_EV(E500, DECORATED_LOADS) \
__PMC_EV(E500, DECORATED_STORES) \
__PMC_EV(E500, LOAD_RETRIES) \
__PMC_EV(E500, STWCX_SUCCESSES) \
__PMC_EV(E500, STWCX_FAILURES) \
#define PMC_EV_E500_FIRST PMC_EV_E500_CYCLES
#define PMC_EV_E500_LAST PMC_EV_E500_STWCX_FAILURES
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
/*
* All known PMC events.
*
* PMC event numbers are allocated sparsely to allow new PMC events to
* be added to a PMC class without breaking ABI compatibility. The
* current allocation scheme is:
*
* START #EVENTS DESCRIPTION
* 0 0x1000 Reserved
* 0x1000 0x0001 TSC
* 0x2000 0x0080 AMD K7 events
* 0x2080 0x0100 AMD K8 events
* 0x10000 0x0080 INTEL architectural fixed-function events
* 0x10080 0x0F80 INTEL architectural programmable events
* 0x11000 0x0080 INTEL Pentium 4 events
* 0x11080 0x0080 INTEL Pentium MMX events
* 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events
Reserve events for XScale. Reviewed by: jkoshy, gnn MFC after: 1 week
2009-09-22 17:45:28 +00:00
* 0x11200 0x00FF INTEL XScale events
Add ARMv7 performance monitoring counters. Differential Revision: https://reviews.freebsd.org/D1687 Reviewed by: rpaulo Sponsored by: DARPA, AFRL
2015-01-28 16:08:07 +00:00
* 0x11300 0x00FF MIPS 24K events
Add support for the MIPS74K SoC family performance counters events. These are similar to the mips24k performance counters - some are available on perfcnt0/3, some are available on perfcnt1/4. However, the events aren't all the same. * Add the events, named the same as from Linux oprofile. * Verify they're the same as "MIPS32(R) 74KTM Processor Core Family Software User's Manual"; Document Number: MD00519; Revision 01.05. * Rename INSTRUCTIONS to something else, so it doesn't clash with the alias INSTRUCTIONS. I'll try to tidy this up later; there are a few other aliases to add and shuffle around. Tested: * QCA9558 SoC (AP135 board) - MIPS74Kc core (no FPU.) * make universe; where it didn't fail for other reasons. TODO: * It'd be nice to support the four performance counters in at least this hardware, rather than just two. Reviewed by: bsdimp ("looks good; don't break world".)
2015-04-05 02:57:02 +00:00
* 0x11400 0x00FF Octeon events
* 0x11500 0x00FF MIPS 74K events
Implement hwpmc(4) for Freescale e500 core. This supports e500v1, e500v2, and e500mc. Tested only on e500v2, but the performance counters are identical across all, with e500mc having some additional events. Relnotes: Yes
2015-04-18 21:39:17 +00:00
* 0x13000 0x00FF MPC7450 events
* 0x13100 0x00FF IBM PPC970 events
* 0x13300 0x00FF Freescale e500 events
Add ARMv7 performance monitoring counters. Differential Revision: https://reviews.freebsd.org/D1687 Reviewed by: rpaulo Sponsored by: DARPA, AFRL
2015-01-28 16:08:07 +00:00
* 0x14000 0x0100 ARMv7 events
Add Performance Monitoring Counters support for AArch64. Family-common and CPU-specific counters implemented. Supported CPUs: ARM Cortex A53/57/72. Reviewed by: andrew, bz, emaste, gnn, jhb Sponsored by: ARM Limited Differential Revision: https://reviews.freebsd.org/D2555
2015-05-19 15:25:47 +00:00
* 0x14100 0x0100 ARMv8 events
Add software PMC support. New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
2012-03-28 20:58:30 +00:00
* 0x20000 0x1000 Software events
- Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to reduce ABI disruptions when new cpu types and new PMC events are added in the future. - Support alternate spellings for PMC events. Derive the canonical spelling of an event name from its enumeration name in 'enum pmc_event'. - Provide a way for users to disambiguate between identically named events supported by multiple classes of PMCs in a CPU. - Change libpmc's machine-dependent event specifier parsing code to better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
*/
#define __PMC_EVENTS() \
__PMC_EV_BLOCK(TSC, 0x01000) \
__PMC_EV_TSC() \
__PMC_EV_BLOCK(K7, 0x2000) \
__PMC_EV_K7() \
__PMC_EV_BLOCK(K8, 0x2080) \
__PMC_EV_K8() \
__PMC_EV_BLOCK(IAF, 0x10000) \
__PMC_EV_IAF() \
__PMC_EV_BLOCK(IAP, 0x10080) \
__PMC_EV_IAP() \
__PMC_EV_BLOCK(P4, 0x11000) \
__PMC_EV_P4() \
__PMC_EV_BLOCK(P5, 0x11080) \
__PMC_EV_P5() \
__PMC_EV_BLOCK(P6, 0x11100) \
Reserve events for XScale. Reviewed by: jkoshy, gnn MFC after: 1 week
2009-09-22 17:45:28 +00:00
__PMC_EV_P6() \
__PMC_EV_BLOCK(XSCALE, 0x11200) \
Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor. Add macros for properly accessing coprocessor 0 registers that support performance counters. Reviewed by: jkoshy rpaulo fabien imp MFC after: 1 month
2010-03-03 15:05:58 +00:00
__PMC_EV_XSCALE() \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_BLOCK(MIPS24K, 0x11300) \
__PMC_EV_MIPS24K() \
Add list of Octeon's PMC counters obtained from cvmx-core.h
2012-03-23 00:04:09 +00:00
__PMC_EV_BLOCK(OCTEON, 0x11400) \
__PMC_EV_OCTEON() \
Add support for the MIPS74K SoC family performance counters events. These are similar to the mips24k performance counters - some are available on perfcnt0/3, some are available on perfcnt1/4. However, the events aren't all the same. * Add the events, named the same as from Linux oprofile. * Verify they're the same as "MIPS32(R) 74KTM Processor Core Family Software User's Manual"; Document Number: MD00519; Revision 01.05. * Rename INSTRUCTIONS to something else, so it doesn't clash with the alias INSTRUCTIONS. I'll try to tidy this up later; there are a few other aliases to add and shuffle around. Tested: * QCA9558 SoC (AP135 board) - MIPS74Kc core (no FPU.) * make universe; where it didn't fail for other reasons. TODO: * It'd be nice to support the four performance counters in at least this hardware, rather than just two. Reviewed by: bsdimp ("looks good; don't break world".)
2015-04-05 02:57:02 +00:00
__PMC_EV_BLOCK(MIPS74K, 0x11500) \
__PMC_EV_MIPS74K() \
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
__PMC_EV_BLOCK(UCF, 0x12000) \
__PMC_EV_UCF() \
__PMC_EV_BLOCK(UCP, 0x12080) \
__PMC_EV_UCP() \
Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x). Sampling is in progress. Approved by: nwhitehorn (mentor) MFC after: 9.0-RELEASE
2011-12-24 19:34:52 +00:00
__PMC_EV_BLOCK(PPC7450, 0x13000) \
__PMC_EV_PPC7450() \
Add hwpmc(4) support for the PowerPC 970 class processors, direct events. This also fixes asserts on removal of the module for the mpc74xx. The PowerPC 970 processors have two different types of events: direct events and indirect events. Thus far only direct events are supported. I included some documentation in the driver on how indirect events work, but support is for the future. MFC after: 1 month
2014-02-01 02:03:50 +00:00
__PMC_EV_BLOCK(PPC970, 0x13100) \
__PMC_EV_PPC970() \
Implement hwpmc(4) for Freescale e500 core. This supports e500v1, e500v2, and e500mc. Tested only on e500v2, but the performance counters are identical across all, with e500mc having some additional events. Relnotes: Yes
2015-04-18 21:39:17 +00:00
__PMC_EV_BLOCK(E500, 0x13300) \
__PMC_EV_E500() \
Add ARMv7 performance monitoring counters. Differential Revision: https://reviews.freebsd.org/D1687 Reviewed by: rpaulo Sponsored by: DARPA, AFRL
2015-01-28 16:08:07 +00:00
__PMC_EV_BLOCK(ARMV7, 0x14000) \
__PMC_EV_ARMV7() \
Add Performance Monitoring Counters support for AArch64. Family-common and CPU-specific counters implemented. Supported CPUs: ARM Cortex A53/57/72. Reviewed by: andrew, bz, emaste, gnn, jhb Sponsored by: ARM Limited Differential Revision: https://reviews.freebsd.org/D2555
2015-05-19 15:25:47 +00:00
__PMC_EV_BLOCK(ARMV8, 0x14100) \
__PMC_EV_ARMV8()
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
#define PMC_EVENT_FIRST PMC_EV_TSC_TSC
Add software PMC support. New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
2012-03-28 20:58:30 +00:00
#define PMC_EVENT_LAST PMC_EV_SOFT_LAST
MFP4: - Implement sampling modes and logging support in hwpmc(4). - Separate MI and MD parts of hwpmc(4) and allow sharing of PMC implementations across different architectures. Add support for P4 (EMT64) style PMCs to the amd64 code. - New pmcstat(8) options: -E (exit time counts) -W (counts every context switch), -R (print log file). - pmc(3) API changes, improve our ability to keep ABI compatibility in the future. Add more 'alias' names for commonly used events. - bug fixes & documentation.
2005-06-09 19:45:09 +00:00
#endif /* _DEV_HWPMC_PMC_EVENTS_H_ */
Reference in New Issue Copy Permalink