Commit Graph

420 Commits

Author SHA1 Message Date
Konstantin Belousov
7aea69e54a Remove mips MD atomic_load_64 and atomic_store_64.
The only users of the functions were db_read_bytes() and
db_write_bytes() ddb(4) interfaces.  Replace the calls with direct
reads and writes, which are automatically atomic on 64bits and n32.

Note that removed assembler implementation for mips32 is not atomic
anyway.

Reviewed by:	jhb
Discussed with:	imp
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
Differential revision:	https://reviews.freebsd.org/D13586
2017-12-22 23:27:03 +00:00
Konstantin Belousov
37f48d5aba Fix mips build after introduction of MD definitions of atomic_load_64
and atomic_store_64.

The MD definitions are provided for LP64 only, while mips also uses
them for 32bit and n32.  Only define mips variants for 32bit and n32
and change the syntax to match common definitions.

Note that this commit does not fix 32bit asm implementation to follow
new KBI, this will be fixed later.  The functions are only used for 8
byte ddb accesses so the known bug does not prevent normal kernel
operations.

Sponsored by:	The FreeBSD Foundation
2017-12-21 23:39:00 +00:00
Konstantin Belousov
30d4f9e888 Add atomic_load(9) and atomic_store(9) operations.
They provide relaxed-ordered atomic access semantic.  Due to the
FreeBSD memory model, the operations are syntaxical wrappers around
the volatile accesses.  The volatile qualifier is used to ensure that
the access not optimized out and in turn depends on the volatile
semantic as implemented by supported compilers.

The motivation for adding the operation is to help people coming from
other systems or knowing the C11/C++ standards where atomics have
special type and require use of the special access operations.  It is
still the case that FreeBSD requires plain load and stores of aligned
integer types to be atomic.

Suggested by:	jhb
Reviewed by:	alc, jhb
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
Differential revision:	https://reviews.freebsd.org/D13534
2017-12-19 09:59:20 +00:00
Pedro F. Giffuni
796df753f4 SPDX: Consider code from Carnegie-Mellon University.
Interesting cases, most likely from CMU Mach sources.
2017-11-30 15:48:35 +00:00
Pedro F. Giffuni
19d3b47b92 sys/mips: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.
2017-11-27 15:07:26 +00:00
Landon J. Fuller
caeff9a3c2 bhnd(4): implement MIPS and PCI(e) interrupt support
On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the
common bhnd(4) core drivers; we now register an INTRNG child PIC that
handles routing of backplane interrupt vectors via the MIPS core.

On BHND PCI devices, backplane interrupt vectors are now routed to the
PCI/PCIe host bridge core when bus_setup_intr() is called, where they are
dispatched by the PCI core via a host interrupt (e.g. INTx/MSI).

The bhndb(4) bridge driver tracks registered interrupt handlers for the
bridged bhnd(4) devices and manages backplane interrupt routing, while
delegating actual bus interrupt setup/teardown to the parent bus on behalf
of the bridged cores.

Approved by:	adrian (mentor, implicit)
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
Landon J. Fuller
e60ff6a3b4 Preemptively map MIPS INTRNG interrupts on non-FDT MIPS targets
This replaces a partial workaround introduced in r305527 that was
incompatible with nested INTRNG interrupt controllers if not also using
FDT.

On non-FDT MIPS INTRNG targets, we now preemptively produce a set of fixed
mappings for the MIPS IRQ range during nexus attach. On FDT targets,
OFW_BUS_MAP_INTR() remains responsible for mapping the MIPS IRQs.

Approved by:	adrian (mentor)
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D12385
2017-11-21 01:54:48 +00:00
Pedro F. Giffuni
51369649b0 sys: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 3-Clause license.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

Special thanks to Wind River for providing access to "The Duke of
Highlander" tool: an older (2014) run over FreeBSD tree was useful as a
starting point.
2017-11-20 19:43:44 +00:00
Pedro F. Giffuni
df57947f08 spdx: initial adoption of licensing ID tags.
The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

Special thanks to Wind River for providing access to "The Duke of
Highlander" tool: an older (2014) run over FreeBSD tree was useful as a
starting point.

Initially, only tag files that use BSD 4-Clause "Original" license.

RelNotes:	yes
Differential Revision:	https://reviews.freebsd.org/D13133
2017-11-18 14:26:50 +00:00
Michal Meloun
904d8c492f Add AT_HWCAP2 ELF auxiliary vector.
- allocate value for new AT_HWCAP2 auxiliary vector on all platforms.
 - expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly
   same way as for AT_HWCAP.

MFC after:	1 month
Reviewed by:	kib
Differential Revision:	https://reviews.freebsd.org/D12699
2017-10-21 12:05:01 +00:00
Landon J. Fuller
011e84e0a7 Add MIPS32/64 Rev2 CP0 intctl register definitions.
Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D12300
2017-09-15 19:56:21 +00:00
John Baldwin
c2f37b9245 Add AT_HWCAP and AT_EHDRFLAGS on all platforms.
A new 'u_long *sv_hwcap' field is added to 'struct sysentvec'.  A
process ABI can set this field to point to a value holding a mask of
architecture-specific CPU feature flags.  If an ABI does not wish to
supply AT_HWCAP to processes the field can be left as NULL.

The support code for AT_EHDRFLAGS was already present on all systems,
just the #define was not present.  This is a step towards unifying the
AT_* constants across platforms.

Reviewed by:	kib
MFC after:	1 month
Differential Revision:	https://reviews.freebsd.org/D12290
2017-09-14 14:26:55 +00:00
Conrad Meyer
70dd00d6c0 Fix limits.h constants to have correct type on MIPS
Use correctly typed constants to avoid bogus errors like
https://lists.freebsd.org/pipermail/svn-src-all/2017-August/150400.html
(like x86 _limits.h).

Reported by:	bde, asomers
Reviewed by:	mjoras, tinderbox
Sponsored by:	Dell EMC Isilon
2017-08-26 03:21:12 +00:00
Jason A. Harmening
eb36b1d0bc Clean up MD pollution of bus_dma.h:
--Remove special-case handling of sparc64 bus_dmamap* functions.
  Replace with a more generic mechanism that allows MD busdma
  implementations to generate inline mapping functions by
  defining WANT_INLINE_DMAMAP in <machine/bus_dma.h>.  This
  is currently useful for sparc64, x86, and arm64, which all
  implement non-load dmamap operations as simple wrappers
  around map objects which may be bus- or device-specific.

--Remove NULL-checked bus_dmamap macros.  Implement the
  equivalent NULL checks in the inlined x86 implementation.
  For non-x86 platforms, these checks are a minor pessimization
  as those platforms do not currently allow NULL maps.  NULL
  maps were originally allowed on arm64, which appears to have
  been the motivation behind adding arm[64]-specific barriers
  to bus_dma.h, but that support was removed in r299463.

--Simplify the internal interface used by the bus_dmamap_load*
  variants and move it to bus_dma_internal.h

--Fix some drivers that directly include sys/bus_dma.h
  despite the recommendations of bus_dma(9)

Reviewed by:	kib (previous revision), marius
Differential Revision:	https://reviews.freebsd.org/D10729
2017-07-01 05:35:29 +00:00
Konstantin Belousov
43f41dd393 Make struct syscall_args visible to userspace compilation environment
from machine/proc.h, consistently on all architectures.

Reviewed by:	jhb
Sponsored by:	The FreeBSD Foundation
MFC after:	3 weeks
X-Differential revision:	https://reviews.freebsd.org/D11080
2017-06-12 20:53:44 +00:00
John Baldwin
4a0f7f1c10 Add initial support for the floating point implementation register.
- Save the current FIR in the global 'cpuinfo' structure in a new
  'fpu_id' member.
- Decode flags in the FIR when displaying other CPU flags during boot.
- Use the existing "dummy" slot in the floating point register structure
  to export the FIR in process core dumps and via ptrace().  Note that
  while the FIR register is not volatile, this practice of storing the FIR
  in the floating-point register set is used in other OS's.

Reviewed by:	kan
MFC after:	1 month
Sponsored by:	DARPA / AFRL
Differential Revision:	https://reviews.freebsd.org/D10617
2017-05-09 17:35:16 +00:00
Gleb Smirnoff
83c9dea1ba - Remove 'struct vmmeter' from 'struct pcpu', leaving only global vmmeter
in place.  To do per-cpu stats, convert all fields that previously were
  maintained in the vmmeters that sit in pcpus to counter(9).
- Since some vmmeter stats may be touched at very early stages of boot,
  before we have set up UMA and we can do counter_u64_alloc(), provide an
  early counter mechanism:
  o Leave one spare uint64_t in struct pcpu, named pc_early_dummy_counter.
  o Point counter(9) fields of vmmeter to pcpu[0].pc_early_dummy_counter,
    so that at early stages of boot, before counters are allocated we already
    point to a counter that can be safely written to.
  o For sparc64 that required a whole dummy pcpu[MAXCPU] array.

Further related changes:
- Don't include vmmeter.h into pcpu.h.
- vm.stats.vm.v_swappgsout and vm.stats.vm.v_swappgsin changed to 64-bit,
  to match kernel representation.
- struct vmmeter hidden under _KERNEL, and only vmstat(1) is an exclusion.

This is based on benno@'s 4-year old patch:
https://lists.freebsd.org/pipermail/freebsd-arch/2013-July/014471.html

Reviewed by:	kib, gallatin, marius, lidl
Differential Revision:	https://reviews.freebsd.org/D10156
2017-04-17 17:34:47 +00:00
Gleb Smirnoff
9ed01c32e0 All these files need sys/vmmeter.h, but now they got it implicitly
included via sys/pcpu.h.
2017-04-17 17:07:00 +00:00
Patrick Kelsey
67d955aab4 Corrected misspelled versions of rendezvous.
The MFC will include a compat definition of smp_no_rendevous_barrier()
that calls smp_no_rendezvous_barrier().

Reviewed by:	gnn, kib
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D10313
2017-04-09 02:00:03 +00:00
Bruce Evans
f434f3515b Fix printing of negative offsets (typically from frame pointers) again.
I fixed this in 1997, but the fix was over-engineered and fragile and
was broken in 2003 if not before.  i386 parameters were copied to 8
other arches verbatim, mostly after they stopped working on i386, and
mostly without the large comment saying how the values were chosen on
i386.  powerpc has a non-verbatim copy which just changes the uncritical
parameter and seems to add a sign extension bug to it.

Just treat negative offsets as offsets if they are no more negative than
-db_offset_max (default -64K), and remove all the broken parameters.

-64K is not very negative, but it is enough for frame and stack pointer
offsets since kernel stacks are small.

The over-engineering was mainly to go more negative than -64K for the
negative offset format, without affecting printing for more than a
single address.

Addresses in the top 64K of a (full 32-bit or 64-bit) address space
are now printed less well, but there aren't many interesting ones.
For arches that have many interesting ones very near the top (e.g.,
68k has interrupt vectors there), there would be no good limit for
the negative offset format and -64K is a good as anything.
2017-03-26 18:46:35 +00:00
Warner Losh
43b96a4eb5 Revert prior commit to restore the files mangled by my "fixing" merge
conflicts for a git rebase I tried to do.
2017-03-01 02:10:40 +00:00
Warner Losh
fbbd9655e5 Renumber copyright clause 4
Renumber cluase 4 to 3, per what everybody else did when BSD granted
them permission to remove clause 3. My insistance on keeping the same
numbering for legal reasons is too pedantic, so give up on that point.

Submitted by:	Jan Schaumann <jschauma@stevens.edu>
Pull Request:	https://github.com/freebsd/freebsd/pull/96
2017-02-28 23:42:47 +00:00
Jason A. Harmening
e2a8d17887 Bring back r313037, with fixes for mips:
Implement get_pcpu() for amd64/sparc64/mips/powerpc, and use it to
replace pcpu_find(curcpu) in MI code.

Reviewed by:	andreast, kan, lidl
Tested by:	lidl(mips, sparc64), andreast(powerpc)
Differential Revision:	https://reviews.freebsd.org/D9587
2017-02-19 02:03:09 +00:00
Alexander Kabaev
7b6d9d0c3a Use 64bit store instruction in atomic_fcmpset_64.
Reported by: br
2017-02-06 14:00:28 +00:00
Konstantin Belousov
9fb10d635e Define the vm_ooffset_t and vm_pindex_t types as machine-independend.
The types are for the byte offset and page index in vm object.  They
are similar to off_t, which is defined as 64bit MI integer.  Using MI
definitions will allow to provide consistent MD values of vm
object-related maximum sizes.

Reviewed by:	alc
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
2017-02-04 12:26:38 +00:00
Jason A. Harmening
ad62ba6e96 Revert r313037
The switch to get_pcpu() in MI code seems to cause hangs on MIPS.
Back out until we can get a better idea of what's happening there.

Reported by:	kan, lidl
2017-02-04 06:24:49 +00:00
Alexander Kabaev
2733239f37 Add atomic_fcmpset_*() inlines for MIPS
atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the
read value from the target memory location into the 'old' pointer.

Reviewed by:	imp, brooks
Requested by:	mjg
Differential Revision:	https://reviews.freebsd.org/D9391
2017-02-01 05:00:34 +00:00
Jason A. Harmening
65ed483615 Implement get_pcpu() for the remaining architectures and use it to
replace pcpu_find(curcpu) in MI code.
2017-02-01 03:32:49 +00:00
John Baldwin
da53b41194 Only call stacktrace_subr() from DDB.
There was a single call to stacktrace() under an #ifdef DEBUG to obtain
a stack trace during a fault that resulted in a function pointer to a
printf function being passed to stacktrace_subr() in db_trace.c.  The
kernel now has existing interfaces for obtaining a stack trace outside
of DDB (kdb_backtrace(), or the stack_*() API) that should be used instead.
Rather than fix the one call however, remove it since the kernel will
dump a trace anyway once it panics.

Make stacktrace_subr() static, remove the function pointer and change it
to use db_printf() explicitly.

Discussed with:	kan
Sponsored by:	DARPA / AFRL
2017-01-05 00:08:04 +00:00
Alexander Kabaev
1b664b2eea Be more conservative when enabling write-combining on MIPS
Some MIPS revisions do implement uncached-accelerate caching
attribute, but place extra requirement on access, such as
partial-word or out-of-sequence writes potentially having an
“unpredictable” effects.
2016-12-28 13:48:00 +00:00
Alexander Kabaev
a0e41d3784 Implement pmap_change_attr and related APIs on MIPS
On platforms that have uncached-accelerate cache attribute, map it
to VM_MEMATTR_WRITE_COMBINING. Otherwise, leave write comining
undefined.

Reviewed by:	adrian, jhb (glance)
Differential Revision:	https://reviews.freebsd.org/D8894
2016-12-28 02:55:26 +00:00
John Baldwin
7212e5d8bf Teach DDB how to unwind across a kernel stack overflow.
Kernel stack overflows in MIPS call panic() directly from an assembly
handler after storing the interrupted context's registers in a
trapframe.  Rather than inferring the location of ra, sp, and pc from
the instruction stream, recognize the pc of a kernel stack overflow
and pull the registers from the trapframe.

Sponsored by:	DARPA / AFRL
2016-12-23 03:27:11 +00:00
Ruslan Bukin
62993bb71e Increase pcpu size to 512 so it become both denominator
of PAGE_SIZE and aligned to CACHE_LINE_SIZE.

This fixes CTASSERT.

Sponsored by:	DARPA, AFRL
2016-11-23 11:30:40 +00:00
Ruslan Bukin
d509eaf204 Account for bigger secondary data cache line size.
Secondary data cache line size can be bigger than
primary data cache line size, so use biggest value
as a minimum alignment.

Submitted by:	kan
Sponsored by:	DARPA, AFRL
2016-11-19 16:36:38 +00:00
Ruslan Bukin
92fd9fe2b7 Add Ingenic XBurst coprocessor 0 extra bits.
Submitted by:	kan
Sponsored by:	DARPA, AFRL
2016-11-19 15:38:13 +00:00
Ruslan Bukin
bf214121f8 Identify Ingenic CPUs.
Submitted by:	kan
Sponsored by:	DARPA, AFRL
2016-11-19 15:10:10 +00:00
Alexander Kabaev
63a16ecab1 Subject: [PATCH] Pass MACHINE_ARCH on command line for MIPS kernels.
While there, make param.h guess proper MACHINE_ARCH on hardfloat targets
correctly as well, so tools like bmake can get their defaults right.
This does not help the kernel case, since we compile them with forced
-msoft-float and need to override an incorrect guess by param.h.

Reviewed by: br
Differential Revision:	https://reviews.freebsd.org/D8574
2016-11-18 16:23:31 +00:00
Michael Zhilin
679761c0e0 [MIPS] Print Config7 on boot for several MIPS architectures
Config7 contains useful fields, for instance, field AR indicating that the D-cache is configured to avoid cache aliases. This patch brings printing of config7 for MIPS 24K, 74K, 1004K.

Reviewed by:	adrian
Approved by:	adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D8514
2016-11-14 21:38:36 +00:00
Ruslan Bukin
5bca221511 Add full softfloat and hardfloat support for MIPS.
This adds new target architectures for hardfloat:
mipselhf mipshf mips64elhf mips64hf.

Tested in QEMU only.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D8376
2016-10-31 15:33:58 +00:00
John Baldwin
ed3abcbb0d Correct definition of 'struct sigcontext' on MIPS.
Add missing fields ('sr' and 'mc_tls') to 'struct sigcontext'.

The kernel doesn't use 'struct sigcontext' but instead uses 'ucontext_t'
which includes 'mcontext_t' in 'struct sigframe' to build the signal frame.
As a result, this change is not an ABI change but simply making
'struct sigcontext' correct.  Note that 'struct sigcontext' is only used
for "Traditional BSD style" signal handlers.

While here, rename the 'xxx' field to '__spare__' to match 'mcontext_t'.

Sponsored by:	DARPA, AFRL
2016-10-26 17:37:08 +00:00
Warner Losh
b2a7ac4802 Fix building on i386 and arm. But 'public domain' headers on the files
with no creative content. Include "lost" changes from git:
o Use /dev/efi instead of /dev/efidev
o Remove redundant NULL checks.

Submitted by: kib@, dim@, zbb@, emaste@
2016-10-13 06:56:23 +00:00
Warner Losh
943ac2b07e Include stubs even on the platforms we don't support so libsysdecode
continues to build.
2016-10-11 22:54:29 +00:00
Brooks Davis
79816bbe94 The TLS offset is a property of the process ABI.
Move to a per-proc TLS offset rather than incorrectly keying off the
presense of freebsd32 compability in the kernel.

Reviewed by:	adrian, sbruno
Obtained from:	CheriBSD
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D7843
2016-09-15 17:25:52 +00:00
Ruslan Bukin
84aec472fc Allow the use of soft-interrupts for sending IPIs.
This will be required for SMP support on MIPS Malta platform.

Reviewed by:	adrian
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D7835
2016-09-08 17:37:13 +00:00
Stanislav Galabov
2b99b9f3d2 Fix MIPS INTRNG (both FDT and non-FDT) behaviour broken by r304459
More changes to MIPS may be required, as commented in D7692, but this
revision aims to restore MIPS INTRNG functionality so we can move on
with working interrupts.

Reported by:	yamori813@yahoo.co.jp
Tested by:	mizhka (on BCM), sgalabov (on Mediatek)
Reviewed by:	adrian, nwhitehorn (older version)
Sponsored by:	Smartcom - Bulgaria AD
Differential Revision:	https://reviews.freebsd.org/D7692
2016-09-07 09:31:10 +00:00
Adrian Chadd
b812fe4d6b [mips] add support for using the MIPS user register for TLS data.
This work, originally from Stacey Son, uses the MIPS UserReg for
reading the TLS data, and will fall back to the normal syscall path
when it isn't supported.

This code dynamically patches cpu_switch() to bypass the UserReg
instruction so to avoid generating a machine exception.

Thanks to sson for the original work, and to Dan Nelson for
bringing it to date and testing it on MIPS32 with me.

Tested:

* mips64 (sson)
* mips74k (dnelson_1901@yahoo.com) - AR9344 SoC, UserReg support
* mips24k (adrian) - AR9331 SoC, no UserReg support

Obtained from:	sson, dnelson_1901@yahoo.com
2016-08-07 01:29:55 +00:00
Robert Watson
57b3862fd2 Garbage collect unused prototype for clockintr().
MFC after:	3 days
2016-05-20 15:34:03 +00:00
Robert Watson
a75a7d90e9 When attempting to satisfy mmap() requests for superpage alignment on
64-bit MIPS, use superpage rather than physical-segment constants, or
we may improperly fail to apply suitable alignment -- yet still allow
mmap() to appear to succeed.

Reviewed by:	sson
MFC after:	1 week
Sponsored by:	DARPA, AFRL
2016-04-30 19:29:03 +00:00
Andrew Turner
59c3cb81c1 Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine
independent code that needs to know about INTRNG such as PCI drivers.

Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
2016-04-15 16:05:41 +00:00
Stanislav Galabov
915c6043b0 Make NIRQ configurable for MIPS
Submitted by:	kan
Reviewed by:	kan
Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D5964
2016-04-15 15:44:02 +00:00