This adds the concept of "operating points," combinations of frequency
and voltage at which the cpu is known to work correctly. Some day these
should come from FDT data, but for now the table is hard-coded.
This also allows tuning the min and max operating frequencies. The min
frequency is what the thermal management code will slow down to if the
core temperature gets too high. The max frequency is what gets used if
the temperature is okay.
Normally the max cannot be set higher than the value burned into the
ocotp fuses as the chip's rated max, but there is now a new sysctl+tunable
cpu_overclock_enable; when set to non-zero it allows raising the frequency
above the ocotp value: USE WITH CARE! (At least one of my imx6 boards
has a cpu whose ocotp values never got set correctly; they claim a max
of 792mhz, but the physical markings on the chip say it's good to 1ghz.)
Because all these values affect the entire SoC, there is a new sysctl
node, hw.imx6, where all these values live. The values that are currently
under dev.imx6_anatop.0 should probably move to hw.imx6 too, because
"anatop" doesn't even mean anything to me, let alone to an end user.
description was eaten by the dog (or an editor crash or something).
Add variable-frequency support to the arm mpcore eventtimer driver.
This allows a platform's early init code to tell the mpcore driver that the
clock frequency can vary. That causes the mpcore driver to register an
eventtimer, but not a timecounter. The platform has to provide a time
counter using some other fixed-frequency clock, but can still use the
per-cpu goodness of the mpcore hardware for event timers.
When the platform support code does something to change the frequency of
the CPU clocks (power saving, thermal management) it must tell the mpcore
driver code about it using arm_tmr_change_frequency().
register values, then restart the timer. This prevents a situation where
an old event fires just as we're about to load a new value into the timer,
when the start routine is called to change the time of the current event.
Also re-nest the parens properly for casting the result of converting
time and frequency to a count. This doesn't actually change the result of
the calcs, but will some day prevent a loss-of-precision warning on the
assignment, if that warning gets enabled.
Support covers device drivers for:
- Interrupt Combiner
- gpio/pad, External Interrupts Controller (pad)
- I2C Interface
- Chrome Embedded Controller
- Chrome Keyboard
Also:
- Use new gpio dev class in EHCI driver
- Expand device tree information
* Save the required VFP registers on context switch. If the exception bit
is set we need to save and restore the FPINST register, and if the fp2v
bit is also set we need to save and restore FPINST2.
* Move saving and restoring the floating point control registers to C.
* Clear the fpexc exception and fp2v flags on a floating-point exception.
* Signal a SIGFPE if the fpexc exception flag is set on an undefined
instruction. This is how the ARM core signals to software there is a
floating-point exception.
The ADC has a 12bit resolution and its raw output can be read via sysctl(8)
interface.
The driver allows the setup of ADC clock, samples average and open delay
(the number of clock cycles to wait before start the conversion).
The TSC_ADC module is set in the general purpose mode (no touchscreen
support).
Tested on Beaglebone-black.
Written based on AM335x TRM.
Reviewed by: rpaulo
Approved by: adrian (mentor)
Tested by: me, Brian J. McGovern, Sulev-Madis Silber (ketas)
To reduce the diff struct pcu.cnt field was not renamed, so
PCPU_OP(cnt.field) is still used. pc_cnt and pcpu are also used in
kvm(3) and vmstat(8). The goal was to not affect externally used KPI.
Bump __FreeBSD_version_ in case some out-of-tree module/code relies on the
the global cnt variable.
Exp-run revealed no ports using it directly.
No objection from: arch@
Sponsored by: EMC / Isilon Storage Division
The armv7 architecture uses a unified TLB model for maintenence ops even
if separate instruction and data TLBs are implemented in hardware. That
means that there's no distinction between the 'I' and 'D' flavors of flush,
they all use the same 'ID' implementation. On the other hand, there is a
difference between SMP and UP on armv7, but not on arm11, so use the armv7
routines for cortex-a processors.
further refinement is required as some device drivers intended to be
portable over FreeBSD versions rely on __FreeBSD_version to decide whether
to include capability.h.
MFC after: 3 weeks
which was added by cognet in 2012, so remove the no-longer-applicable
license stuff that referred to all the old contents, and put in a
standard 2-clause BSD license (to cover the 6 lines of useful code left
in here).
swi_exit code in exception.S instead of having its own inline expansion
of the DO_AST and PULLFRAME macros. That means that now all references
to the PUSH/PULLFRAME and DO_AST macros are localized to exception.S,
so move the macros themselves into there and remove them from asmacros.h
and eliminate vectors.S. All low-level exception handling is now
consolidated into exception.S.
Along with moving the default FIQ handler, change it to disable FIQs
before returning. An FIQ should never happen, but if it does, it's got
to be disabled as part of ignoring it.
In general, we have hand-wavy support for FIQs that probably hasn't been
used for 10 years and probably doesn't work (almost certainly doesn't
work for SMP because it only updates the vector on the current cpu). This
change doesn't really make the overall situation any better or worse.
and the functionality it provided into arm/exception.S. Rename the main
irq handling routine from arm_handler_execute() to arm_irq_handler() to
make it more congruent with how other exception handlers are named, and
also update its signature to reflect what has long been reality: it is
passed just a trapframe pointer, no interrupt number argument.
never actually ran on these chips (other than using SA1 support in an
emulator to do the early porting to FreeBSD long long ago). The clutter
and complexity of some of this code keeps getting in the way of other
maintenance, so it's time to go.
to the actual handler routine. All the pointers are static-intialized to
the only handlers available, and yet various platform-specific inits still
set those pointers (to the values they're already initialized to). Begin
to drain the swamp by removing all the redundant external declarations and
runtime setting of the pointers that's scattered around various places.
The old code used static storage to preserve a couple registers while
setting up the trapframe for the main handler. Doing so was the last
leftover crumbs from the days when a low-level debugger was hooked into
the exception entry code.
Now the exception entry sequence is essentially the same as for the
other exceptions, which still involves needlessly indirecting through
a function pointer which points to the same code on every platform.
Removing that indirection will be handled as a separate cleanup.
This work is based on an analysis by Juergen Weiss.
enabled. In vfp_discard(), if the state in the VFP hardware belongs to
the thread which is dying, NULL out pcpu fpcurthread to indicate the
state currently in the hardware belongs to nobody.
Submitted by: Juergen Weiss
Pointy hat to: me
a leftover from the days when a low-level debugger had hooks in the
undefined exception vector and needed stack space to function. These days
it effectively isn't used because we switch immediately to the svc32 mode
stack on exception entry. For that, the single undef mode stack per core
that gets set up at init time works fine.
The stack wasn't necessary but it was harmful, because the space for it
was carved out of the normal per-thread svc32 stack, in effect cutting
that 8K stack in half. If svc32 mode used more than 4k of stack space it
wandered down into the undef mode stack, and then an undef exception would
overwrite a couple words on the stack while switching to svc32 mode,
corrupting the scv32 stack. Having another stack abut the bottom of the
svc32 stack also effectively mooted the guard page below the stack.
This work is based on analysis and patches submitted by Juergen Weiss.
The old code was full of complexity that would only matter if the
kernel itself used the VFP hardware. Now that's reduced to either killing
the userland process or panicking the kernel on an illegal VFP instruction.
This removes most of the complexity from the assembler code, reducing it
to just calling the save code if the outgoing thread used the VFP.
The routine that stores the VFP state now takes a flag that indicates
whether the hardware should be disabled after saving state. Right now it
always is, but this makes the code ready to be used by get/set_mcontext()
(doing so will be addressed in a future commit).
Remove the arm-specific pc_vfpcthread from struct pcpu and use the MI
field pc_fpcurthread instead.
Reviewed by: cognet
appropriate for each of the 'foo' in the tree. This will allow us to
compile them together (although symbol conflicts prevent us from doing
that today, this just fixes the file name collision).
struct sigframe containing the struct ucontext.
The signal trampoline return code on the other hand DOES have just a
struct sigframe on the stack to work with, so have it get a pointer to
the ucontext out of there to pass along to sys_sigreturn.
In other words, make everything work right whether sys_sigreturn is
invoked from the trampoline or from userland code calling sigreturn(2).
Submitted by: Takashi Komatsu <komatsu.taka@jp.panasonic.com>
Reviewed by: cognet
It is available mostly in A10 devices like Hackberry, Marsboard,
Mele A1000, A2000, A100 HTPC, cubieboard1 and A20 device
like cubieboard2.
TX performance can be improved using both channels 0 and 1.
RX performance is poor and needs improvement with the assistance of
external DMA controller in case there is bulk TCP receiver.
Reviewed by: yongari@
Approved by: stas (mentor)
we've been using was actually just spinning due to ARM having redefined
the old 'wait for interrupt' operation via the system coprocessor as a nop
and replacing it with a WFI instruction.
code can supply a better implementation. A SoC with variable CPU frequency
is likely to use a fixed-frequency timer for DELAY() (but still use the
mpcore private timers as eventtimers).
Also remove spaces from the eventtimer and timecounter names.
implementation in arm/machdep.c. Most arm platforms either don't need to
do anything, or just need to call the standard eventtimer init routines.
A generic implementation that does that is now provided via weak linkage.
Any platform that needs to do something different can provide a its own
implementation to override the generic one.
- Don't use spaces or dots in the eventtimer or timecounter names.
They turn into sysctl node names, and it's just confusing.
- Use comparator #3 instead of #1 for one-shot events. There's an
extra 1-cycle penalty in the hardware for accessing the registers
for comparator 1, no point in paying that penalty.
- Lower the quality of the eventtimer from 1000 to 800, because the
device can't support PERCPU timers and some other device in the system
may be able to provide that.
Quartz is a tiny module utilized Freescale VF6xx
system-on-chip and development kit produced by
Device Solutions.
Quartz is available in a form of LGA (38x38x2mm)
or as a module with high-density connectors.
Sponsored by: Device Solutions
the Bufferable bit in the PDE entries of the secondary processor startup
pagetables.
The caches really need to be invalidated even earlier than this, but this
is a big step in the right direction. The invalidate needs to happen
before the MMU is enabled, which means it has to be called from asm code
that's running with physical addressing. Fixing that will be handled in
a future change.
implementations for each of the chips we support. Most chips up through
armv6 can use the armv4 implementation which has a single coprocessor
opcode for this operation. The rather more complex armv7 implementation
comes from netbsd.
While this is technically more correct, I don't think it much matters,
because the only thing in the tree that calls cpu_flush_dcache() is md(4)
and I'm > 99% sure it's bogus that it does so; md has no ability to do
anything that can perturb data cache coherency.
it into a bunch of different .c files. Remove declarations for the unused
mptramp() function from everywhere except AramadaXP (and I think it's
really not used there either, because the code that references it appears
to be insanely does-nothing in nature).
WANDBOARD.common config, but with the freescale-specific optons and devices
all together at the bottom now. In addition to reformatting and shuffling
lines around, two new options are added because they're now known to work,
VFP and FREEBSD_BOOT_LOADER.
This config does not include any static DTB, it requires that u-boot
provide a DTB (or a custom kernel config can compile one in).
This will supercede all the existing WANDBOARD* configs, but those will
be left around for a while to help people transition their customized
configs to include this new one instead.
The temperature monitor device is enabled to sample the die temperature at
16hz. The temperature is published via sysctl. A callout routine at 10hz
monitors the temperature and throttles back the cpu if the temperature
goes over a user-settable throttle point (by default 10C less than the
critical high-point temperature for the chip). The hardware is supposed
to be able to deliver an interrupt when the temperature exceeds a settable
limit, but the interrupt never arrives so for now a callout does the job.
At attach time we read the maximum cpu frequency the chip is allowed to run
at and the cpu is set to run at that speed. It's reported at attach time.
A sysctl variable reports the current speed when queried.
New sysctl values:
dev.imx6_anatop.0.cpu_mhz: 984
dev.imx6_anatop.0.temperature: 37.9C
dev.imx6_anatop.0.throttle_temperature: 95.0C
Steven Lawrance did the initial heavy lifting on this, but I changed
enough stuff that I'm the one to blame if anything breaks.
Submitted by: Steven Lawrance <stl@koffein.net>
and CAMBRIA boards that does not use loader to load the kernel. This
is basically how it was done for i386. This way tunables can also be
set. For example in config file:
env "/conf/AVILA.env"
And in AVILA.env:
vfs.unmapped_buf_allowed=0
MFC after: 2 weeks
is attached, by establishing a temporary mapping of the registers when
necessary. This is a temporary measure to keep progress moving; in the
long run we need better control over the order in which devices attach
(better than "the order they appear in the fdt dts source").
Attempt to demote the superpage if trying to pmap_enter() on
one. Panic only when the particular superpage should
no longer exist for that pmap and address.
Because pmap_enter_locked() is called from few different functions
some redundancy in superpage promotion attempts can be observed.
Hence, avoid promotion in pmap_enter_object() (if the object can
be mapped by superpage it will be handled by pmap_enter_object()
itself) and also do not waste time in pmap_enter_quick().
From now on the promotion will be performed only in pmap_enter().
It was possible to create RW superpage mapping even if
the base pages were RO due to wrong setting of the prot
flag passed to pmap_map_section().
Promotion attempt should be canceled in case of attributes
mismatch between any two base pages. Since we still use
pv_flags to maintain permission to write (PVF_WRITE) and
wired status (PVF_WIRED) for a page, it is also necessary
to take those variables into account.
Invalidate L1 PTE regardles of existance of the corresponding
l2_bucket. This is relevant when superpage is entered via
pmap_enter_object() and will fix crash on entering page
in place of not properly removed superpage.
because we use the 1MiB section maps as they only need a single pagetable.
To allow this we only use pc relative loads to ensure we only load from
physical addresses until we are running from a known virtual address.
As a side effect any data from before or 64MiB after the kernel needs to
be mapped in to be used. This should not be an issue for kernels loaded
with ubldr as it places this data just after the kernel. It will be a
problem when loading directly from anything using the Linux ABI that
places the ATAG data outside this range, for example U-Boot.
Add gpioled(4) to BEAGLEBONE kernel and add the description of the four
on-board leds of beaglebone-black to its DTS file.
Approved by: adrian (mentor, implicit)
change the gpio children can be described as directly connected to the GPIO
controller without the need of describing the OFW GPIO bus itself on the
DTS file.
With this commit the OFW GPIO bus is fully functional on BBB and RPi.
GPIO controllers which want to use the OFW GPIO bus will need similar
changes.
Approved by: adrian (mentor, implicit)
to decide what protections are required by the faulting access. The old
code disassembled the faulting instruction, and there are a lot of new
instructions that aren't handled. The old code is still used for armv4/5
which doesn't have the WNR bit)
routine, now a platform can provide a pointer to an early_putc() routine
which is used instead of cn_putc(). Control can be handed off from early
printf support to standard console support by NULLing out the pointer
during standard console init.
This leverages all the existing error reporting that uses printf calls,
such as panic() which can now be usefully employed even in early
platform init code (useful at least to those who maintain that code and
build kernels with EARLY_PRINTF defined).
Reviewed by: imp, eadler
Real means the one TSC / Symmetricom / Microsemi actually uses on their 4370
and other rm9200 boards. This code demonstrates a variety of useful things
board init code can do, including adjusting the master clock frequency.
communicate the kernel's physical load address from where it's known in
initarm() into cpu_mp_start() which is called from non-arm code and
takes no parameters.
This adds the global variable and ensures that all the various copies
of initarm() set it. It uses the variable in cpu_mp_start(), eliminating
the last uses of KERNPHYSADDR outside of locore.S (where we can now
calculate it instead of relying on the constant).
a new physmem.c file. The new code provides helper routines that can be
used by legacy SoCs and newer FDT-based systems. There are routines to
add one or more regions of physically contiguous ram, and exclude one or
more physically contiguous regions of ram. Ram can be excluded from crash
dumps, from being given over to the vm system for allocation management,
or both. After all the included and excluded regions have been added,
arm_physmem_init_kernel_globals() processes the regions into the global
dump_avail and phys_avail arrays and realmem and physmem variables that
communicate memory configuration to the rest of the kernel.
Convert all existing SoCs to use the new helper code.
This was an optimization used only by a few xscale platforms. Part of
the optimization was to create a direct map for all physical pages, and
that resulted in making multiple mappings of pages in a way that bypassed
the logic in pmap.c to handle VIVT cache aliasing. It also just generally
made the code more complex and hard to maintain for all SoCs.
Reviewed by: cognet
and where the code that references it can safely be elided if it's not
defined (meaning the code is used for legacy arm platforms that still
define the compile-time PHYSADDR but not on newer systems that calculate
the value at runtime).
in effect due to r250753. That is sufficient for all SoCs with a 32 byte
cache line size. Systems with 64 byte cache lines will need the option;
that will be done in a separate commit.
Thanks to loos@ for pointing out r250753.
a sub-node of nexus (ofwbus) rather than direct attach under nexus. This
fixes FDT on x86 and will make coexistence with ACPI on ARM systems easier.
SPARC is unchanged.
Reviewed by: imp, ian
the old way was to store pcpu in a register, and get curthread from pcpu,
which is not very atomic, and led to issues if the thread was migrated
to another core between the time we got the pcpu address and the time we
got curthread.
Instead, we now store curthread where pcpu used to be store, and we
calculate the pcpu address based on the cpu id.
to check the status property in their probe routines.
Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352. Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.
Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
It turns out the version of gas we're using interprets the old '_all' mask
as 'fc' instead of 'fsxc'. That is, "all" doesn't really mean "all".
This was the cause of the "wrong-endian register restore" bug that's
been causing problems with some cortex-a9 chips. The 'endian' bit in the
spsr register would never get changed (it falls into the 'x' mask group)
and the first return-from-exception would fail if the chip had powered on
with garbage in the spsr register that included the big-endian bit. It's
unknown why this affected only certain cortex-a9 chips.
strings and include arbitrary information (IRQ line/domain/sense). When the
ofw_bus_map_intr() API was introduced, it assumed that, as on most systems,
these were either 1 cell, containing an interrupt line, or 2, containing
a line number plus a sense code. It turns out a non-negligible number of
ARM systems use 3 (or even 4!) cells for interrupts, so make this more
general.
devices. This is a nop, except for what's reported by atmelbus for the
resources.
It would be nice if we could dymanically allocated these things, but
the pmap_mapdev panics if we don't keep the static mappings, so we
still need to play the carefully allocate VA space between all
supported SoC game.
User's with their own devices may need to make adjustments.
Note that this commit hasn't been compile tested because these files
are not hooked up to the build...
PR: 186129
Submitted by: Takanori Sawada
Approved by: rpaulo
Make comments match parameters
Add options for early printf so we get regression build testing on it.
Add preview of options for FDT support coming soon (I hope)
console, it calls the grab functions. These functions should turn off
the RX interrupts, and any others that interfere. This makes mountroot
prompt work again. If there's more generalized need other than
prompting, many of these routines should be expanded to do those new
things.
Reviewed by: bde (with reservations)
and invoke it for bootverbose logging, and also from a new DDB command,
"show devmap". Also tweak the format string for the bootverbose output
of physical memory chunks to get the leading zeros in the hex values.
this to the cache line size is required to avoid data corruption on armv4
and armv5, and improves performance on armv6, in both cases by avoiding
partial cacheline flushes for USB IO.
this to the cache line size is required to avoid data corruption on armv4
and armv5, and improves performance on armv6, in both cases by avoiding
partial cacheline flushes for USB IO.
All these configs already exist in 10-stable. A few that don't (and
thus can't be MFC'd yet) will be committed separately.
every arm system must have some static mappings to work correctly (although
currently they all do), so remove some panic() calls (which would never
been seen anyway, because they would happen before a console is available).
related to setting up static device mappings. Since it was only used by
arm/mv/mv_pci.c, it's now just static functions within that file, plus
one public function that gets called only from arm/mv/mv_machdep.c.
in the dts source, and adding the right devices to the kernel config. Also
generally bring the kernel config into line with what we have for other
Marvell/Kirkwood systems (add lots of useful devices and options).
One particularly notable addition amongst the kernel config changes is
USB_HOST_ALIGN=32, which may help eliminate data corruption on USB drives.
PR: kern/181975 arm/162159
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
(aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
requests to its parent (nexus). This allows x86 FDT devices to allocate
both memory and IO requests and removes the last notionally MI use of
fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
static device mappings.
This SoC relied heavily on the fact that all devices were static-mapped
at a fixed address, and it (rather bogusly) used bus_space read and write
calls passing hard-coded virtual addresses instead of proper bus handles,
relying on the fact that the virtual addresses of the mappings were known
at compile time, and relying on the implementation details of arm
bus_space never changing. All such usage was replaced with calls to
bus_space_map() to obtain a proper bus handle for the read/write calls.
This required adjusting some of the #define values that map out hardware
registers, and some of them were renamed in the process to make it clear
which were defining absolute physical addresses and which were defining
offsets. (The ones that just define offsets don't appear to be referenced
and probably serve no value other than perhaps documentation.)
and add static mappings that cover most of the on-chip peripherals with
1MB section mappings. This adds about 220MB or so available kva space
by not using a hard-coded 0xF0000000 as the mapping address.
when running on FDT systems. Unmap memory in nexus_deactivate_resource().
Also, call rman_activate_resource() before mapping device memory, and only
do the mapping if it returns success.
Reviewed by: nwhitehorn
searching. If you didn't configure a timer capture pin you'd get a data
abort as it wandered into the weeds, now you get a nice warning message
about your config, as originally intended.
Fix race condition in DELAY function: sc->tc was not initialized yet when
time_counter pointer was set, what resulted in NULL pointer dereference.
Export sysfreq to dts.
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Add suport for setting triggering level and polarity in GIC.
New function pointer was added to nexus which corresponds
to the function which sets level/sense in the hardware (GIC).
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
This seems to cause issues with jemalloc + {dhclient, sshd}.
Thus, revert this for now until the root cause can be found and
fixed.
This should quieten some runtime problems with the Raspberry Pi.
PR: kern/185046
MFC after: 3 days
capture mode together with the timecounter's PPS polling feature to get
very accurate PPS capture without any interrupt processing (or latency).
Hardware timers 4 through 7 have associated capture-trigger input pins.
When the PPS support is compiled in the code automatically chooses the
first timer it finds that has the capture-trigger pin set to input mode
(this is configured via the fdt data).
- Use named constants for register bits, instead of mystery numebrs
scattered around in the code.
- Use inline functions for bus space read/write, instead of macros
that rely on global variables.
- Move the timecounter struct into the softc instead of treating it
as a global variable. Backlink from it to the softc.
- This leaves a pointer to the softc as the only static/global variable
and it's now used only by DELAY().
clients. Mask RX interrupts while grabbed on the atmel serial
driver. This UART interrupts every character. When interrupts are
enabled at the mountroot> prompt, this means the ISR eats the
characters. Rather than try to create a cooperative buffering system
for the low level kernel console, instead just mask out the ISR. For
NS8250 and decsendents this isn't needed, since interrupts only happen
after 14 or more characters (depending on the fifo settings). Plumb
such that these are optional so there's no change in behavior for all
the other UART clients. ddb worked on this platform because all
interrupts were disabled while it was running, so this problem wasn't
noticed. The mountroot> issue has been around for a very very long
time.
MFC after: 3 days
Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural
similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded
boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064.
Approved by: stas (mentor)
completely full, we'd not complete any of the mbufs due to the fence
post error (this creates a large leak). When this is fixed, we still
leak, but at a much smaller rate due to a race between ateintr and
atestart_locked as well as an asymmetry where atestart_locked is
called from elsewhere. Ensure that we free in-flight packets that
have completed there as well. Also remove needless check for NULL on
mb, checked earlier in the loop and simplify a redundant if.
MFC after: 3 days
this change we may end up with a panic (Fatal kernel mode data abort:
'External Non-Linefetch Abort (S)') as described in
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/276862.aspx.
It is now possible to bring up I2C1 and I2C2 on BBB.
Approved by: adrian (mentor)
vm_max_virtual_address to be KERNVIRTADDR + 256MB. This allows some
future shock protection since the KVA requirements have gone up since
the unmapped changes have gone in, as well as preventing us from
overlapping with the hardware devices, which we map at 0xd0000000,
which we'd hit with anything more than 85MB...
MFC after: 3 days
always returning '0' for all the reads, even for the outputs. It is now
known to work with gpioiic(4) and gpioled(4).
Approved by: adrian (mentor)
Tested on: BBB
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.
This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.
A similar change was made in OpenBSD.
Discussed with: -arch, rdivacky
Reviewed by: cperciva
enables data cache and other chip-specific features. It was previously
done via an early SYSINIT, but it was being done after pmap and vm setup,
and those setups need to use mutexes. On some modern ARM platforms,
the ldrex/strex instructions that implement mutexes require the data cache
to be enabled.
A nice side effect of enabling caching earlier is that it eliminates the
multi-second pause that used to happen early in boot while physical memory
and pmap and vm were being set up. On boards with 1 GB or more of ram
this pause was very noticible, sometimes 5-6 seconds.
PR: arm/183740
When entering a mapping via pmap_enter() unmanaged pages ought to be
naturally excluded from the "modified" and "referenced" emulation.
RW permission should be granted implicitly when requested,
otherwise unmanaged page will not recover from the permission fault
since there will be no PV entry to indicate that the page can be written.
In addition, only managed pages that participate in "modified"
emulation need to be marked as "dirty" and "writeable" when entered
with RW permissions. Likewise with "referenced" flag for managed pages.
Unmanaged ones however should not be marked as such.
Reviewed by: cognet, gber
When emulating modified bit the executable attribute was cleared by
mistake when calling pmap_set_prot(). This was not a problem before
changes to ref/mod emulation since all the pages were created RW basing
on the "prot" argument in pmap_enter(). Now however not all pages are RW
and the RW permission can be cleared in the process.
Added proper KTRs accordingly.
Spotted by: cognet
Reviewed by: gber
host.host_ocr, examine the correct field when setting up the hardware. Also,
the offset for the capabilties register should be 0x140, not 0x240.
Submitted by: Ilya Bakulin <ilya@bakulin.de>
Pointy hat to: me
rely only on checking the device unit to indentify the BSC unit we are
attaching to. Make use of the device base address to identify our BSC unit.
Approved by: adrian (mentor)
