sdhci controllers, such as the one on a Raspberry Pi, mishandle the signal
timing in high speed signaling mode, but run just fine in standard mode
with the bus running at frequencies between 25-50MHz (which shouldn't work).
This is the solution adopted by U-Boot and other OSes (linux and *BSD)
for the timeouts on Raspberry Pi boards with certain SD cards. Some
research shows that this quirk is also used on a few other boards, so the
fix is a generic quirk instead of being in the RPi-specific driver code.
This change is based on information discovered by Michal Meloun.
the stack for secondary cores, the other two values are only used for zeroing
bss on the primary core. No need to store the size of the stack at the
top of the stack (seems to be a leftover instruction from some cut-n-paste).
While in theory this should have been a transparent change (and was for all
other drivers), cpsw(4) never used the proper accessor macros in a few
places but spelt the indirect m_hdr.mh_* out itself. Convert those to
use m_len and m_data and unbreak the driver build.
To cut off the power we need to start the shutdown sequence by writing
the OFF bit on PMIC.
Once the PMIC is programmed the SoC needs to toggle the PMIC_PWR_ENABLE
pin when it is ready for the PMIC to cut off the power. This is done by
triggering the ALARM2 interrupt on SoC RTC.
The RTC driver only works in power management mode which means it won't
provide any kind of time keeping functionality. It only implements a way
to trigger the ALARM2 interrupt when requested.
Differential Revision: https://reviews.freebsd.org/D1489
Reviewed by: rpaulo
MFC after: 2 weeks
The driver inherently does dma in 512 byte chunks, but it's possible that
such a buffer can span two physically discontiguous pages (such as when
a userland program does IO on the raw /dev/mmcsdN devices). Now the driver
can handle a buffer that's split across two pages.
It could in theory handle any number of segments now, but as long as IO is
being done in 512 byte blocks it will never need more than two.
requires that each 512 byte IO be in a single contiguous buffer, but if a
buffer crosses a page boundary and the physical pages aren't contiguous
you can get an EFBIG failure (too many segments).
The driver really should handle multiple segment IO, but before adding that
I wanted to make sure that it's handling failure properly while the failure
is easily recreatable.
that some #ifdef SMP code is also conditional on __ARM_ARCH >= 7; we don't
support SMP on armv6, but some drivers and modules are compiled with it
forced on via the compiler command line.
For this to work the driver needs to know the bank it has attached to since
the registers for the first 12 pins are at a different location.
Move the lock initialization to simplify the code.
isn't supposed to manage all the GPIO pins in the system from a single
instance, instead it will attach to each one of the four available GPIO
controllers and only deal with one bank at time (32 pins per bank).
Rework part of the driver to take advantage of that, this simplify the
code a lot.
Also fix a bug in rk30_gpio_get_function() which wouldn't return the
correct values.
While here fix a typo in register name.
code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly
identical and simply redefine a number of constants and helper subroutines;
a generic implementation will make it easier to implement features around
kernel core dumps. This change does not alter any minidump code and should
have no functional impact.
PR: 193873
Differential Revision: https://reviews.freebsd.org/D904
Submitted by: Conrad Meyer <conrad.meyer@isilon.com>
Reviewed by: jhibbits (earlier version)
Sponsored by: EMC / Isilon Storage Division
mostly paves the way for the new pmap code, and shouldn't result in any
noticible behavior differences.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
The ancient gas we've been using interprets .align 0 as align to the
minimum required alignment for the current section. Clang's integrated
assembler interprets it as align to a byte boundary. Fortunately both
assemblers interpret a non-zero value as align to 2^N so just make sure
we have appropriate non-zero values everywhere.
The elftoolchain project includes these additional defines for various
userland programs. Given that arch-specific defines are still interesting
in the context of userland programs reading or writing ELF metadata, they
should be included in top-level ELF headers.
Remove duplicate defines from ARM and MIPS elf headers.
Submitted by: will (initial version)
Reviewed by: imp, will
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D844
raft of new warnings that appear to be on by default in clang 3.5.0.
Fix RPI-B build issues with new clang not liking the ability to pass
arbitrary flags to as, since some flags are more arbitrary (and thus
verboten) than others.
These warnings should be actually fixed in the code, but this is a
band-aide to get things (almost) building again.
end of the actual instruction sequence for the function but before some
misc data in the text segment. This eliminates a strange "size must be
constant" error from the integrated assembler. Also, the build_pagetables
function was missing an END(), but really the problem is that it shouldn't
have an ASENTRY() because it's not a function that needs to be a global
symbol with unwind info and all, it's just a little private subroutine
used in very early kernel init.
the cache before clean/invalidate ensured that no new lines can come into
the cache or migrate between levels during the operation, but may not be
safe on some chips. Instead, if the cache was enabled on entry, do the
wbinv while it's still enabled, and then disable it and do a separate
invalidate pass. After the intitial writeback we know there are no
dirty lines left and no new dirty lines can be created as long as we
carefully avoid touching memory before turning the cache off. Add a
comment about that so no new code gets inserted between those points.
The kernel build machinery really wants the entry point to be in a file
named locore.S so doing this avoids a bunch of changes to the build system
for relatively little benefit.
armv6/7 systems. We need to use some new armv6/7 features at startup
and splitting the implemenations to separate files will be more maintainable
than adding even more #ifdef sections to locore.S.
Because of the standardized interfaces to cache and MMU operations in armv7,
we can tolerate the kernel being entered with caches enabled. This allows
running u-boot and loader(8) with caches enabled, and the performance
improvement can be dramatic (boot times can be cut from over a minute
to under 30 seconds). The new implementation also has more robust cache
and mmu sequences for launching AP cores, and it paves the way for
upcoming changes to the pmap code which will use the TEX remap feature.
Changes in mp_machdep.c work with the new behavior in locore-v6 mp_entry,
and also reuse the original boot-time page tables to get transitioned
from physical to virtual addressing before installing the normal tables.
Submitted by Svatopluk Kraus and Michal Meloun with some changes by me.
the #ifdef stuff at multiple points the functions are called from. Also
rework the armv7 implementations so that the invalidate operations work
from outermost to innermost cache level, and the writeback works from
inner to outer levels.
initially set up the MMU. Some day they may also be useful as part of
suspend/resume handling, when we get better at power management.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
are inline functions that handle all the routine maintenance operations
except the flush-all and invalidate-all routines which are required only
during early kernel init.
These inline functions should be very much faster than the old mechanism
that involved jumping through the big cpufuncs table, especially for
common operations such as invalidating a single TLB entry. Note that
nothing is calling these yet, this just is just required infrastructure
for upcoming changes to the pmap-v6 code.
mechanism defined for armv7 (and also present on some armv6 chips including
the arm1176 used on rpi). The information is parsed into a global cpuinfo
structure, which will be used by (upcoming) new cache and tlb maintenance
code to handle cpu-specific variations of the maintence sequences.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
macro wasn't needed and was being used with swapped arguments which always
give the same result (0) defeating the overflow check.
On initialization, do not use bcm_mbox_intr() to read the pending messages,
with the new semaphore based implementation this will lead to semaphore
being incremented on the channels that contain pending data and will make
the first read for that channel return stale data.
This fixes the hang that happens on boot while initializing the cpufreq on
Raspberry Pi.
According to http://e2e.ti.com/support/arm/sitara_arm/f/791/t/210729 the
USB reset pulse has an undocumented duration of 200ns and during this
period the module must not be acessed.
We wait for 100us to take into account for some imprecision of the early
DELAY() loop.
This fixes the eventual 'External Non-Linefetch Abort (S)' that happens at
boot while resetting the musb subsystem.
While here, enable the USB subsystem clock before the first access.
Discussed with: ian, adrian
MFC after: 2 weeks
This enables the use of GPIO pins as interrupt sources for kernel devices
directly attached to gpiobus (userland notification will be added soon).
The use of gpio interrupts for other kernel devices will be possible when
intrng is complete.
All GPIO pins can be set to trigger on:
- active-low;
- active-high;
- rising edge;
- falling edge.
Tested on: Beaglebone-black
code, passing a 0/1 flag that indicates which type of abort it was. This
sets the stage for unifying the handling of page faults in a single routine.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz
If it seems like this is getting out of hand, I quite agree. I wonder if
it's safe, here in the 21st century, to lose the distinction between C and
ASM symbols?
around so that related things are more grouped together, rewrite comments.
No functional changes, this is all so that the functional changes in the
next commit will stand out.
'extra' entry points which are nested within or provide a synonym name
for another function. It's most likely not safe to be messing with the
IP and LR registers at anything other than the primary entry point to a
function. Anywhere beyond initial function entry, those registers may
be in use as scratch or variable registers.
semicolons between the code and comments instead of after the comments,
and line continuations in the arbitrary but now consistant column 76.
No functional changes.
- Eliminate unused irqframe
- Eliminate unused saframe
- Instead of splitting r4-sp storage between the stack and switchframe,
just put all the registers in switchframe and eliminate the un_32 struct.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>
Fix the following issues:
- Removed revision from device softc, it isn't used anywhere else out of
device attach routine;
- Move the duplicated code for verification of valid banks (and pins) to
a single function;
- Use some macros to simplify the handling of some constants;
- Update some stale comments.
which means that the NFSCLIENT and NFSSERVER
kernel options will no longer work. This commit
only removes the kernel components. Removal of
unused code in the user utilities will be done
later. This commit does not include an addition
to UPDATING, but that will be committed in a
few minutes.
Discussed on: freebsd-fs
exception. In this case no registers will be updated but the link register
will be copied to the program counter to be used to find the calling
function. In this case the program counter may be updated and we should
continue with the trace.
TI OMAP controllers which will return the reset-in-progress bit as zero if
you read the status register too fast after setting the reset bit.
The zero is apparently from a stale snapshot of the internal state presented
in the interface register, and leads to a false indication that the reset
is complete when it either hasn't started yet or is in-progress. The
workaround is to first loop until the bit is seen as asserted, then do the
normal loop waiting to see it de-asserted.
Submitted by: Michal Meloun <meloun@miracle.cz>
can't do a timeout bigger than 15 seconds. The code wasn't checking for
this and because bitmasking was involved the requested timeout was
basically adjusted modulo-16. That led to things like a 128 second
timeout actually being a 9 second timeout, which accidentally worked fine
until watchdogd was changed to only pet the dog once every 10 seconds.
o Move similar block/networking methods to common file
o Follow r275640 and correct MMIO registers width
o Pass value to MMIO platform_note method.
Sponsored by: DARPA, AFRL
far away from a ldr psuedo instruction. With this clang will place the
literal value here where it's close enough to be loaded.
MFC after: 1 week
Sponsored by: ABT Systems Ltd
If this feels like deja vu... the last time this was fixed in this file
only ARM_MMU_V6 was fixed, this time it's ARM_ARCH_V6 (and this time I
searched for other occurrances of pj4b in here).
the first cacheline if the buffer start address is not on a cacheline
boundary. Normally a buffer which is not cacheline-aligned is bounced,
but a special rule applies for mbufs, which are always misaligned due to
the header. We know the cpu will not write to the header while dma is in
progress (so we've been told anyway), but it may have written to the
header shortly before starting a read, so we need to flush that write out
to memory before invalidating the whole buffer.
In collaboration with Mical Meloun and Svata Kraus.
It is automatically set when -fPIC is passed to the compiler.
Reviewed by: dim, kib
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D1179
For OMAP4, the old values for 1MHz gave a bus frequency of about 890KHz.
The new numbers hit 1MHz exactly.
For AM335x the prescaler values are adjusted to give a 24MHz clock for
all 3 standard speeds, as the manual recommends (as near as we can tell,
there are errors and typos apparent in the document). Also, 1MHz speed
is added, and has been tested successfully on a BeagleboneWhite board.
PR: 195009
The current support for controlling i2c bus speed is an inconsistant mess.
There are 4 symbolic speed values defined, UNKNOWN, SLOW, FAST, FASTEST.
It seems to be universally assumed that SLOW means the standard 100KHz
rate from the original spec. Nothing ever calls iicbus_reset() with a
speed of FAST, although some drivers would treat it as the 400KHz standard
speed. Mostly iicbus_reset() is called with the speed set to UNKNOWN or
FASTEST, and there's really no telling what any individual driver will do
with those.
The speed of an i2c bus is limited by the speed of the slowest device on
the bus. This means that generally the bus speed needs to be configured
based on the board/system and the components within it. Historically for
i2c we've configured with device hints. Newer systems use FDT data and it
documents a clock-frequency property for i2c busses. Hobbyists and
developers are likely to want on the fly changes. These changes provide
all 3 methods, but do not require any existing drivers to change to use
the new facilities.
This adds an iicbus method, iicbus_get_frequency(dev, speed) that gets the
frequency for the requested symbolic speed. If the symbolic speed is SLOW
or if there is no speed configured for the bus, the returned value is
100KHz, always. Otherwise, if bus speed is configured by hints, fdt,
tunable, or sysctl, that speed is returned. It also adds a helper
function, iicbus_init_frequency() that any bus driver subclassed from
iicbus can initialize the frequency from some other source of info.
Initial driver implementations are provided for Freescale and TI.
Differential Revision: https://reviews.freebsd.org/D1174
PR: 195009
We used to invalidate the cache for PREREAD alone, or writeback+invalidate
for PREREAD with PREWRITE, then treat POSTREAD as a no-op. Prefetching on
modern systems can lead to parts of a DMA buffer getting pulled into the
caches while DMA is in progress (due to access of "nearby" data), so it's
mandatory to invalidate during the POSTREAD sync even if a PREREAD
invalidate also happened.
In the PREREAD case the invalidate is done to ensure that there are no
dirty cache lines that might get automatically evicted during the DMA,
corrupting the buffer. In a PREREAD+PREWRITE case the writeback which is
required for PREWRITE handling is suffficient to avoid corruption caused
by eviction and no invalidate need be done until POSTREAD time.
Submitted by: Michal Meloun <meloun@miracle.cz>
The PREWRITE handling does a writeback of any dirty cachelines, so there's
no danger of an eviction during the DMA corrupting the buffer. There will
be an invalidate done during POSTREAD, so doing it before the read too is
wasted time.
for cache maintenance operations, but ensure that all prior writes have
reached memory when doing a PREWRITE sync.
Submitted by: Michal Meloun <meloun@miracle.cz>
I originally overlooked a couple flag bits defined in the fdt binding docs.
One flag suppresses the pad configuration (pullup/pulldown/etc). The other
one requires that the SION (set input on) flag be set in the mux register.
Also, it appears from the data involved that if the input register
address in the config tuple is zero, there is no input configuration. The
old code was writing to register zero, which contains a collection of misc
control bits (having nothing to do with input configuration) that probably
shouldn't get overwritten arbitrarily. The bindings doc doesn't explictly
mention this.
that expose new bugs with HS mode.
When the old code could not do the proper card detection it would boot with
lower defaults (and no HS mode) and this makes some HS cards boots.
Now, with the card always identified as HS capable, the sdhci controller
tries to run the card at HS speeds and makes the boot always fail.
Disable the HS mode for now (which still can be enabled with the tunable)
until it is properly fixed.
MFC with: r273264
Requested by: many
have chosen different (and more traditional) stateless/statuful
NAT64 as translation mechanism. Last non-trivial commits to both
faith(4) and faithd(8) happened more than 12 years ago, so I assume
it is time to drop RFC3142 in FreeBSD.
No objections from: net@
It turns out an alignment of zero can lead to an endless loop in the
vm reservations code, so specifically disallow that. The manpage says
hardware which can do dma at any address should use a value of one, which
hints at the forbiddeness of zero without exactly saying it. Several
other conditions which could lead to insanity in working with the tag are
also checked now.
Every existing call to bus_dma_tag_create() (about 680 of them) was
eyeballed for violations of these things, and two alignment=0 glitches
were fixed. It's possible something was missed, but overall this
shouldn't lead to any arm users suddenly experiencing failures.
unit 0.
It seems that this 'simplification' was copied to all GPIO drivers in tree.
This fix a bug where a GPIO controller could fail to attach its children
(gpioc and gpiobus) if another GPIO driver attach first.
and casuword(9), but do not mix value read and indication of fault.
I know (or remember) enough assembly to handle x86 and powerpc. For
arm, mips and sparc64, implement fueword() and casueword() as wrappers
around fuword() and casuword(), which means that the functions cannot
distinguish between -1 and fault.
On architectures where fueword() and casueword() are native, implement
fuword() and casuword() using fueword() and casuword(), to reduce
assembly code duplication.
Sponsored by: The FreeBSD Foundation
Tested by: pho
MFC after: 2 weeks (ia64 needs treating)
Multipass device attachment was tested on many arm platforms by users and
only success was reported on the arm@ mailing list. This is just the
long-delayed followup of making it the default.
Multipass attachment is necessary when using vendor-supplied FDT data,
because our devices may need to be attached in a different order than they
are described in the FDT data.
used for kernel devices it is used by i2c(8).
This fix the 'error: Device not configured' when i2c(8) tries to reset the
controller, as an example:
# i2c -r
Resetting I2C controller on /dev/iic0: error: Device not configured
For now use conservative settings for default i2c speeds.
MFC after: 1 week
For an unkown reason (at moment), sometimes if_cpsw cannot read from PHY
and fails to attach calling cpsw_detach() which end up in a panic.
Fix it by doing the proper check before detach the miibus and also fix the
leak of few variables.
And to actually make it work, ether_ifattach() has to be moved to the end
of cpsw_attach() to avoid a race where calling ether_ifdetach() before
domain_init() (which will only run later on) would make it crash at
INP_INFO_RLOCK() on in_pcbpurgeif0().
Tested on: BBB (am335x)
MFC after: 1 week
the map count and without being able to keep track of the current map
allocation, bus_dma_tag_destroy() will fail to proceed and will return
EBUSY even after all the maps have been correctly destroyed with
bus_dmamap_destroy().
Found while testing the detach method of a NIC.
Tested on: BBB (am335x)
Reviewed by: cognet, ian
MFC after: 1 week
workaround for an imx6 chip erratum. Linux works around the bug with
changes in fdt data that we can't currently handle, so to enable running
with standard vendor-supplied fdt data, this watches for an attempt to map
the gpio1_6 interrupt and remaps it back to the standard ethernet interrupt.
This can be undone when the intrng project is completed and our gpio drivers
can also be interrupt controllers.
for, or that are required to run the chip (such as busses). Turn off all
the devices we don't yet have drivers for.
Some day we will have a fully functional imx6 clock driver so that we can
manage clocks based on fdt data. This will have to do until then.
- Wrong integer type was specified.
- Wrong or missing "access" specifier. The "access" specifier
sometimes included the SYSCTL type, which it should not, except for
procedural SYSCTL nodes.
- Logical OR where binary OR was expected.
- Properly assert the "access" argument passed to all SYSCTL macros,
using the CTASSERT macro. This applies to both static- and dynamically
created SYSCTLs.
- Properly assert the the data type for both static and dynamic
SYSCTLs. In the case of static SYSCTLs we only assert that the data
pointed to by the SYSCTL data pointer has the correct size, hence
there is no easy way to assert types in the C language outside a
C-function.
- Rewrote some code which doesn't pass a constant "access" specifier
when creating dynamic SYSCTL nodes, which is now a requirement.
- Updated "EXAMPLES" section in SYSCTL manual page.
MFC after: 3 days
Sponsored by: Mellanox Technologies
timecounter resolution is available, so ask for a 1 GHz frequency. It
won't actually get one that fast, but that'll get the fastest available
clock and use a divisor of 1 (probably 132 or 66mhz on current hardware).
EWOULDBLOCK.
Do not print any message at errors. The errors are properly sent to upper
layers which should be able to deal with it, including printing the errors
when they need to.
The error message was quite annoying while scanning the i2c bus.
MFC after: 1 week
This fix a race where the threads waiting for the bus would wake up early
and still see bus as busy.
While here, give a better description to wmesg for the two use cases we
have (bus and io waiting).
MFC after: 1 week
will now find the virtual to physical mapping for libkvm to use at
runtime. This makes PHYSADDR redundant, however keep it around to give
everyone a chance to update their libkvm.
MFC after: 1 week
physaddr. This should allow for a kernel where PHYSADDR and KERNPHYSADDR
are both undefined.
For now libkvm will use the old method of reading physaddr and kernaddr
to allow it to work with old kernels. This could be removed in the future
when enough time has passed.
Differential Revision: https://reviews.freebsd.org/D939
MFC after: 1 week
bus_new_pass() handler so it doesn't happen until BUS_PASS_CPU. This allows
the anatop driver to outbid the generic simplebus driver (which the FDT
data describes as compatible).
Some day when we handle power regulators, this driver may actually
become a functional simplebus and attach the regulators as children, as
described in the FDT data.
lose the contents of consecutive writes (that happens within two SD card
clock cycles).
This fixes the causes of instability during the SD card detection and
identification on Raspberry Pi (which happens at 400 kHz and so was much
more vulnerable to this issue).
Remove the previous workaround which clearly can't provide the same effect.
MFC after: 1 week
Relnotes: yes
to be present. Thsi creates a new per-SoC driver that handles probe and
setting/getting the gpio flags.
Differential Revision: https://reviews.freebsd.org/D943
Reviewed by: loos, rpaulo
MFC after: 1 week
The TI watchdog timer is present on BeagleBone's. Since 2014, U-Boot
has been booting the BeagleBone with the watchdog enabled. We need to
disable it on boot to avoid a spurious reset.
The timer isn't exactly precise, but it will do as a watchdog. This
is also a reflection of the watchdog(9) API.
In the future, we could handle interrupts, but the watchdog(9) API
needs to be a bit smarter before that can happen.
Differential Revision: https://reviews.freebsd.org/D965
Reviewed by: andrew
MFC after: 1 week
Relnotes: yes
in userland rename in-kernel getenv()/setenv() to kern_setenv()/kern_getenv().
This fixes a namespace collision with libc symbols.
Submitted by: kmacy
Tested by: make universe
few changes to drivers, no kernel config was added. As the SoCs are quite
old and the code is unmaintained start the process of removing support by
deleting the header file and code that depends on it along with the macro
SOC_OMAP3. Other Ti SoCs shouldn't be affected, other than for us to have
less code to maintain.
Differential Revision: https://reviews.freebsd.org/D936
Reviewed by: rpaulo, loos
registers and use it in the ARMv7 CPU functions.
The sysreg.h file has been checked by hand, however it may contain errors
with the comments on when a register was first introduced. The ARMv7 cpu
functions have been checked by compiling both the previous and this version
and comparing the md5 of the object files.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>
Submitted by: Michal Meloun <meloun at miracle.cz>
Reviewed by: ian, rpaulo
Differential Revision: https://reviews.freebsd.org/D795
When the FreeBSD kernel is loaded from Xen the symtab and strtab are
not loaded the same way as the native boot loader. This patch adds
three new global variables to ddb that can be used to specify the
exact position and size of those tables, so they can be directly used
as parameters to db_add_symbol_table. A new helper is introduced, so callers
that used to set ksym_start and ksym_end can use this helper to set the new
variables.
It also adds support for loading them from the Xen PVH port, that was
previously missing those tables.
Sponsored by: Citrix Systems R&D
Reviewed by: kib
ddb/db_main.c:
- Add three new global variables: ksymtab, kstrtab, ksymtab_size that
can be used to specify the position and size of the symtab and
strtab.
- Use those new variables in db_init in order to call db_add_symbol_table.
- Move the logic in db_init to db_fetch_symtab in order to set ksymtab,
kstrtab, ksymtab_size from ksym_start and ksym_end.
ddb/ddb.h:
- Add prototype for db_fetch_ksymtab.
- Declate the extern variables ksymtab, kstrtab and ksymtab_size.
x86/xen/pv.c:
- Add support for finding the symtab and strtab when booted as a Xen
PVH guest. Since Xen loads the symtab and strtab as NetBSD expects
to find them we have to adapt and use the same method.
amd64/amd64/machdep.c:
arm/arm/machdep.c:
i386/i386/machdep.c:
mips/mips/machdep.c:
pc98/pc98/machdep.c:
powerpc/aim/machdep.c:
powerpc/booke/machdep.c:
sparc64/sparc64/machdep.c:
- Use the newly introduced db_fetch_ksymtab in order to set ksymtab,
kstrtab and ksymtab_size.
We've always considered the mpcore timers to be a single monolithic device
and we defined our own fdt binding for it with our own compat string. The
published bindings treat the timers as two separate devices, a global
timer and a "timer-watchdog" device for the per-cpu private timers. Thus
our binding has two tuples in the regs property, one set of registers for
the global timer and one for the private timers. The published bindings
have two separate devices, each with a single set of registers. (Note that
we don't use the optional watchdog feature of the hardware.)
These changes add the compat strings for the published bindings. If our
own compat string appears, we expect to get two sets of memory resources.
For the published bindings, there's only one set of memory resources, and
only the private timers have an associated interrupt.
The other major change is that there can no longer be a single global var
for the softc pointer because now there may be multiple devices at
runtime. Since the global timer is used only as a timecounter and the
private timers only as eventtimers, and there will only be one of each,
those are now the pointers which are global, and the priv fields of those
structures backlink to the device softc.
In the fdt data we've written for ourselves, the interrupt properties
for GIC interrupts have just been a bare interrupt number. In standard
data that conforms to the published bindings, GIC interrupt properties
contain 3-tuples that describe the interrupt as shared vs private, the
interrupt number within the shared/private address space, and configuration
info such as level vs edge triggered.
The new gic_decode_fdt() function parses both types of data, based on the
#interrupt-cells property. Previously, each platform implemented a decode
routine and put a pointer to it into fdt_pic_table. Now they can just
list this function in their table instead if they use arm/gic.c.
The code had references to both intr_offset and intr_parent variable names
as referring to the parent interrupt node. The intr_parent variable
wasn't actually defined anywhere, but the only references to it were as
an argument to a macro that didn't use that argument in expansion, so
the undefined variable accidentally didn't cause an error.
The intr_parent name makes more sense in context, so change all occurrances
of intr_offset to intr_parent.
nexus_alloc_resource() and don't set a bushandle.
nexus_activate_resource() will set a proper bushandle.
- Implement a proper nexus_release_resource().
- Fix ixppcib_activate_resource() to call rman_activate_resource()
before creating a mapping for the resource.
Tested by: jmg
va == pa map.
I'm not sure the code would work if we are not running from the identity
map as the ARM core may attempt to read the next instruction from an
invalid memory location.
boards.
This is just intended to split the common config entries out, further
cleanup is expected.
Reviewed by: ian@, rpaulo@ (earlier version)
Differential Revision: https://reviews.freebsd.org/D731
o Unmagic 'configuration done' bit
o Move probe() to place before attach() for better navigation
o Use bus_read_n instead of bus_space_read_n functions
Pointed out by: andrew
Sponsored by: DARPA, AFRL
be usable as the default timer in place of the physical timer.
We are guaranteed to have access to the virtual timer, but when running
under a hypervisor may not have access to the physical.
Differential Revision: https://reviews.freebsd.org/D588
few "general purpose registers" whose values control chip behavior in ways
that have nothing to do with IO pin mux control. Define a simple API that
other soc-specific code can use to read and write the registers, and provide
the imx51 implementation of them.
- miibus fixes as suggested by Yonghyeon Pyun.
- enable VLAN MTU support.
- fix a few WITNESS complaints in cgem_attach().
- have cgem_attach() properly init the ifnet struct before calling
mii_attach() to fix panic when using e1000phy.
- fix ethernet address changing.
- fix transmit queue overflow handling.
- tweak receive queue handling to reduce receive overflows.
- bring out MAC statistic counters to sysctls.
- add e1000phy to config file.
- implement receive hang work-around described in reference guide.
- change device name from if_cgem to cgem to be consistent with other
interfaces.
Submitted by: Thomas Skibo <ThomasSkibo@sbcglobal.net>
Reviewed by: wkoszek, Yonghyeon PYUN <pyunyh@gmail.com>
