Commit Graph

657 Commits

Author SHA1 Message Date
Adrian Chadd
33d340324a Correctly handle AR_MoreAggr when assembling multi-descriptor final frames.
Linux ath9k doesn't have this issue as it doesn't try queuing multi-
descriptor frames to the hardware.

Before, I was only setting the first and last descriptor in the final
frame correctly - and that was done by accident. The first descriptor in
the last sub-frame was being correctly updated by ath_tx_setds_11n();
the last descriptor in the last sub-frame was being correctly updated
by ath_buf_set_rate(). But both of those are "incorrect".

The correct behaviour is:

* AR_IsAggr is set for all descriptors for all subframes in an aggregate.
* AR_MoreAggr is set for all descriptors for all non-final sub-frames
  in an aggregate.

Ie, all descriptors in the last sub-frame of an aggregate must have this
field set to 0.

I still need to do a couple of extra passes to ensure the pad delimiter
field is being correctly handled in all descriptors in the last sub-frame.
2012-04-04 21:49:49 +00:00
Adrian Chadd
2fe1131c7b Add a threadid to the ah_decode API.
This adds the current thread ID to each logged register and mark entry,
allowing for easier debugging of concurrent/overlapping NIC operations.
2012-04-04 20:46:20 +00:00
Adrian Chadd
7961e32527 Disable a specific Merlin hardware workaround which may cause hangs on some
PCIe controllers.

Obtained from:	Atheros / Linux
2012-04-04 20:42:32 +00:00
Adrian Chadd
d780702e8b Sprinkle some style(9) things around. 2012-03-22 21:47:14 +00:00
Adrian Chadd
7b1144d245 Break out the radar code into a separate source file.
This mirrors the internal HAL organisation and reduces the differences
between the HAL codebases slightly.

Obtained from:	Atheros
2012-02-20 03:07:07 +00:00
Adrian Chadd
2a4106cfef Fix the return type.
Submitted by:	arundel
Found by:	clang/llvm
2012-02-17 08:45:08 +00:00
Adrian Chadd
5a86e1369c Fix the usefir128 config bit flipping. 2012-02-14 20:06:28 +00:00
Adrian Chadd
cfa5ef068f Improve the radar register config API.
* Fix the "enabled" flag to actually reflect whether radar detection is
  enabled or not.
* Add flags for the relstep/relpwr checks.
2012-02-14 20:05:28 +00:00
Adrian Chadd
2af3b95bf2 Enforce the hardware chainmask when allowing the user to override the
chainmask.

This way a disabled radio chain can't be enabled by a user.
2012-02-10 10:10:41 +00:00
Adrian Chadd
40ffb20de6 Extend the HAL code to allow the RX and TX chainmask to be overridden
by capabilities.

Add an ar5416SetCapability() function, which contains logic to override
the chainmask and update the relevant stream.

This is designed to be called after the attach function, which presets
the TX/RX chainmask and stream.

TODO: check the chainmask against the hardware chainmask so non-existing
chains aren't enabled.
2012-02-10 09:58:20 +00:00
Adrian Chadd
1db689c583 Support AR9281/AR5B91 - a 1x2 stream device based on the AR9280.
* Override the TX/RX stream count if the EEPROM reports a single RX or
  TX stream, rather than assuming the device will always be a 2x2 strea
  device.

* For AR9280 devices, don't hard-code 2x2 stream.  Instead, allow the
  ar5416FillCapabilityInfo() routine to correctly determine things.

The latter should be done for all 11n chips now that
ar5416FillCapabilityInfo() will set the TX/RX stream count based on the
active TX/RX chainmask in the EEPROM.

Thanks to Maciej Milewski for donating some AR9281 NICs to me for
testing.
2012-01-31 22:31:16 +00:00
Adrian Chadd
7f925de11a Radar API related fixes.
* For legacy NICs, the combined RSSI should be used.
  For earlier AR5416 NICs, use control chain 0 RSSI rather than combined
  RSSI.
  For AR5416 > version 2.1, use the combined RSSI again.

* Add in a missing AR5212 HAL method (get11nextbusy) which may be called
  by radar code.

This serves no functional change for what's currently in FreeBSD.
2012-01-30 23:07:27 +00:00
Adrian Chadd
a86e181b4c Break out the "memory" EEPROM data read method from being AR9130 specific
to being more generic.

Other embedded SoCs also throw the configuration/PCI register
info into flash.

For now I'm just hard-coding the AR9280 option (for on-board AR9220's on
AP94 and commercial designs (eg D-Link DIR-825.))

TODO:

* Figure out how to support it for all 11n SoC NICs by doing it in
  ar5416InitState();
* Don't hard-code the EEPROM size - add another field which is set
  by the relevant chip initialisation code.
* 'owl_eep_start_loc' may need to be overridden in some cases to 0x0.
  I need to do some further digging.
2012-01-15 19:22:34 +00:00
Adrian Chadd
f5d9d54516 .. the AR5416 HAL code touches the MIMO parts in HAL_CHANNEL,
so this is also needed.

Pointed out by:	bz
2012-01-07 20:23:05 +00:00
Adrian Chadd
ac2dae5070 Commit a temporary workaround for people who are building kernels
where they've disabled all the wireless devices/framework.

This is just a build workaround. If you're actively using wireless,
you must still define AH_SUPPORT_AR5416 as I'm not sure what else
will break!

The real solution is to make the module build depend if AH_SUPPORT_AR5416
is defined, as well as make the 11n code in if_ath_tx.c and if_ath_tx_ht.c
completely optional (maybe depend upon ATH_SUPPORT_11N.)
2012-01-07 20:13:55 +00:00
Dimitry Andric
a3388f6d69 Reapply r228785 now it has been tested by Adrian. Also add comments
with the old AR_SCR_SLE_XXX values, with a short explanation why they
were changed.

Reviewed by:	adrian
MFC after:	1 week
2011-12-30 02:58:37 +00:00
Adrian Chadd
613f73a82d AR5416 has 14 GPIO pins, from 0->13. 2011-12-26 08:21:29 +00:00
Adrian Chadd
2942e03f5c Update the hardware LED blinking code to do something useful rather than
relying on what the register defaults are.

This forces the blink mode to be proportional to the TX and RX frames
which match the RX filter.

This (along with a few tweaks to if_ath_led.c to configure the correct
GPIO pins) allows my DWA-552 AR5416 NIC to blink the LEDs in a useful
fashion, however those LEDs are marked "Link" and "Act(ivity)", which
don't really map well to the "power" / "network" LED interface which
the MAC provides. Some further tinkering is needed to see what other
useful operating modes are possible.
2011-12-26 06:07:21 +00:00
Adrian Chadd
252b52fd58 Disable the code which hard-sets the LEDs on. This prevents the LED
state from correctly updating things.

The reference driver directly enables/disables the LED state as required,
rather than nailing it up like it currently is.  That'll have to come
later by adding some further HAL methods.

Obtained from:	Atheros
2011-12-23 09:09:10 +00:00
Adrian Chadd
b5e55cb397 Port over some more GPIO fixes from the atheros reference HAL.
* Bring the AR5416 GPIO mux mask code in line with the code from the
  HAL.

* Add HAL_DEBUG_GPIO debugging statements, to track what's going on.

* Add Kiwi GPIO specific changes for reading values back.

Obtained from:	Atheros
2011-12-23 08:53:22 +00:00
Adrian Chadd
e81f85f155 Port over some GPIO and LED fixes.
* As a preparation for AR9287 GPIO support, add in the AR9287 GPIO mask.
* Fix the association mask values; these are post-shift values but were
  being shifted in twice. This resulted in some garbage being written
  in the wrong place and the link LED (at least on my d-link AR5416
  NIC) giving totally incorrect blink patterns.
2011-12-23 08:32:53 +00:00
Adrian Chadd
153bf8fbd3 Remove unused #define's.
Pointy hat to: adrian, for not properly reading things when he copied
  ar9285.h to ar9287.h.
2011-12-23 04:05:39 +00:00
Adrian Chadd
ead079638f Use the correct types when calling the decompression mask function.
There's currently no public code which uses this feature and the
current reference driver doesn't enable this feature at all.
It's possible it was used by a previous version of the driver and
that indeed it should return HAL_STATUS; but at this point I'm
happy to require that they complain and submit a patch.

This was found by LLVM compile-time type checking.

Submitted by:	dim
2011-12-22 21:54:53 +00:00
Dimitry Andric
38d3d227ed Revert r228786. We'll need to work around the warnings in another way.
Requested by:	adrian
MFC after:	1 week
2011-12-22 14:09:08 +00:00
Dimitry Andric
a6c1d38f59 Revert r228785. We'll need to work around the warnings in another way.
Requested by:	adrian
MFC after:	1 week
2011-12-22 13:47:36 +00:00
Dimitry Andric
6831e3178a Fix enum conversion problems in sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
and sys/dev/ath/ath_hal/ar5416/ar5416_misc.c:

sys/dev/ath/ath_hal/ar5212/ar5212_misc.c:577:24: warning: implicit conversion from enumeration type 'HAL_STATUS' to different enumeration type 'HAL_BOOL' [-Wconversion]
                return HAL_EINVAL;
                ~~~~~~ ^~~~~~~~~~

and:

sys/dev/ath/ath_hal/ar5416/ar5416_misc.c:164:9: warning: implicit conversion from enumeration type 'HAL_STATUS' to different enumeration type 'HAL_BOOL' [-Wconversion]
        return HAL_OK;
        ~~~~~~ ^~~~~~

In both cases, enums HAL_BOOL and HAL_STATUS are mixed up.

MFC after: 1 week
2011-12-21 17:36:45 +00:00
Dimitry Andric
46fb42dc9d Fix shift overflow problem in sys/dev/ath/ath_hal/ar5210/ar5210_power.c
and sys/dev/ath/ath_hal/ar5211/ar5211_power.c:

sys/dev/ath/ath_hal/ar5210/ar5210_power.c:36:3: warning: signed shift result (0x200000000) requires 35 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_ALLOW);
                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
sys/dev/ath/ath_hal/ah_internal.h:472:42: note: expanded from:
                (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
                                                       ^
sys/dev/ath/ah_osdep.h:127:49: note: expanded from:
            (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
                                                       ^~~~

The AR_SCR_SLE_{WAKE,SLP,NORM} values are pre-shifted in ar5210reg.h and
ar5211reg.h, while they should be unshifted, like in ar5212reg.h.  Then,
when the OS_REG_RMW_FIELD() macro shifts them again, the values will
overflow, becoming effectively zero.

MFC after: 1 week
2011-12-21 17:16:43 +00:00
Adrian Chadd
4473d4da67 Add the 11n chipset RF frontends to the linker set, even though they're not
attached this way.

The AR5212 based NICs have a variety of RF frontends, so there's a linker set
which the AR5212 attach routine calls. The same framework is used for the
AR5416 and later but as there's a fixed RF frontend for each 11n NIC, it
is just directly attached.

However in the case of compiling a cut down HAL (eg _just_ AR9130 WMAC support),
the linker set ends up being empty and this causes the compile to fail.

So this is just a workaround for that - it means those users who wish an 11n
only HAL can compile the 11n chipsets and RF frontend they need, and just
"ath_ar5212" for the AR5212/AR5416 common code, and it'll just work.

Sponsored by:	Hobnob, Inc.
2011-12-15 00:59:11 +00:00
Adrian Chadd
7f4245c1b3 Use the correct RF version probe routine.
Obtained from:	Atheros
Sponsored by:	Hobnob, Inc.
2011-12-15 00:54:11 +00:00
Adrian Chadd
6bf0b868ce Add some (totally untested!) code to correctly set the RF half/quarter
mode configuration registers. This is apparently required for correct
behaviour, but also requires the chip to actually officially support it.

Sponsored by:	Hobnob, Inc.
2011-11-19 21:12:35 +00:00
Adrian Chadd
a3909ec506 Disable writing to the extension CYCPWR1 register.
This seems to make ANI behave better on the AR5416/AR5418.

Sponsored by:	Hobnob, Inc.
2011-11-12 16:47:23 +00:00
Adrian Chadd
9ddf14906a Correct device id comments. 2011-11-11 00:48:41 +00:00
Adrian Chadd
cf5d42d4b0 Bump this up to where it used to be.
I need to investigate this a little closer, but it seems that in noisy
environments the NF load takes longer than 5 * DELAY(10) and this is
messing up future NF calibrations. (The background: NF calibrations
begin at the value programmed in after the load has completed, so
if this is never loaded in, the NF calibrations only ever start at
the currently calibrated NF value, rather than starting at something
high (say -50.)

More investigation about the effect on 11n RX and calibration results
are needed.

Sponsored by:	Hobnob, Inc.
2011-11-09 23:28:47 +00:00
Adrian Chadd
ddbe3036e5 Introduce a work-around for issues with the AR5416 based MAC on SMP devices.
The AR5416 MAC (which shows up in the AR5008, AR9001, AR9002 devices) has
issues with PCI transactions on SMP machines. This work-around enforces
that register access is serialised through a (global for now) spinlock.

This should stop the hangs people have seen with the AR5416 PCI devices
on SMP hosts.

Obtained by:	Linux, Atheros
2011-11-09 22:39:44 +00:00
Adrian Chadd
b07bd63bfe Commit a missing fix - the AR_SREV_KIWI_10_OR_LATER() check. 2011-11-09 21:41:18 +00:00
Adrian Chadd
3ca6cfa89e Even though the HAL doesn't currently support Kiwi 1.0/1.1,
be "more correct" about the Kiwi setup.

Obtained from:	Atheros
2011-11-09 19:09:03 +00:00
Adrian Chadd
ac3fb727ff * Force the MAC to wakeup before we try resetting it, to ensure
it actually _gets_ reset properly.
* Add some more comments describing why things are done.

Obtained from:	Atheros
2011-11-09 14:34:25 +00:00
Adrian Chadd
985c86c038 Tidy up the AR9287 HAL a tiny bit - fix up AR9280 references. 2011-11-09 14:30:58 +00:00
Adrian Chadd
2e4464a4af Migrate the AR5416 ANI code to use the previously introduced method
to fetch the current channel busy statistics, rather than duplicating
it here.

This forms the (very crude) basis for doing basic channel surveying.

Sponsored by:	Hobnob, Inc.
2011-11-09 05:48:20 +00:00
Adrian Chadd
26ae0bb475 Disable OFDM weak signal detection by default. Leave this to be
enabled if required by STA operation.

This quietens a lot of OFDM errors seen in hostap mode, where
there are no beacon RSSI levels to tune the dynamic range of the
baseband.

This may reduce reception range at the fringes, but does increase
stability.

Sponsored by:	Hobnob, Inc.
2011-11-09 05:45:30 +00:00
Adrian Chadd
eb81a8f672 Use a restricted set of parameters when operating in hostap mode.
The 5ghz hostap mode (where DFS is being done) requires ANI to be disabled
or the radar detection parameters don't work as advertised (as they're based
on signal strength level, and tweaking ANI affects the signal strangth,
dynamic range and power increase the baseband is looking for in order to
detect it as a "signal".)

Obtained from:	Linux, Atheros
Sponsored by:	Hobnob, Inc.
2011-11-09 05:43:48 +00:00
Adrian Chadd
7f6a8cca83 Add logic to ANI to tweak the firstep parameter when in hostap mode.
This is normally done based on the beacon RSSI but this isn't available
in hostap mode.

Obtained from:	Atheros
Sponsored by:	Hobnob, Inc.
2011-11-09 05:41:40 +00:00
Adrian Chadd
fcf3bb80d5 .. and add some ANI fixes missing from the last ANI commit.
Obtained from:	Atheros
Sponsored by:	Hobnob, Inc.
2011-11-09 05:39:17 +00:00
Adrian Chadd
581449cb66 Include some ANI fixes for the AR5416.
* If we fall through from an ANI command (eg because it's out of range,
  or it's disabled) then fall through to the next ANI command rather then
  being stuck there.

* Fix some off-by-one comparisons, meaning the final level in some parameters
  were never tweaked.

Obtained from:	Atheros
Sponsored by:	Hobnob, Inc.
2011-11-09 05:37:11 +00:00
Adrian Chadd
d3054f72e0 Add a new HAL parameter which forces a full reset rather than warm reset.
This forces a full reset of the baseband/radio and seems needed to clear
some issues (with Merlin at least) when the baseband gets confused in a
very noisy environment.

Sponsored by:	Hobnob, Inc.
2011-11-09 05:30:24 +00:00
Adrian Chadd
a1dd224b99 Port over a new routine which grabs the percentage of time spent in TX frame, RX frame,
RX clear, RX extension clear.

This is useful for estimating channel business.

The same routines should be written for AR5210->AR5212 where appopriate.

Obtained from:	Atheros
2011-11-09 05:25:30 +00:00
Adrian Chadd
020d7846cb Add in some more PCI/PCIe differentiation. 2011-11-09 04:38:27 +00:00
Adrian Chadd
5b77f8e9f5 Try to make it more obvious when users are using the PCI or PCIe versions of
the 11n chips.
2011-11-09 04:35:33 +00:00
Adrian Chadd
31fdf3d6d2 Fix the KTR option to compile by default - it was referencing
some unmerged interrupt status debugging code from my branch.

* Add ah_intrstate[8] which will have the record of the last
  call to ath_hal_getintr().
* Wrap the KTR code behind ATH_KTR_INTR_DEBUG.
* Add the HAL interrupt debugging behind AH_INTERRUPT_DEBUGGING.

This is only done for the AR5416 and later NICs but it will be
trivial to add to the earlier NICs if required.

Neither are enabled by default, although to minimise HAL binary
API differences, the ah_intrstate[] array is always compiled into
the ath_hal struct.
2011-11-08 22:50:28 +00:00
Adrian Chadd
543d97bb43 Call the correct chipset power routine when disabling the AR5416 and later NICs. 2011-11-04 13:32:13 +00:00
Adrian Chadd
d79ac7a74f Add in some more 11n related HAL methods. 2011-10-25 23:33:54 +00:00
Adrian Chadd
e674b5f30d The AR5413 datasheet specifies that AR_TxIntrReq should be set consistently
for all frames, so do so.
2011-10-25 23:28:16 +00:00
Adrian Chadd
6897698afe Add some fixes to the 11n aggregation HAL calls:
* preserve AR_TxIntrReq on every descriptor in an aggregate chain,
  not just the first descriptor;
* always blank out the descriptor in ar5416ChainTxDesc() when forming
  aggregates - the way I'm using this in the 11n branch is to first
  chain aggregates together, then use the other HAL calls to fill in
  the details.
2011-10-25 23:24:05 +00:00
Adrian Chadd
00d829dae7 Correct/complete a partially-disabled TX interrupt mitigation configuration.
Although a previous commit disabled TX interrupt mitigation handling and
configuration, the mask register bits weren't setup correctly.
2011-10-25 23:17:53 +00:00
Adrian Chadd
9ff4b713b2 Fix an incorrect flag.
Obtained from:	Atheros
2011-10-25 23:14:40 +00:00
Adrian Chadd
0047ff7096 Save and restore the association ID across interface resets.
Obtained from:	Atheros
MFC after:	1 week
2011-10-25 23:13:36 +00:00
Adrian Chadd
5916ef68df Add some 11n bits from the if_ath_tx 11n branch:
* Add the TID field in the TX status descriptor;
* Add in the 11n first/middle/last functions for fiddling
  with the descriptors. These are from the Linux and the
  reference driver, but I'm not (currently) using them.
* Add further AR_ISR_S5 register definitions.

Obtained from:	Linux ath9k, Atheros
2011-10-25 23:09:07 +00:00
Adrian Chadd
24f5f7ee4e Reduce the NF wait timeout. When doing heavy 11n RX loads, this can actually
interfere with traffic, as the NF load can take quite a while and poking the
AGC every 10uS is just a bit silly.

Instead, just leave the baseband NF calibration where it is and just read it
back next time a longcal interval happens.
2011-10-25 23:01:53 +00:00
Adrian Chadd
0cbbe87008 Port over some missing code from the ar5212 reference driver reset path.
The final missing bit here is enabling the PCI configuration register
read, but there's currently no glue available for the HAL to read (and
write) PCI configuration space registers.

Obtained from:	Atheros
2011-10-18 03:17:06 +00:00
Adrian Chadd
46614948dd Implement the first part of the BB read workaround.
The AR5008/AR9001 series NICs have a bug where BB register reads
will occasionally be corrupted. This could cause issues with things
such as ANI, which adjust operational parameters based on the
BB radio register reads. This was introduced in the AR5008 chip
and fixed with the first released AR9002 series NIC (AR9280v2.)

A followup commit will implement the acutal WAR when reading
BB registers. I'm still not sure how I'll implement it - whether
it should be done in the osdep layer, or whether it should just
live in the AR5416 HAL. Either way, they can use this capability
bit to determine whether to implement the WAR or not.

Thankyou to various sources inside Atheros who have helped me track
down what this particular issue is.

Obtained from:	Atheros
2011-10-18 03:01:41 +00:00
Adrian Chadd
31a47d8c14 Add in OS_REG_BIT_SET, a macro which does what it says it does.
This will be used in an upcoming commit to the ar5212 HAL.
2011-10-18 02:46:26 +00:00
Adrian Chadd
a57433b96b Add an AR5416 aware version of the "current RSSI" function.
Pre-11n devices and AR5416 use AR_PHY(263) for current RX RSSI.
AR9130 and later have a fourth calibration register (for doing
ADC calibration) and thus the register has moved to AR_PHY(271).

This isn't currently used by any of the active code; I'm committing
this for completeness and in case any third party code attempts to
use it for legacy reasons.
2011-10-04 00:32:10 +00:00
Adrian Chadd
f6f6e2c803 Port over the radar pulse decoding code common to the AR5416 and later chipsets.
Obtained from:	Atheros
2011-10-03 12:12:03 +00:00
Adrian Chadd
f20aaceeb4 Remove an unused variable. 2011-10-02 14:10:25 +00:00
Adrian Chadd
62f62f4f4a Various interrupt handling and RX interrupt mitigation fixes.
* The AR_ISR_RAC interrupt processing method has a subtle bug in all
  the MAC revisions (including pre-11n NICs) until AR9300v2.
  If you're unlucky, the clear phase clears an update to one of the
  secondary registers, which includes TX status.

  This shows up as a "watchdog timeout" if you're doing very low levels
  of TX traffic. If you're doing a lot of non-11n TX traffic, you'll
  end up receiving a TX interrupt from some later traffic anyway.

  But when TX'ing 11n aggregation session traffic (which -HEAD isn't yet
  doing), you may find that you're only able to TX one frame (due to
  BAW restrictions) and this may end up hitting this race condition.

  The only solution is to not use RAC and instead use AR_ISR and the
  AR_ISR_Sx registers. The bit in AR_ISR which represents the secondary
  registers are not cleared; only the AR_ISR_Sx bits are. This way
  any updates which occur between the read and subsequent write will
  stay asserted and (correctly) trigger a subsequent interrupt.

  I've tested this on the AR5416, AR9160, AR9280. I will soon test
  the AR9285 and AR9287.

* The AR_ISR TX and RX bits (and all others!) are set regardless of
  whether the contents of the AR_IMR register. So if RX mitigation is
  enabled, RXOK is going to be set in AR_ISR and it would normally set
  HAL_INT_RX.

  Fix the code to not set HAL_INT_RX when RXOK is set and RX mitigation
  is compiled in. That way the RX path isn't prematurely called.

  I would see:

  * An interrupt would come in (eg a beacon, or TX completion) where
    RXOK was set but RXINTM/RXMINT wasn't;
  * ath_rx_proc() be called - completing RX frames;
  * RXINTM/RXMINT would then fire;
  * ath_rx_proc() would then be called again but find no frames in the
    queue.

  This fixes the RX mitigation behaviour to not overly call ath_rx_proc().

* Start to flesh out more correct timer interrupt handling - it isn't
  kite/merlin specific. It's actually based on whether autosleep support
  is enabled or not.

This is sourced from my 11n TX branch and has been tested for a few weeks.

Finally, the interrupt handling change should likely be implemented
for AR5210, AR5211 and AR5212.
2011-10-02 14:08:56 +00:00
Adrian Chadd
7e132ca3e3 Document exactly what the RX interrupt mitigation timers do. 2011-10-02 13:51:26 +00:00
Adrian Chadd
75350906bc For now (ie: until autosleep support is fully fleshed out), always clear
all of the RX status fields when initialising a new RX descriptor.
2011-10-02 13:47:03 +00:00
Adrian Chadd
9bf15204ae Disable TX interrupt mitigation just for the time being.
There are some timing concerns which I've yet to fully map out.
In any case, there's an existing software driven mitigation method
for TX interrupts and when TX'ing 11n frames, the whole frame itself
generates an interrupt rather then the subframes.
2011-10-02 13:43:06 +00:00
Adrian Chadd
0e56140a1b Fix a corner case in the HAL debugging changes, where ah was NULL.
Although I tried to fix this earlier by introducing HALDEBUG_G(), it
turns out there seem to be other cases where the pointer value is still
NULL.

* Fix DO_HALDEBUG() and the HALDEBUG macro to check whether ah is NULL
  before deferencing it
* Remove HALDEBUG_G() as it's no longer needed

This is hopefully a merge candidate for 9.0-RELEASE as enabling
debugging at startup could result in a kernel panic.
2011-09-30 05:17:57 +00:00
Adrian Chadd
353d29772b Change the default CABQ time to be 70% of the beacon interval,
rather than the whole beacon interval.

The reference driver and Linux ath9k both choose 80% of the
beacon interval and they do it in the driver rather than
the HAL (Ath reference) or ath9k_hw (ath9k.)

This quietens stuck beacon conditions on my AR9220/AR9280
based NICs when a lot of burst broadcast/multicast traffic
is going on. It doesn't seem to annoy the earlier MACs as
much as the AR9280 and later one.

Obtained from:	Linux ath9k, Atheros
2011-09-28 03:05:04 +00:00
Adrian Chadd
c3f2102bef The AR5212 setup path (also used by the AR5416 code) configures a
local variable with a beacon interval of 100 TU. This never gets modified
if the beacon interval configuration changes.

This may have been correct in earlier times, but with the advent of
staggered beacons (which default to 1 / ATH_BCBUF beacon interval, so
25 TU here) this value is incorrect.

It is used to configure the default CABQ readytime. So here, the cabq
was being configured to be much greater than the target beacon timer
(TBTT.)

The driver should be configuring a cabq readytime value rather then
leaving it to the HAL to choose sensible defaults. This should be
done in the future - I'm simply trying to ensure sensible defaults
are chosen.
2011-09-28 03:03:23 +00:00
Adrian Chadd
fc4de9b7fc Update the TSF and next-TBTT methods to work for the AR5416 and later NICs.
This is another commit in a series of TDMA support fixes for the 11n NICs.

* Move ath_hal_getnexttbtt() into the HAL; write methods for it.
  This returns a timer value in TSF, rather than TU.

* Move ath_hal_getcca() and ath_hal_setcca() into the HAL too, where they
  likely now belong.

* Create a new HAL capability: HAL_CAP_LONG_RXDESC_TSF.
  The pre-11n NICs write 15 bit TSF snapshots into the RX descriptor;
  the AR5416 and later write 32 bit TSF snapshots into the RX descriptor.
* Use the new capability to choose between 15 and 31 bit TSF adjustment
  functions in ath_extend_tsf().

* Write ar5416GetTsf64() and ar5416SetTsf64() methods.
  ar5416GetTsf64() tries to compensate for TSF changes at the 32 bit boundary.

According to yin, this fixes the TDMA beaconing on 11n chipsets and TDMA
stations can now associate/talk, but there are still issues with traffic
stability which need to be investigated.

The ath_hal_extendtsf() function is also used in RX packet timestamping;
this may improve adhoc mode on the 11n chipsets. It also will affect the
timestamps seen in radiotap frames.

Submitted by:	Kang Yin Su <cantona@cantona.net>
Approved by:	re (kib)
2011-09-08 01:23:05 +00:00
Adrian Chadd
c62055f6de Add a definition for ASYNC_CAUSE_CLR. It's not used yet, but the
reference driver does clear the async interrupts after each service.
I'll tinker with this in a future commit.

Obtained from:	Atheros
Approved by:	re (kib)
2011-09-07 03:00:58 +00:00
Adrian Chadd
aacc74998a Fix 5ghz calibration logic when using AR9280 w/ fast clock.
When the fast clock (44mhz) is enabled for 5ghz HT20, the
dual ADCs aren't enabled. Trying to do the ADC calibrations
here would result in calibration never completing; this
resulted in IQ calibration never running and thus performance
issues in 11a/11n HT20 mode.

Leave it enabled for non-fastclock (40mhz) 11a mode and
HT40 modes.

This has been fixed in discussion with Felix Fietkau (nbd)
and discussions with the Atheros baseband team.

Linux ath9k now has a similar fix.

Approved by:	re (kib)
2011-09-06 10:54:56 +00:00
Adrian Chadd
d497ffcab4 Fix the addac serial load register write for AR5416.
Obtained from:	Linux, Atheros
Approved by:	re (kib)
2011-09-06 10:49:05 +00:00
Adrian Chadd
607756e9de TIM/Timer fixes for AR5416 and later:
* Fix SLEEP1/SLEEP2 register definitions; the CAB/Beacon timeout
  fields have changed in AR5416 and later
* The TIM_PERIOD and DTIM_PERIOD registers are now microsecond fields,
  not TU.

Obtained from:	Linux ath9k, Atheros reference
Approved by:	re (kib, blanket)
2011-08-24 00:45:53 +00:00
Adrian Chadd
34ff1d08f6 These timer registers are all 1uS in resolution in AR5416
or later. Previous hardware had some as TU, some as 1/8th
TU.

* Modify AR_NEXT_DBA and AR_NEXT_SWBA to use a new macro,
  ONE_EIGHTH_TU_TO_USEC(), which converts the 1/8th TU
  fields to USEC. This is just cosmetic and matches the
  Atheros reference driver.

* Fix AR_NEXT_TBTT, which is USEC, not TU.

Submitted by:	paradyse@gmail.com
Approved by:	re (kib, blanket)
2011-08-23 13:36:09 +00:00
Adrian Chadd
ffae5d00d2 Bitten again by the optional HALDEBUG compilation.
Remove this debugging, it's not needed anymore and when not enabled,
those variables trigger a compiler warning.

Approved by:	re (kib, blanket)
Pointy-hat-to:	adrian, for not testing a non-debug compile of this code enough
2011-08-08 18:05:22 +00:00
Adrian Chadd
7dd4de1301 The older HAL code sets up the regulatory domain once; FreeBSD/net80211
allows it to be overridden at runtime.

Thus, add a function which updates ah_dfsDomain after a channel set
call to ath_hal_set_channels().

Approved by:	re (kib, blanket)
2011-08-08 17:33:35 +00:00
Adrian Chadd
8db87e4079 Introduce some more DFS related hooks, inspired both by local work
and the Atheros reference code.

The radar detection code needs to know what the current DFS domain is.
Since net80211 doesn't currently know this information, it's extracted
from the HAL regulatory domain information.

The specifics:

* add a new ath_dfs API hook, ath_dfs_init_radar_filters(), which
  updates the radar filters whenever the regulatory domain changes.
* add HAL_DFS_DOMAIN which describes the currently configured DFS domain .
* add a new HAL internal variable which tracks the currently configured
  HAL DFS domain.
* add a new HAL capability, HAL_CAP_DFS_DMN, which returns the currently
  configured HAL DFS domain setting.
* update the HAL DFS domain setting whenever the channel setting is
  updated.

Since this isn't currently used by any radar code, these should all
be no-ops for existing users.

Obtained from:	Atheros
Submitted by:	KBC Networks, sibridge
Approved by:	re (kib, blanket)
2011-08-08 16:22:42 +00:00
Adrian Chadd
60829c4817 Add another HAL method - ah_isFastClockEnabled - which returns AH_TRUE
if 5ghz fast clock is enabled in the current operating mode.

It's slightly dirty, but it's part of the reference HAL and used by
the (currently closed-source) radar event code to map radar pulses
back to microsecond durations.

Obtained from:	Atheros
Approved by:	re (kib, blanket)
2011-08-08 13:15:39 +00:00
Adrian Chadd
625b09b021 Undo this for now. It's "right", but it means everything will rely on
the ar9130 code.

Since at least one kernel config specifies individual ath HAL chips
rather than just "device ath_hal" (arm/AVILA), I'm doing this so people
aren't caught out when they update to -HEAD or 9.0 and discover their
ath setup doesn't compile.

I'll revisit this with a proper fix sometime before 9.0-RELEASE.

Approved by:	re (kib, blanket)
Pointed out by:	ray@
Pointy hat to:	adrian@
2011-08-03 23:57:38 +00:00
Adrian Chadd
844537c1e0 Add in a dirty hack that allows for AR9280/AR9285/AR9287 embedded
systems, in the same way that AR9130 embedded systems work.

This isn't -everything- that is required - the PCI glue still
needs to be taught about the eepromdata hint, along the same
lines as the AHB glue.

Approved by:	re (kib, blanket)
2011-08-03 13:39:11 +00:00
Adrian Chadd
b1698e1f6b * Fix a clash in structure naming which occurs with (closed source)
radar detection code. This is just to make porting the atheros
  radar code easier.

* add a missing space.

Approved by:	re (kib, blanket)
2011-08-03 13:36:14 +00:00
Adrian Chadd
52227d94df Remove the EEPROM minor >= 19 check for txgaintype; that's only needed for
Merlin / v14 eeprom formats.

Approved by:	re (kib, blanket)
2011-08-03 06:51:14 +00:00
Adrian Chadd
44ade163ce Add extra flags for the radar event API.
(They're not used by any public code at the current time.)

Approved by:	re (kib)
2011-07-31 05:01:42 +00:00
Adrian Chadd
6eec7effeb Add some more phyerr bits.
Obtained from:	Atheros
Approved by:	re (kib)
2011-07-31 03:33:02 +00:00
Adrian Chadd
7239f9f75b Introduce the FRAC_5G EEPROM parameter.
This seems to indicate whether to program the NIC for fractional 5ghz
mode (ie, 5mhz spaced channels, rather than 10 or 20mhz spacing) or not.
The default (0) seems to mean "only program fractional mode if needed".
A different value (eg 1) seems to always enable fractional 5ghz mode
regardless of the frequency.

Obtained from:	Atheros
Approved by:	re (kib)
2011-07-30 13:45:12 +00:00
Adrian Chadd
b649b13f03 Prepare for embedded use of the AR9285/AR9287.
Calibration/PCI data that's written to flash (rather than EEPROM attached
to the NIC) is typically already in host-endian. The existing checks
end up swapping 16 bit words incorrectly - the correct solution would be
to read the magic value and determine the EEPROM endianness from that.
(This is what Linux does.)

This doesn't completely enable embedded use of the AR9285/AR9287 -
notably, the EEPROM read methods need to be made generic and available
to all EEPROM drivers. I'll worry about that later.

Approved by:	re (kib)
2011-07-30 13:37:38 +00:00
Adrian Chadd
bb40c7e83f Fix AR5416 radar parameter initialisation.
* I messed up the order of parameter true/false; oops!
* AR_PHY_RADAR_1 was being written at the wrong place, and was writing
  potential garbage to the hardware.

Approved by:	re (kib)
2011-07-30 13:34:57 +00:00
Adrian Chadd
78b72aff33 Fix the initial calibration sample count when doing ADC calibrations.
Obtained from:	Atheros
Approved by:	re (kib)
2011-07-30 13:31:27 +00:00
Adrian Chadd
e875139a4f Fix ANI handling to work correctly when (trying) to receive radar errors.
* Teach the AR5212/AR5416 ANI code to use the RX filter methods, rather
  than calling the RX filter routines directly.

* Make HAL_ANI_PRESENT and HAL_ANI_MODE unconditionally available,
  regardless of whether ah_ani_function is masking it.

* (Mostly) fully disable ANI if interference mitigation is disabled.
  When disabled, the ANI code doesn't touch any ANI/PHY registers,
  leaving them the default value. This is in line with what the
  Atheros reference driver does.

* Correctly set the ANI parameters during ANI reset, rather than
  when ANI is enabled. In this way, if ANI is disabled or enabled
  whilst the NIC is not active (and there's no current channel),
  bogus parameters or a NULL pointer deference doesn't occur.

There's still some lingering issues - notably, the MIB events/interrupts
aren't fully disabled, so MIB interrupts still occur. I'll worry about
that later.

Approved by:	re (kib)
2011-07-30 13:30:24 +00:00
Adrian Chadd
f1ef788d6f Bring over AR5416 specific RX filter get/set routines.
This in particular fixes radar PHY handling - on the AR5212
NIC, one enables the AR_PHY_ERR_RADAR bit in AR_PHY_ERR;
the AR5416 and later also needs a bit set in AR_RX_FILTER.

A follow-up commit is needed to convert the AR5416 ANI code
to use this particular method, as it's currently using the
AR5212 methods directly.

Obtained from:	Atheros
Approved by:	re (kib)
2011-07-30 13:25:11 +00:00
Adrian Chadd
c86c3aa3d9 I noticed that the Merlin NICs I had (AR9220, AR9280) never completed
the ADC calibrations if the NIC is in 5ghz 11a or 5ghz HT/20 modes.
I've been told that the dual-ADC is only engaged in turbo/40mhz modes.

Since Sowl (AR9160) seems to return valid-looking calibration data
in 5ghz 20MHz modes, I'm only disabling it for Merlin for now.
It may turn out I can disable it for all chipsets and only enable
it for 40MHz modes.

Approved by:	re (kib)
2011-07-30 13:21:33 +00:00
Adrian Chadd
827660cf9a Fix the AR9280 initial AGC calibration code.
It looks like this was mixed up with the AR9285 calibration code.
This code is now more in line with what Linux ath9k and Atheros
reference drivers do.

Obtained from:	Atheros
Approved by:	re (kib)
2011-07-30 13:18:48 +00:00
Adrian Chadd
09ac182ca5 Modify the radar API a little to be easier to "change" via run-time
tools.

* introduce pe_enabled, which (will) indicate whether the radar
  detection stuff is enabled or not. Right now it's incorrectly
  set, based on something previously written. I'll sort it out
  later.

* Don't set HAL_PHYERR_PARAM_ENABLE in pe_relstep to say whether
  radar detection is on.

* Return whether blockradar, fir128 and enmaxrssi is enabled.

* Change some of the phyerr params to be integers rather than
  HAL_BOOL so they can be set to the NOPARAM value when the
  setup function is called. This is in line with other radar
  parameters.

* Add new configuration parameters for fir128, blockradar and
  enmaxrssi, rather than defaulting to off, on and on respectively.

Approved by:	re (kib)
2011-07-21 14:16:42 +00:00
Adrian Chadd
64d6d2d3fc Break out the PLL setup into (mostly) per-chip methods, rather than
polluting the AR5416 code with later chipset support.

Note: ar9280InitPLL() supports Merlin (AR9280) and later (AR9285, AR9287.)

Submitted by:	ssgriffonuser@gmail.com
Approved by:	re (kib)
2011-07-21 08:35:10 +00:00
Adrian Chadd
e8e6035991 This re-enables HT40 channels for use when DFS is enabled.
These should be disabled for the AR5416 in hostap/mesh/ibss mode,
as the AR5416 doesn't have support for radar detection on the
ext channel of a HT40 setup. Later chips do.

Approved by:	re (kib)
2011-07-21 08:31:55 +00:00
Adrian Chadd
e2e849485f These two are ath_hal regulatory domain updates from the Atheros
reference driver.

* Australia should use FCC3_WORLD
* Add some new SKUs; these are just the EEPROM values and haven't been
  fully defined yet. As such they won't affect anything.

Obtained from:	Atheros
Approved by:	re (kib)
2011-07-20 12:46:58 +00:00
Adrian Chadd
7d12b6e172 Make sure the extended regdomain word is initialised.
As with the AR9285, the AR9287 has a default word of 0x1F which means
all the various bits in that field are set on by default.
2011-06-28 00:01:55 +00:00
Adrian Chadd
8fc0556a5e Small fix to bring the non-debug definitions of HALDEBUG/HALDEBUG_G in line
with the debug definitions.
2011-06-24 23:59:14 +00:00
Adrian Chadd
dc6ebb1bca add missing #define for the non-debug case. 2011-06-23 12:11:43 +00:00
Adrian Chadd
f6f1dfb66b Re-introduce a global ath_hal_debug again for now, whilst I figure out what
to do about the few cases where the HAL state isn't available (regdomain)
or isn't yet setup (probe/attach.)

The global ath_hal_debug now affects all instances of the HAL.

This also restores the ability for probe/attach debugging to work; as
the sysctl tree may not be attached at that point. Users can just set
the global "hw.ath.hal.debug" to a suitable value to enable probe/attach
related debugging.
2011-06-23 06:55:29 +00:00
Adrian Chadd
4c728c42f5 Fix indenting issues introduced by the previous commit. 2011-06-23 06:53:13 +00:00
Adrian Chadd
37931a3544 Break out most of the HAL related tweaks into a per-HAL instance,
rather than global variables.

This specifically allows for debugging to be enabled per-NIC, rather
than globally.

Since the ath driver doesn't know about AH_DEBUG, and to keep the ABI
consistent regardless of whether AH_DEBUG is enabled or not, enable the
debug parameter always but only conditionally compile in the debug
methods if needed.

The ALQ support is currently still global pending some brainstorming.

Submitted by:	ssgriffonuser@gmail.com
Reviewed by:	adrian, bschmidt
2011-06-23 02:38:36 +00:00
Adrian Chadd
e484e92770 Since HAL_PHYERR_* is used in the radar code, always include ah_desc.h. 2011-06-07 14:00:47 +00:00
Adrian Chadd
3d423111f6 Flesh out a new HAL method to fetch the radar PHY error frame information.
For the AR5211/AR5212, this is apparently a one byte pulse duration
counter value. It is only coded up here for the AR5212 as I don't have
any AR5211-series hardware to test it on.

This information was extracted from the Madwifi DFS branch along with
some local additions.

Please note - all this does is extract out the radar event duration,
it in no way reflects the presence of a radar. Further code is needed
to take a set of radar events and filter them to extract out correct
radar pulse trains (and ignore other events.)

For further information, please see:

http://wiki.freebsd.org/dev/ath_hal%284%29/RadarDetection

This includes references to the relevant patents which describe what
is going on.

Obtained from:	Madwifi
2011-06-07 09:03:28 +00:00
Adrian Chadd
04d172db03 Bring over the relevant registers to use when implementing the quiet time
portion of 802.11h.

The AR5212 code has been brought over as a reference, it's currently
untested.

Obtained from:	Atheros
2011-06-03 07:27:53 +00:00
Adrian Chadd
2cb5233b43 Add some missing DFS chipset functionality to the FreeBSD HAL.
Please note - this doesn't in any way constitute a full DFS
implementation, it merely adds the relevant capability bits and
radar detection threshold register access.

The particulars:

* Add new capability bits outlining what the DFS capabilities
  are of the various chipsets.
* Add HAL methods to set and get the radar related register values.
* Add AR5212 and AR5416+ DFS radar related register value
  routines.
* Add a missing HAL phy error code that's related to radar event
  processing.
* Add HAL_PHYERR_PARAM, a data type that encapsulates the radar
  register values.

The AR5212 routines are just for completeness. The AR5416 routines
are a super-set of those; I may later on do a drive-by pass to
tidy up duplicate code.

Obtained from:	Linux, Atheros
2011-06-01 20:01:02 +00:00
Adrian Chadd
76355edba5 Teach if_ath about devices which have short-GI in 20MHz channel modes.
This has been disabled until now because there hasn't been any supported
device which has this feature. Since the AR9287 is the first device to
support it, and since now the HAL has functional AR9287+11n support,
flip this on.
2011-05-29 00:17:13 +00:00
Adrian Chadd
133cf74b7e Fix AR9287 operation when >1 TX chain is enabled.
I didn't pick this up with the initial commit because I was only testing
with 11bg.
2011-05-28 15:43:56 +00:00
Adrian Chadd
8d01245e7e Fix a macro name - it's currently unused in this file however, but
keep it consistent with ar9280.c.
2011-05-26 20:22:10 +00:00
Adrian Chadd
a3906079d2 Revert this erroneous commit and re-disable the AR9285 combined antenna
diversity.
2011-05-26 20:17:59 +00:00
Adrian Chadd
0c50156f91 Remove the three-chain scaled power check for the AR9287 - it isn't
needed.
2011-05-26 16:59:42 +00:00
Adrian Chadd
1ecf8ddf5a Make sure only two chains are calibrated for the AR9287. 2011-05-26 16:55:44 +00:00
Adrian Chadd
fe5237edef Add some open-loop TX power debugging for AR9287. 2011-05-26 16:52:37 +00:00
Adrian Chadd
f1285519e2 Bring over the AR5416 per-rate TX power code, modified to use the
AR9287 EEPROM layout.

The AR9287 only supports 2ghz, so I've removed the 5ghz code (but left
the 5ghz edge flags in there for now) and hard-coded the 2ghz-only
path.

Whilst I'm there, fix a typo (ar9285->ar9287.)

This meets basic TX throughput testing - iperf TX tests == 27-28mbit in 11g,
matching the rest of my 11g kit.
2011-05-26 15:55:27 +00:00
Adrian Chadd
ea18ed263e Flesh out ar9287SetTransmitPower() based on the AR9285 routine.
Hard-code the per-rate TX power at 5dBm for now so testing can be done.

This passes initial TX testing in 11g mode (but, obviously, at 5dBm.)
2011-05-26 15:01:37 +00:00
Adrian Chadd
4551052dbe Flesh out the TX power calibration for the AR9287.
I'm assuming for now that the AR9287 is only open-loop TX power control
(as mine is) so I've hard-coded the attach path to fail if the NIC is
not open-loop.

This greatly simplifies the TX calibration path and the amount of code
which needs to be ported over.

This still isn't complete - the rate calculation code still needs to be
ported and it all needs to be glued together.

Obtained from:	Linux ath9k
2011-05-26 14:29:05 +00:00
Adrian Chadd
90759dbed6 Add the AR9287 chip identification string. 2011-05-26 09:27:58 +00:00
Adrian Chadd
8143e16401 Fix a bad merge from a previous commit. 2011-05-26 09:22:59 +00:00
Adrian Chadd
0293774898 Merlin -> Kiwi 2011-05-26 09:16:09 +00:00
Adrian Chadd
d8daa2e3f6 Bring over my AR9287 work in progress.
It isn't linked into the build because it's missing the TX power
and PDADC programming code.

This code is mostly based on the ath9k codebase, compared against
the Atheros codebase as appropriate.

What's implemented:

* probe/attach
* EEPROM board value programming
* RX initial calibration
* radio channel programming
* general MAC / baseband setup
* async fifo setup
* open-loop tx power calibration

What's missing before it can be enabled by default:

* TX power / calibration setting code
* closed-loop tx power calibration routines
* TSF2 handling
* generic timer support from ath9k

Obtained from:	Atheros, ath9k
2011-05-26 09:15:33 +00:00
Adrian Chadd
b3096aee0b AR9287 prep work:
* Add PCI/PCIE devids
* Add AR9287/Kiwi version check macros
* AR_SREV_9287 -> AR_SREV_KIWI

Obtained from:	Atheros, ath9k
2011-05-26 08:35:47 +00:00
Adrian Chadd
a1cf3a877a Add temp sense to the EEPROM variable list;
Export the temperature sense variables to ah_eeprom_9287.c
2011-05-26 08:20:14 +00:00
Adrian Chadd
727edca45b The current ANI capability information uses a different set of
values for the commands, compared to the internal command values
(HAL_ANI_CMD.)

My eventual aim is to make the HAL_ANI_CMD internal enum match
the public API and then remove all this messiness.

This now allows HAL_CAP_INTMIT users to use a public HAL_CAP_INTMIT_
enum rather than magic constants.

The only magic constants currently used by if_ath are "enable" and
"present". Some local tools of mine allow for direct, manual fiddling
of the ANI variables and I'll convert these to use the public enum API
before I commit them.
2011-05-25 07:34:49 +00:00
Adrian Chadd
241d9a3400 Tidy up the ANI API in preparation for looking to expose some more
of the ANI statistics and committing some tools which use these.

* Change HAL_ANI_* commands _back_ to be numerical, rather than a
  bitmap;
* modify access to the ANI control bitmap to convert a command to
  a bitmap;
* Fix the ANI noise immunity fiddling for CCK errors - it wasn't
  checking whether noise immunity was disabled or not.
2011-05-25 07:19:19 +00:00
Adrian Chadd
9f4563363b The ANI control for the AR5416 and later chips was calling ar5212AniControl(),
which did AR5212 specific initialisation. This would cause some slight
silliness when enabling/disabling ANI.

Just to be completely correct - and to ensure the phy error mask/RX filter
register isn't incorrectly played with - make the ANI control function a
method, have it set appropriately for AR5212/AR5416, and call that from the
ANI control interface.
2011-05-24 18:25:40 +00:00
Adrian Chadd
634be0a971 Use the new per-series antenna and TPC definitions when setting ctl8->11.
This should hopefully make it clearer to developers what is going on
and when TPC is being hacked on, make it obvious why it isn't working for
series 1, 2, 3.

I won't flip on setting TX power for TX series 1, 2, 3 until I've done
some further testing with Kite to ensure it doesn't break anything.
(Before people ask - yes, TPC is only needed for 5ghz regdomains and
yes, Kite is a 2.4ghz only chip, but there are potential use cases
for 2ghz TPC. I just need to sit down and ensure it's supported and
functional.)
2011-05-24 05:49:02 +00:00
Adrian Chadd
e808ca4454 Add in descriptions for TX descriptor fields ctl8-11 - these fields
control the antenna control bits for the four TX series and the
TPC settings for TX series 1, 2, 3.

The specifics:

* The TPC setting for TX series 0 is handled in ctl0.

* TPC is currently disabled, so the per-packet TX power is
  set via the global per-rate TX power register, not per packet.

* The antenna control bits don't matter for AR5416 and later
  so they should stay 0 (which they currently do); they may
  be set for Kite but as there's no TX diversity supported
  at the moment (it requires the NIC to be built with an
  external antenna switch, matching how antenna diversity
  is done on legacy NICs), so again keep them 0.

This is in preparation for supporting per-rate TPC on the
AR5416 and later. The Kite (and soon to come Kiwi) code
sets ctl8-11 to 0x0, which doesn't have any effect at
the moment. When TPC is enabled it would result in the
second, third and fourth TX series attmpts to be done with
a TX power of 0. This commit doesn't change that; it'll
be followed up with some commits to properly set the TPC
registers appropriately.
2011-05-24 05:34:45 +00:00
Adrian Chadd
cd50bf427a The Merlin analog register bank is from 0x7800 -> 0x78fc; fix the code
to reflect this.
2011-05-21 09:23:18 +00:00
Adrian Chadd
db18c342da This isn't needed any longer, it's defined in ah_internal.h. 2011-05-18 11:28:23 +00:00
Adrian Chadd
fdc2e66c57 Fix case, introduced in my previous commit.
Pointy hat goes to:	adrian, for having multiple build screens
			open and checking the wrong one.
2011-05-17 15:03:39 +00:00
Adrian Chadd
655a610236 Use the halMcastKeySrchSupport capability bit to selectively enable/disable
the multicast key search support for AR5212, AR5416 and later.

The general HAL routine ath_hal_getcapability() implement checking this
but it's overridden by a check in ar5212_misc:ar5212GetCapability().
This restores the later functionality in case it's found to be broken
in any of the 11n chipsets.
2011-05-17 11:56:50 +00:00
Adrian Chadd
90de864a5e Set this HAL capabilities flag correctly even though it isn't currently
being used.
2011-05-17 11:52:53 +00:00
Adrian Chadd
0148401a3f Fix NF calibration breakage introduced by me in a past commit.
Since the returned NF will be -ve, checking for <= 0 is not good
enough. For now, check whether it equals 0 or -1; a future commit
will tidy this mess up and have it return HAL_BOOL instead.
2011-05-15 07:59:33 +00:00
Adrian Chadd
acc8122719 Fix the Merlin 5ghz fast-clock EEPROM fetch to return the correct value.
The eeprom Get method should return HAL_OK if fastclock is enabled in the
EEPROM. It was returning the opposite of what it should have.

Submitted by:	Matthew Fleming <mdf356@gmail.com>
2011-05-14 15:24:15 +00:00
Adrian Chadd
92ffeb633d Fix the eeprom set API method to return HAL_STATUS.
The code assumed it could return HAL_OK, HAL_EINVAL and other
HAL_STATUS types; so it shouldn't be declared as returning HAL_BOOL.

This commit was brought to you by the Clang compiler.

Submitted by:	Matthew Fleming <mdf356@gmail.com>
2011-05-14 15:12:02 +00:00
Adrian Chadd
047d6827d0 Import initial EEPROM code for Kite (AR9287).
I've tested this locally and it does indeed read and attach to an AR9287
EEPROM. But a lot more code needs to be ported over to the HAL before
the AR9287 is functional.

I'm importing this separate from the rest of the codebase (and unlinked from
the build for now) in case someone wishes to begin fiddling with porting
the rest of the code over from Linux ath9k.

Obtained from:	Linux ath9k
2011-05-14 14:25:15 +00:00
Adrian Chadd
d6415a7cf6 When disabling RIFS for Sowl (AR9160) and Howl (AR9130), make sure RIFS
is totally disabled.

The Atheros HAL code does this for Sowl/Howl but not for Owl (AR5416) where
RIFS is disabled by default.

This seems to quieten the occasional baseband hang I've been seeing with
the AR9160 in STA mode under constant heavy traffic load.

Obtained from:	Atheros
2011-05-14 05:43:33 +00:00
Adrian Chadd
b357d5767b Major fix: when doing open-loop TX power calibration, adjust
the correct CCK rates rather than adjusting the first handful.
This may have affected some AR9280 based NICs.

Minor fix: merlin check update
2011-05-14 04:17:16 +00:00
Adrian Chadd
98cdd90425 Fixes from the Atheros HAL - formatting; update Merlin checks to be consistent.
Nothing functional should change with this commit.
2011-05-14 04:05:23 +00:00
Adrian Chadd
307abf289d Even though initial calibrations aren't done (yet), add this so we're
consistent with the Atheros HAL.
2011-05-14 01:41:36 +00:00
Adrian Chadd
4342b6100b Only do open loop power control and temperature compensation
for the AR9280 based NICs if it's actually enabled.

Some of the OLC code was erroneously called during setup
and calibration. This may have caused some incorrect behaviour.
2011-05-13 14:33:45 +00:00
Adrian Chadd
2f399d37ee Remove duplicate code - add a function which calculates the ratesArray[]
table which contains the per-rate target TX power.

This code is shared between the v14 eeprom board setup (AR5416, AR9160,
AR9280) and will also be used by the upcoming Kite (AR9287) support.
2011-05-13 10:36:38 +00:00
Adrian Chadd
68b3f39d74 Some diversity changes relating to AR9285.
* grab the main, alt and selected LNA config
* add some optional / disabled logging code
* add a check to reject packets with an invalid main rssi too,
  in case the alt is the active receive chain and main is -ve.

Note: The software-controlled combined diversity code is still disabled.
2011-05-13 09:57:12 +00:00
Adrian Chadd
4b5404a9de Break out the AR9285 analog registers from ar5416/ar5416phy.h and put
them in a new header file, ar9002/ar9285_an.h.

Shuffle the AR9280 analog registers in ar5416/ar541phy.h into a contiguous
spot.
2011-05-12 10:11:24 +00:00
Adrian Chadd
003df2a90f Fix the half/quater rate PLL setup for AR5416, AR9160 and
(beta?) AR9280 chips.

Note: This doesn't "fix" half/quarter rate support for these
chips; it merely fixes an oversight.

Obtained from:	Atheros
2011-05-12 03:25:24 +00:00
Adrian Chadd
8a90965b83 Fixes from Atheros:
* If AR9130, give the chip extra time to reset
* If AR5416, don't shutdown the chip during reset
2011-05-12 03:15:21 +00:00
Adrian Chadd
6b00c928cb Make the NF calibration logic (hopefully!) more resistive to noisy
environments.

In setups where NF calibration can take a while, don't load the CCA
and kick off a new NF calibration if the previous one hasn't yet
completed. This shouldn't happen unless the environment is noisy but
those exist (hi phk!).

Here, if the previous NF hasn't completed when ar5416LoadNf() is run
(which reads the NF), it skips updating the history buffer, loading
the NF CCA array and kicking off the next NF cal. It's hoped it'll
occur in the next long calibration interval.

Obtained from:	Atheros, ath9k, my local HAL
2011-05-11 13:40:13 +00:00
Adrian Chadd
fd331bf9bb Always log if the NF CCA load fails; so users with debugging enabled
can see they're likely in a very noisy environment.
2011-05-11 13:25:43 +00:00
Adrian Chadd
7a8796d17d Make sure the chip is awake before writing to it to finally detach
it.

Obtained from:	Atheros
2011-05-11 13:24:17 +00:00
Adrian Chadd
46dde1e6fa Add a new flag - HAL_DEBUG_UNMASKABLE - which always logs a debug message
(when debug is enabled) no matter what.
2011-05-11 13:22:41 +00:00
Adrian Chadd
5645b9a093 Remove unused variable 2011-05-11 13:20:25 +00:00
Adrian Chadd
85191ae6e8 Remove the initial NF completion check.
This is taking quite a while for some people in some situations
(eg AR5418 in phk's Abusive Radio Environment).

Instead, the rest of the calibration related code should
ensure that a NF calibration has occured before reading NF
values and kicking off another NF calibration.

The channel should also likely be marked as "noisy" (CWINT)
if the NF calibration takes too long.
2011-05-11 11:02:20 +00:00
Adrian Chadd
37fb34b48b Remove a now unneeded comment.. 2011-05-11 10:30:31 +00:00
Adrian Chadd
c454afe290 Restore the RSSI threshold after writing the board values.
This would be overwritten by the board initvals written in ah->writeIni().
2011-05-11 09:47:48 +00:00
Adrian Chadd
12c5d1f2bf AR9285 (Kite) fixes.
* Correct some of the silicon revision checks to match what
  the Atheros HAL does. (See [1] below.)

* Move the PA cal and init cal method assignment to -after-
  the mac version/revision IDs are stored. The AR9285 init
  cal was never being called.

* Enable ANI.

Note Kite 1.0 and 1.1 were prototypes that shouldn't be seen
in the wild. Linux ath9k simply removed the prototype code from
their codebase. I'm going to leave it in there for now but
make it conditionally compilable in the future.

Obtained from:	Atheros
2011-05-10 04:32:27 +00:00
Adrian Chadd
352dbd822c Disable diversity combining support until I can get a firm answer
from Atheros as to what/when this is supposed to be enabled.

Using the default RX fast diversity settings seems to help quite
a bit.

Whilst I'm here, change the prototype to return HAL_BOOL rather than int.
2011-05-09 17:30:25 +00:00
Adrian Chadd
48d813ef34 Fix a regression I introduced - only swap analog chains if the RX chainmask
is 0x5.
2011-05-09 17:10:48 +00:00
Adrian Chadd
e8def8942a Disable TX STBC - it isn't used for now, but it isn't supported on Kite. 2011-05-09 16:49:40 +00:00
Adrian Chadd
60abf57fd5 Import some initial Kite fixed diversity code from Atheros.
For now, the diversity settings are controlled by 'txantenna',
-not- rxantenna. This is because the earlier chipsets had
controllable TX diversity; the RX antenna setting twiddles
the default antenna register. I'll try sort that stuff out at
some point.

Call the antenna switch function from the board setup function
so scans, channel changes, mode changes, etc don't set the
diversity back to a default state too far from what's intended.

Things to todo:

* Squirrel away the last antenna diversity/combining parameters
  and restore them during board setup if HAL_ANT_VARIABLE is
  defined. That way scans, etc don't reset the diversity settings.

* Add some more public facing statistics, rather than what's
  simply logged under HAL_DEBUG_DIVERSITY.

For now, the fixed antenna settings behave better than variable
settings for me. I have some further fiddling to do..

Obtained from:	Atheros
2011-05-09 15:19:49 +00:00
Adrian Chadd
b4d225808d Remove an un-needed PA cal call here. 2011-05-09 14:04:49 +00:00
Adrian Chadd
c9cd76313b Fix the 5ghz fast clock logic.
The macro which I incorrectly copied into ah_internal.h assumed
that it'd be called with an AR_SREV_MERLIN_20() check to ensure
it was only enabled for Merlin (AR9280) silicon revision 2.0 or
later.

Trouble is, the 5GHz fast clock EEPROM flag is only valid for
EEPROM revision 16 or greater; it's assumed to be enabled
by default for Merlin rev >= 2.0. This meant it'd be incorrectly
set for AR5416 and AR9160 in 5GHz mode.

This would have affected non-default clock timings such as SIFS,
ACK and slot time. The incorrect slot time was very likely wrong
for 5ghz mode.
2011-05-08 15:55:52 +00:00
Adrian Chadd
aa66982300 * Add AR_SREV_KITE macro for later use
* Modify AR_SREV_MERLIN_20() to match the Atheros/Linux ath9k behaviour -
  its supposed to match Merlin 2.0 and later Merlin chips.
  AR_SREV_MERLIN_20_OR_LATER() matches AR9280 2.0 and later chips
  (AR9285, AR9287, etc.)
2011-05-08 15:25:22 +00:00
Adrian Chadd
f678fb43eb These EEPROM bits actually defined whether HT/20 and HT/40 support
for the given channel is available.

It isn't used yet; ar5416GetWirelessModes() needs to be taught
about this rather than assuming HT20/HT40 is available.
2011-05-08 08:18:30 +00:00
Adrian Chadd
5c892e7497 Fiddle with the PLL initialisation order to match ath9k/Atheros HAL.
This seems to make the AR9160 behave better during heavy scanning,
where before it'd hang and require a hard reset to recover.

Obtained From:	Linux ath9k, Atheros
2011-05-08 07:21:09 +00:00
Adrian Chadd
351384c64f Properly indent the WAR code i pasted in from ath9k a few months
ago.
2011-05-08 05:45:06 +00:00
Adrian Chadd
60d3878423 * Add in a comment about ar5416InitUserSettings() potentially
modifying AR_DIAG_SW.

  There's a hardware workaround which sets disabling some errors
  early at startup and clears said bits before the PCU begins
  receiving - it does this to avoid RX descriptor status errors.

  It's possible these bits aren't being completely properly twiddled
  in all instances; but in particular if the diag_reg HAL variable
  is set it won't be setting these bits correctly. I'll review this
  at some point.

 * Disable multicast search on mac address and key id - the driver
   doesn't use it at the moment and thus adhoc may be broken for
   merlin and later.

* Change this to be for Merlin 1.0 (which from what I understand
  wasn't ever publicly released) to be more correct.
2011-05-08 05:25:42 +00:00
Adrian Chadd
5accb5fd53 Fiddle with the AR5416 1.0 chainmask setup.
Apparently all three RX chains need to be enabled before initial calibration
is done, even if only two are configured.

Reorder the alt chain swap bit to match what the Atheros HAL is doing.

Obtained From:	ath9k, Atheros
2011-05-08 03:24:17 +00:00
Adrian Chadd
af8223ba6d Fix the IS_5416 checks to actually work correctly.
I've verified that my AR5416 revision 2.2 (minor revision 0x0A) now
matches the correct checks.
2011-05-07 18:42:41 +00:00
Adrian Chadd
26e8415d1d Do a HAL capabilities sync pass based on the Atheros HAL.
* Shuffle some of the capability numbers around to match the
  Atheros HAL capability IDs, just for consistency.

* Add some new capabilities to FreeBSD from the Atheros
  HAL which will be be shortly used when new chipsets are added
  (HAL SGI-20 support is for Kiwi/AR9287 support); for
  TX aggregation (MBSSID aggregate support, WDS aggregation
  support); CST/GTT support for carrier sense/TX timeout.
2011-05-07 15:30:23 +00:00
Adrian Chadd
b657b11d8d Update the ext channel cycpwr threshold 1 register for the extension
channel when the channel is HT/40.

The new ANI code (primarily for the AR9300/AR9400) in ath9k sets this
register but the ANI code for the previous 11n chips didn't set this.

Unlike ath9k, only set this for HT/40 channels.

Obtained From:	ath9k
2011-05-07 13:08:48 +00:00
Adrian Chadd
f93ef5516b Read in the extended regulatory domain flags so future code can use them.
These describe FCC/Japan channel and DFS behaviour.

The AR9285 and later chips don't set these bits in the eeprom, the correct
behaviour is to just assume all five bits are enabled.
2011-05-07 11:05:16 +00:00
Adrian Chadd
001ac28926 Instead of returning an unknown mac/bb signature, just return 0. 2011-05-07 06:52:04 +00:00
Adrian Chadd
b810285f24 Add some comments about which HAL capabilities are currently FreeBSD
specific.

The Atheros HAL and FreeBSD HAL share the same capabilities up
until HAL_CAP_11D, where things begin to diverge.

I'll look at tidying these up soon.

Obtained from:	Atheros
2011-05-07 06:47:09 +00:00
Adrian Chadd
de1334e8d7 Some BB hang changes:
* Add Howl (ar9130) to the list of chips that have DFS/BB/MAC hangs
* Don't treat unknown BB hangs as fatal; ath9k/Atheros HAL don't
  treat it as such.
* Add HAL_DEBUG_DFS to the debug fields in ath_hal/ah_debug.h

The BB hang check simply loops over an observation register checking
for a stuck state engine, but it can happen under high traffic
conditions. Ath9k and the Atheros HAL simply log a debug message and
continue.

Private to FreeBSD:

* Add HAL_DEBUG_HANG to the debug fields
* Change the hang debugging to HAL_DEBUG_HANG rather than HAL_DEBUG_DFS
  like in the Atheros HAL.

Obtained from:	Atheros
2011-05-07 06:45:35 +00:00
Adrian Chadd
ef1901a3c9 Change AR_SREV_OWL_{X}_OR_LATER to AR_SREV_5416_{X}_OR_LATER.
For now, these are equivalent macros. AR_SREV_OWL{X}_OR_LATER
will later change to exclude Howl (AR9130) in line with what
the Atheros HAL does.

This should not functionally change anything.

Obtained from:	Atheros
2011-05-07 02:59:24 +00:00
Adrian Chadd
d1915e7308 Fix the OWL revision checks.
A quick story, which is partially documented in the commit.

The silicon revision in Linux ath9k and the Atheros HAL use an
AR_SREV_REVISION mask of 0x07.

FreeBSD's HAL uses the AR5212 AR_SREV_REVISION mask of 0x0F.

Thus the OWL silicon revisions were coming through as 0xA, 0xB,
0xC, rather than 0x0, 0x1 and 0x2.

My ath9k-sourced AR_SREV_OWL_<X> macros were thus using the wrong
silicon revision values and wouldn't correctly match.

This commit does a few things:

* Change the AR_SREV_OWL_<x> macros to use the AR_SREV_REVISION_OWL_*
  values, not AR_XSREV_REVISION_OWL macros;
* Disable AR_XSREV_REVISION_OWL_* values;
* Modify the IS_5416 to properly check the MAC is OWL, rather than
  potentially matching on non-OWL revisions (which shouldn't happen
  unless there's a silicon revision of higher than 0x9 in a later
  chip..)
* Add a couple more macros from the Atheros HAL for compatibility.

The main difference now is that the Atheros HAL defines
AR_SREV_OWL_{20,22}_OR_LATER subtly differently - it fails on all HOWL
silicon. The AR_SREV_5416_*_OR_LATER macros match on the relevant OWL
version -and- all HOWL versions, along with subsequent versions.

A subsequent commit is going to migrate the uses of AR_SREV_OWL_X_OR_LATER
to AR_SREV_5416_X_OR_LATER to match what's going on in the Atheros HAL.

There's only two uses of AR_SREV_OWL_X_OR_LATER which currently don't
apply to FreeBSD but it may do in the future.

Yes, it's all confusing!
2011-05-07 02:54:52 +00:00
Adrian Chadd
e7cb5d548d Add a function which enables or disables RX RIFS searching, and migrate
the code which does this into it.
2011-05-06 15:33:56 +00:00
Adrian Chadd
47ff47a858 Don't perform NF calibration for radio chains which aren't in use:
Quoting the ath9k commit message:

At present the noise floor calibration is processed in supported
control and extension chains rather than required chains.
Unnccesarily doing nfcal in all supported chains leads to
invalid nf readings on extn chains and these invalid values
got updated into history buffer. While loading those values
from history buffer is moving the chip to deaf state.

This issue was observed in AR9002/AR9003 chips while doing
associate/dissociate in HT40 mode and interface up/down
in iterative manner. After some iterations, the chip was moved
to deaf state. Somehow the pci devices are recovered by poll work
after chip reset. Raading the nf values in all supported extension chains
when the hw is not yet configured in HT40 mode results invalid values.

Reference:	https://patchwork.kernel.org/patch/753862/

Obtained from:	Linux ath9k
2011-05-05 08:11:22 +00:00
Adrian Chadd
ed8659ed69 Another Howl (AR9130) fix.
I haven't seen a 5ghz AR9130 based board yet though!

Obtained from:	Atheros
2011-05-05 04:43:05 +00:00
Adrian Chadd
d2615832bf Fix up the chipset checks for the AR5416 and later silicon.
The checks should function as follows:

* AR_SREV_<silicon> : check macVersion matches that version id
* AR_SREV_<silicon>_<revision> : check macVersion and macRevision match
    the version / revision respectively

* AR_SREV_<silicon>_<revision>_OR_LATER: check that
  + if the chip silicon version == macVersion, enforce revision >= macRevision
  + if the chip silicon version > macVersion, allow it.

For example, AR_SREV_MERLIN() only matches AR9280 (any revision),
AR_SREV_MERLIN_10() would only match AR9280 version 1.0, but
AR_SREV_MERLIN_20_OR_LATER() matches AR9280 version >= 2.0 _AND_
any subsequent MAC (So AR9285, AR9287, etc.)

The specific fixes which may impact users:

* if there is Merlin hardware > revision 2.0, it'll now be correctly
  matched by AR_SREV_MERLIN_20_OR_LATER() - the older code simply
  would match on either Merlin 2.0 or a subsequent MAC (AR9285, AR9287, etc.)

* Kite version 1.1/1.2 should now correctly match. As these macros
  are used in the AR9285 reset/attach path, and it's assumed that the
  hardware is kite anyway, the behaviour shouldn't change. It'll only
  change if these macros are used in other codepaths shared with
  older silicon.

Obtained from:	Linux ath9k, Atheros
2011-05-05 03:42:04 +00:00
Adrian Chadd
59298273a9 Import some HOWL (AR9130) related fixes from Atheros.
Obtained from:	Atheros
2011-05-05 02:59:31 +00:00
Adrian Chadd
5a04ce2fdf Remove this useless bit of code for Kite. The RIFS register value is overriden
by the initvals, so disabling RIFS before calling writeIni() effectively does
nothing.
2011-05-04 09:26:33 +00:00
Adrian Chadd
1422779793 Remove some holdovers from the AR5212 origin of this code.
These aren't relevant here.
2011-04-29 12:52:18 +00:00
Adrian Chadd
9f25ad52ce Introduce AR9130 (HOWL) WMAC support to the FreeBSD HAL.
The AR9130 is an AR9160/AR5416 family WMAC which is glued directly
to the AR913x SoC peripheral bus (APB) rather than via a PCI/PCIe
bridge.

The specifics:

* A new build option is required to use the AR9130 - AH_SUPPORT_AR9130.
  This is needed due to the different location the RTC registers live
  with this chip; hopefully this will be undone in the future.
  This does currently mean that enabling this option will break non-AR9130
  builds, so don't enable it unless you're specifically building an image
  for the AR913x SoC.

* Add the new probe, attach, EEPROM and PLL methods specific to Howl.

* Add a work-around to ah_eeprom_v14.c which disables some of the checks
  for endian-ness and magic in the EEPROM image if an eepromdata block
  is provided. This'll be fixed at a later stage by porting the ath9k
  probe code and making sure it doesn't break in other setups (which
  my previous attempt at this did.)

* Sprinkle Howl modifications throughput the interrupt path - it doesn't
  implement the SYNC interrupt registers, so ignore those.

* Sprinkle Howl chip powerup/down throughout the reset path; the RTC methods
  were

* Sprinkle some other Howl workarounds in the reset path.

* Hard-code an alternative setup for the AR_CFG register for Howl, that
  sets up things suitable for Big-Endian MIPS (which is the only platform
  this chip is glued to.)

This has been tested on the AR913x based TP-Link WR-1043nd mode, in
legacy, HT/20 and HT/40 modes.

Caveats:

* 2ghz has only been tested. I've not seen any 5ghz radios glued to this
  chipset so I can't test it.

* AR5416_INTERRUPT_MITIGATION is not supported on the AR9130. At least,
  it isn't implemented in ath9k. Please don't enable this.

* This hasn't been tested in MBSS mode or in RX/TX block-aggregation mode.
2011-04-28 12:47:40 +00:00
Adrian Chadd
041df70857 Wrap the MIMO stuff in #ifdef AH_SUPPORT_AR5416, as the channel
state doesn't have MIMO stuff in it by default.
2011-04-25 15:51:49 +00:00
Adrian Chadd
c2442d279a Break out the PLL setup into an overridable method.
The only method right now is ar5416InitPLL() which handles multiple
chipsets; this can now be overridden by newer chipset HAL code.
2011-04-24 15:53:57 +00:00
Adrian Chadd
98ebd982c3 Use the refactored ar5416WriteTxPowerRateRegisters() call in the ar9285 code. 2011-04-24 15:48:07 +00:00
Adrian Chadd
b998ae6409 Eliminate code duplication between AR5416/AR9160/AR9280 and AR9285.
Writing the TX power registers is the same between all of these chips
and later NICs (AR9287, AR9271 USB, etc.) so this will reduce code
duplication when those NICs are added to the HAL.
2011-04-24 14:50:29 +00:00
Adrian Chadd
6f5fe81e02 Fix a corner-case of interrupt handling which resulted in potentially
spurious (and fatal) interrupt errors.

One user reported seeing this:

Apr 22 18:04:24 ceres kernel: ar5416GetPendingInterrupts: fatal error,
  ISR_RAC 0x0 SYNC_CAUSE 0x2000

SYNC_CAUSE of 0x2000 is AR_INTR_SYNC_LOCAL_TIMEOUT which is a bus timeout;
this shouldn't cause HAL_INT_FATAL to be set.

After checking out ath9k, ath9k_ar9002_hw_get_isr() clears (*masked)
before continuing, regardless of whether any bits in the ISR registers
are set. So if AR_INTR_SYNC_CAUSE is set to something that isn't
treated as fatal, and AR_ISR isn't read or is read and is 0, then
(*masked) wouldn't be cleared. Thus any of the existing bits set
that were passed in would be preserved in the output.

The caller in if_ath - ath_intr() - wasn't setting the masked value
to 0 before calling ath_hal_getisr(), so anything that was present
in that uninitialised variable would be preserved in the case above
of AR_ISR=0, AR_INTR_SYNC_CAUSE != 0; and if the HAL_INT_FATAL bit
was set, a fatal condition would be interpreted and the chip was
reset.

This patch does the following:

* ath_intr() - set masked to 0 before calling ath_hal_getisr();
* ar5416GetPendingInterrupts() - clear (*masked) before processing
  continues; so if the interrupt source is AR_INTR_SYNC_CAUSE
  and it isn't fatal, the hardware isn't reset via returning
  HAL_INT_FATAL.

This doesn't fix any underlying errors which trigger
AR_INTR_SYNC_LOCAL_TIMEOUT - which is a bus timeout of some
sort - so that likely should be further investigated.
2011-04-23 06:37:09 +00:00
Adrian Chadd
0d07bcba27 Fix the merlin LNA configuration code - these are bit flags, not raw values to be
written into the registers.
2011-04-22 17:57:13 +00:00
Adrian Chadd
635636ea69 The second regdomain word is a set of bitflags describing
regulatory domain behaviour. Document what the v14 EEPROM
flags are.
2011-04-22 10:59:20 +00:00
Adrian Chadd
0d2dd30cbd Bring over a pdadc calibration fix from ath9k - unused power detector
gain values should be 58, not the previous values.

Obtained From:	linux ath9k
2011-04-22 10:57:46 +00:00
Adrian Chadd
d0a0ebc6c3 Rework the Global TX timeout handling to look more like ath9k.
It correctly now sets the AR_IMR BCNMISC register, along with
the GTT register in AR_IMR_S2.
2011-04-18 14:03:05 +00:00
Adrian Chadd
6ad02dbafe Add global TX timeout handling.
The global TX timeout counter increments whenever a frame is ready
to be transmitted and the medium is busy.
2011-04-18 12:15:43 +00:00
Adrian Chadd
d10f1cdc8c Mark the PHY as inactive before the chip is reset.
It's also marked inactive by the initvals, and enabled after
the baseband/PLL has been configured, but before the RF
registers have been programmed.

The origin and reason for this particular change is currently unknown.

Obtained from:	Linux ath9k
2011-04-17 13:46:13 +00:00
Adrian Chadd
b39c47d922 Don't do Kite antenna switch selection this way (for now); antenna
diversity is done elsewhere now.
2011-04-16 13:47:17 +00:00
Adrian Chadd
52d84465a2 Disable classic-style fast diversity on the AR5416 and later.
Antenna diversity on the >= AR5416 is implemented differently than the
AR5212 and previous chips. So for now, and not to confuse things, just
disable it for now.
2011-04-16 12:46:46 +00:00
Adrian Chadd
18a3a3309f Remove some duplicate code from the AR9285 TX power configuration path. 2011-04-16 11:59:37 +00:00
Adrian Chadd
81484cdb07 Add in the last bit of the HAL support for Kite diversity.
* add a new method, specifically for doing per-RX packet
  antenna diversity
* set that HAL method only if it's Kite and a Kite chip that
  does diversity.
2011-04-13 15:12:48 +00:00
Adrian Chadd
1171c869d7 More kite diversity related changes.
* add a diversity flag to the HAL debugging section
* add a check to make sure the kite diversity code doesn't run
  on boards that don't require it, as not all Kite chips will
  implement it.
* add some debug statements when the diversity code makes
  changes to the antenna diversity/combining setup.
2011-04-13 15:08:51 +00:00
Adrian Chadd
ac27b8ff27 Change this to be less noisy. 2011-04-13 14:51:07 +00:00
Adrian Chadd
77823fbc2c Bring over the antenna diversity logic support for Kite.
Again, this is just the code ported from ath9k and included in the build,
it isn't yet enabled.
2011-04-13 11:32:15 +00:00
Adrian Chadd
c772d0204f Port over a TX gain fix from ath9k specific to the AR9285 (Kite) and AR9271.
Note: this HAL currently only supports the AR9285.

From Linux ath9k:

The problem is that when the attenuation is increased,
the rate will start to drop from MCS7 -> MCS6, and finally
will see MCS1 -> CCK_11Mbps. When the rate is changed b/w
CCK and OFDM, it will use register desired_scale to calculate
how much tx gain need to change.

The output power with the same tx gain for CCK and OFDM modulated
signals are different. This difference is constant for AR9280
but not AR9285/AR9271. It has different PA architecture
a constant. So it should be calibrated against this PA
characteristic.

The driver has to read the calibrated values from EEPROM and set
the tx power registers accordingly.
2011-04-13 04:40:59 +00:00
Adrian Chadd
6984989598 Add new fields to the v4k EEPROM modal header. 2011-04-13 03:05:42 +00:00
Adrian Chadd
132163b12f Add OS_REG_RMW, which mirrors ath9k's REG_RMW.
This macro does a read-modify-write pass with register bits to set and clear.
2011-04-13 03:05:15 +00:00
Adrian Chadd
1c554472de Add the initial AR9285 PHY glue for supporting antenna diversity.
This code isn't currently used anywhere; it's just linked into the build.
2011-04-13 02:40:45 +00:00
Adrian Chadd
a03467b1ba De-dup the ar5416 rates array definition. 2011-04-11 11:15:34 +00:00
Adrian Chadd
7ab2ab919c Fix the completely wrong types I used in the previous commit. 2011-04-08 08:49:50 +00:00
Adrian Chadd
82c30dc46e Begin fleshing out a public HAL routine to export the per-chain
ctl/ext noise floor values.

This routine doesn't check to see whether the radio is MIMO
capable - instead, it simply returns either the raw values,
the "nominal" values if the raw values aren't yet available
or are invalid, or '0' values if there's no valid channel/
no valid MIMO values.

Callers are expected to verify the radio is a MIMO radio
(which for now means it's an 11n chipset, there are non-11n
MIMO chipsets out there but I don't think we support them,
at least in MIMO mode) before exporting the MIMO values.
2011-04-08 07:44:00 +00:00
Adrian Chadd
f1ff114882 Export the per-chain ctl/ext noise floor values, raw and uncut, to the
upper-level HAL.

Right now the per-chain noise floor values aren't used anywhere in
the upper-level HAL, so the driver currently has no real reference
to compare the per-chain RSSI values to.

This is needed before per-chain RSSI values (for ctl and ext radios)
are can be thrown upstairs to the net80211 code.
2011-04-08 06:58:01 +00:00
Adrian Chadd
8cc7d3572f Extend the RX descriptor block to include two more EVM words.
This will be needed for later AR93xx/AR94xx 3-stream devices.
2011-04-08 06:29:41 +00:00
Adrian Chadd
5e7d0e6482 Add some more OS_MARK probes to the RX DMA setup/teardown code path.
I'm trying to debug the RX DMA path and help the ath9k guys with
"RX dma abort stuck" issue that both our drivers have.
2011-04-07 13:14:51 +00:00
Adrian Chadd
74e3a02137 The xpaBiasLvlFreq[] fields in the modal header also need swapping
when the EEPROM contents are byte-swapped.
2011-04-05 13:14:17 +00:00
Adrian Chadd
9e9ae8e207 Commit missing bits from the last commit:
* add the hal capability flag
* make sure its disabled for the ar9280/ar9285.
2011-04-04 14:53:36 +00:00
Adrian Chadd
8a2a6beedb Add a HAL capability bit for supporting self-linked RX descriptors and disable it for the 11n chipsets.
From the ath9k source:

==

11N: we can no longer afford to self link the last descriptor.
MAC acknowledges BA status as long as it copies frames to host
buffer (or rx fifo). This can incorrectly acknowledge packets
to a sender if last desc is self-linked.

==

Since this is useful for pre-AR5416 chips that communicate PHY errors
via error frames rather than by on-chip counters, leave the support
in there, but disable it for AR5416 and later.
2011-04-04 14:52:31 +00:00
Adrian Chadd
efa7c2b36c At least set the coverage class value here; worry about populating the
register values at a later date.
2011-04-04 11:01:53 +00:00
Adrian Chadd
f90a170c46 I missed committing this last time - it's needed for the 5ghz fast clock calculation. 2011-04-03 20:15:41 +00:00
Adrian Chadd
97efbf40fc Add in the clock timing calculation when Merlin is using the 5ghz fast clock.
This is a 44mhz clock, not a 40mhz clock like normal for 5ghz operation.
2011-04-03 17:36:32 +00:00
Adrian Chadd
c55968698f Import a fix from the ath9k - reduce the TX FIFO size for Kite (AR9285.) 2011-04-03 12:02:49 +00:00
Adrian Chadd
3d45fa543f Add an explanation of the inivals 2011-04-03 11:59:52 +00:00
Adrian Chadd
634a6d0283 From ath9k - clear the RX descriptor status before recycling it. 2011-04-02 00:27:22 +00:00
Adrian Chadd
5d51c507d0 Add some more debugging 2011-04-02 00:24:13 +00:00
Adrian Chadd
b569f9f5df Introduce AH_AR5416_INTERRUPT_MITIGATION which enables interrupt mitigation for
the AR5416 and later. Rename the older HAL option to use this.
2011-03-31 08:48:05 +00:00
Adrian Chadd
bb16aa8120 .. And another missed commit - add the PSPOLL capability. 2011-03-26 13:06:43 +00:00
Adrian Chadd
d2211b6a68 This was missing from the previous HAL commit - it fixes a typo and
introduces the PS-POLL hardware support.
2011-03-26 11:59:18 +00:00
Adrian Chadd
a0e1036046 Introduce hardware PS-POLL support in the HAL.
Linux ath9k only enables this for AR9280 and later NICs; so
create a capability for it so it isn't enabled for earlier
NICs.

Enabling hardware PS-POLL support will come in a later commit
and will be disabled by default.
2011-03-26 10:47:17 +00:00
Adrian Chadd
f95233b6f5 Put these two back to mirror what ath9k does.
Even though they map to setting the error filter register,
ath9k also writes them untouched to AR_RX_FILTER.

The Force-BSSID match bit can stay high, as it maps to a
misc mode register setting rather than an RX filter bit.
2011-03-26 07:29:48 +00:00
Adrian Chadd
8c98d9bae1 Shuffle around the HAL_RX_FILTER bits to be slightly more sensible.
The phyerr, radar and bssid-match bits aren't real bits, they map
to enabling bits in other registers. Move those out of the way of
valid RX filter bits.

Add a few new fields from ath9k - compba, ps-poll, mcast-bcast-all.
2011-03-26 07:15:35 +00:00
Adrian Chadd
75f0fbfbbf I broke periodic adc calibrations - so restore them to working order. 2011-03-25 10:53:13 +00:00
Adrian Chadd
7dd51df82f After discussion with Felix Fietkau (nbd) about the ath9k Merlin LNA bit
settings, it seems that our defines are backwards and don't match what
is in the EEPROM documentation or internal driver.

The ath9k code used to have a bitfield here, rather than a uint8_t, and
there were #defines used to swap the order based on the endian of the
platform - this wasn't because of nybble or bit ordering of the
underlying host but because of what the compiler was doing.

This may be the reason for the backwards field numbers, as ath9k had
similar issues.
2011-03-25 00:45:24 +00:00
Adrian Chadd
423c974c28 Flip ANI on for the AR5416 and later chips. I haven't verified it on
the AR9285 so I'll leave it off for that.

Ath9k sources indiciate that one of the ANI modes interferes with
RIFS detection, so match ath9k and disable that.
2011-03-25 00:40:08 +00:00
Adrian Chadd
24cfde2fc3 The right commit - add a couple more AR_PCU_MISC_MODE2 register bits -
SOWL specific.
2011-03-25 00:06:58 +00:00
Adrian Chadd
30fa312b45 oops, commited the wrong file change. 2011-03-25 00:06:19 +00:00
Adrian Chadd
c2a1d035e6 Add some more AR_PCU_MISC_MODE2 register settings - these are SOWL or later. 2011-03-25 00:05:26 +00:00
Adrian Chadd
6893df4146 Bring over interrupt mitigation changes from ath9k.
* The existing interrupt mitigation code didn't mitigate anything - the
  per-packet TX/RX interrupts are still occuring. It's possible this
  worked for the AR5416 but not any later chipsets; I'll investigate and
  update as needed.

* Set both the RX and TX threshold registers whilst I'm at it.

This is verified to work on the AR9220 and AR9160. I'm leaving it off
by default in case it's truely broken, but I need to have it enabled
when doing 11n testing or interrupt loads exceed 10,000 interrupts/sec.
2011-03-25 00:03:21 +00:00
Adrian Chadd
ef58d1e0b8 Make the ar2133ForceBias() call controllable at runtime.
At least one AR5416 user has reported measurable throughput drops
with this option. For now, disable it and make it a run-time
twiddle. It won't take affect until the next radio programming
trip though (eg channel scan, channel change.)
2011-03-23 23:48:44 +00:00
Adrian Chadd
d4c081e362 The AR5416+ chips all have MIB counters (which the AR5416 ANI code assumes)
so there's no need to enable the RX of invalid frames just to do ANI.

The if_ath code and AR5212 ANI code setup the RX filter bits to enable
receiving OFDM/CCK errors if the device doesn't have the hardware
MIB counters. It isn't initialising it for the AR5416+ because all of
those chips have hardware MIB counters.

This fixes the odd (and performance affecting!) situation where if ani
is enabled (via sysctl dev.ath.X.intmit) then suddenly there's be a very
large volume of phy errors - which is good to track, but not what was
intended. Since each PHY error is a received (0 length) frame, it can
significantly tie up the RX side of things.
2011-03-23 03:58:55 +00:00
Adrian Chadd
f6f59583bf Bring over an XPA (external power amplifer) bias fix for the AR9160.
This fix modifies the const addac initval array, rather than modifying
a local copy. It means that running >1 AR9160 on a board may prove to
be unpredictable.

The AR5416 init path also does something similar, so supporting
>1 AR5416 of different revisions could cause problems.

The later fix will be to create a private copy of the Addac data
for the AR5416, AR9160 (and AR9100 when it's merged in) and then
modify that as needed.

Obtained From:	Linux ath9k
2011-03-22 10:29:36 +00:00
Adrian Chadd
507de8028f Fix OFDM ANI statistics gathering for the AR5416 and later chips.
I found this when trying to figure out why the RX PHY error count
didn't match the OFDM error count ANI was using. It turns out
there was two problems:

* What this commit addresses - using the wrong mask for OFDM errors,
  and
* The RX filter is set incorrectly after a channel scan (at least)
  even if interference mitigation is enabled by default.

ANI is still disabled by default for the AR5416 and later chips.
2011-03-22 07:19:49 +00:00
Adrian Chadd
fdb9c24c19 Set the "right" CCA register.
Obtained From:	ath9k
2011-03-22 05:47:48 +00:00
Adrian Chadd
6359b5731c Break out the RF mode setup into ar5416SetRfMode(), mirroring what ath9k does. 2011-03-22 00:52:44 +00:00
Adrian Chadd
b335ecffa2 Do a bit of spring cleaning in the board setup code, just to
bring it in line with the rest of the register initialisation.

I've verified that the 2/5ghz board values written to the
chip match what was previously written.
2011-03-22 00:43:58 +00:00
Adrian Chadd
dca968a2ce Bring over a few queue changes from ath9k:
* add pspoll/uapsd queue setup defaults;
* enable the exponential backoff window rather than the random
  backoff window when doing TX contention management.
2011-03-22 00:14:17 +00:00
Adrian Chadd
299bb4987b Even though it's very unlikely the misc mode register setting at -attach-
would be a problem, make sure it isn't overwritten by whatever is in
there at cold reset.

This brings the > ar5416 init path treatment of AR_MISC_MODE.
2011-03-22 00:12:26 +00:00
Adrian Chadd
fecc2a5eea Remove the merlin delay workaround here, it isn't appropriate for
the analog bank writes as Merlin never does them.
2011-03-22 00:11:04 +00:00
Adrian Chadd
1f0caefd53 Back that commit out - something's broken, and I need to figure out
what/why.
2011-03-21 17:44:52 +00:00
Adrian Chadd
020f937363 This CLKDRV workaround should only be for AR5416 v2.0/2.1;
the check was too strict and enabled it for all non AR5416-v2.2
chipsets - including later ones.
2011-03-21 17:12:03 +00:00