Commit Graph

18642 Commits

Author SHA1 Message Date
Ivan Malov
61b3e9e79a common/sfc_efx/base: report maximum Rx data count
Such information is useful to client drivers which deal with
large Rx pool buffers (16-bit wide data count) and thus need
to avoid overflow when setting EF10's 14-bit wide data count.

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2022-09-28 11:51:39 +02:00
Ivan Malov
79b0c19261 common/sfc_efx/base: fix maximum Tx data count
Maximum data count of a Tx descriptor is advertised to users,
however, this value is mistakenly derived from the Rx define.
Use the Tx one instead. The resulting value will be the same.

Fixes: 1e43fe3cb4 ("net/sfc/base: separate limitations on Tx DMA descriptors")
Cc: stable@dpdk.org

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2022-09-28 11:51:39 +02:00
Bhagyada Modali
91907ec247 net/axgbe: save segment data in scattered Rx
Saving the current segments of the packet, when the next segment data is
not ready.

Fixes: 965b3127d4 ("net/axgbe: support scattered Rx")
Cc: stable@dpdk.org

Signed-off-by: Bhagyada Modali <bhagyada.modali@amd.com>
Acked-by: Chandubabu Namburu <chandu@amd.com>
2022-09-21 16:39:08 +02:00
Bhagyada Modali
30ff4d00d9 net/axgbe: clear buffer on scattered Rx chaining failure
Clearing mbuf, first_seg when chaining mbufs fail.
Increment the error count for the same.

Fixes: 965b3127d4 ("net/axgbe: support scattered Rx")
Cc: stable@dpdk.org

Signed-off-by: Bhagyada Modali <bhagyada.modali@amd.com>
Acked-by: Chandubabu Namburu <chandu@amd.com>
2022-09-21 16:39:08 +02:00
Bhagyada Modali
2a761aec22 net/axgbe: reset end of packet in scattered Rx
Reset the EOP in the failure scenario and also after the last segment.
Remove updating the packet length explicitly as it is done in chaining.

Fixes: 965b3127d4 ("net/axgbe: support scattered Rx")
Cc: stable@dpdk.org

Signed-off-by: Bhagyada Modali <bhagyada.modali@amd.com>
Acked-by: Chandubabu Namburu <chandu@amd.com>
2022-09-21 16:39:08 +02:00
Kiran Kumar K
e5d0e3c759 common/cnxk: update base rule merging mechanism
Added changes to base rule install mechanism.
If action type is IPsec and multi channel is set,
then base rule will not be merged.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Reviewed-by: Satheesh Paul <psatheesh@marvell.com>
2022-09-30 09:10:39 +02:00
Hanumanth Pothula
8a96c7f8a5 net/cnxk: fix DF bit in vector mode
In vector mode, DF bit is not programmed correctly, as the
return value of vsetq_lane_u64() is ignored, which actually
contains the updated value, leading HW to free mbufs though
NIX_TX_OFFLOAD_MBUF_NOFF_F flag is set.

Hence, save return value of vsetq_lane_u64() appropriately so
that DF bit is programmed correctly.

Fixes: 862e281287 ("net/cnxk: add vector Tx for CN9K")
Fixes: f71b7dbbf0 ("net/cnxk: add vector Tx for CN10K")
Cc: stable@dpdk.org

Signed-off-by: Hanumanth Pothula <hpothula@marvell.com>
2022-09-30 09:09:23 +02:00
Hanumanth Pothula
5a0f64d84b net/cnxk: fix configuring large Rx/Tx queues
While configuring NIX, local variables 'nb_rxq' and 'nb_txq'
are declared as 8bit variables, leading to an integer overflow
when an application sends Rxq/Txq value greater than 255.

Hence, declare local variables, 'nb_rxq' and 'nb_txq' as 16bit
variable. Also, during the cleanup, make sure PFC tree is not created.

Fixes: b75e0aca84 ("net/cnxk: add device configuration operation")
Cc: stable@dpdk.org

Signed-off-by: Hanumanth Pothula <hpothula@marvell.com>
2022-09-30 09:09:18 +02:00
Kevin Liu
ccf33dccf7 net/ice: check illegal packet sizes
If the length of data_len in mbuf is less than 17 or
greater than the maximum frame size, it is illegal.

These illegal packets will lead to Tx/Rx hang and
can't recover automatically.

This patch check those illegal packets and protect
Tx/Rx from hanging.

Fixes: 17c7d0f9d6 ("net/ice: support basic Rx/Tx")
Cc: stable@dpdk.org

Signed-off-by: Kevin Liu <kevinx.liu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-30 10:28:29 +02:00
Kevin Liu
19ee91c6bd net/iavf: check illegal packet sizes
If the length of data_len in mbuf is less than 17 or
greater than the maximum frame size, it is illegal.

These illegal packets will lead to Tx/Rx hang and
can't recover automatically.

This patch check those illegal packets and protect
Tx/Rx from hanging.

Fixes: a2b29a7733 ("net/avf: enable basic Rx Tx")
Cc: stable@dpdk.org

Signed-off-by: Kevin Liu <kevinx.liu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-30 10:26:32 +02:00
Shun Hao
9b7fcf395c net/mlx5: fix meter profile delete after disable
If a meter's profile is changed after meter disabled, there's an issue
that will fail when deleting the old profile.

This patch fixes this by adding the correct process to decrease the old
profile's reference count when changing profile.

Fixes: 63ffeb2ff2 ("net/mlx5: support meter profile update")
Cc: stable@dpdk.org

Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-10-02 09:13:55 +02:00
Shun Hao
530dc58073 net/mlx5: fix meter ID tag for meter hierarchy
Currently, when flow usese meter hierarchy, a tag action is always applied
to set the first meter's meter id, so as to update the first meter's drop
count. But it's not considered if first meter doesn't have drop count.

This patch fixes it, that in hierarchy, if the first meter doesn't have
drop count, no need to add the meter id tag action. No change for
non-hierarchy meter.

Fixes: e8146c63 ("net/mlx5: support represented port item in flow rules")
Cc: stable@dpdk.org

Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-10-02 09:13:54 +02:00
Shun Hao
ca7e6051e7 net/mlx5: limit meter flow when matching all ports
If there's no param in represented_port item, it will be treated as
matching all ports by default. But there's some limitation when using it
with meter hierarchy.

This patch adds the limitation that when matching all ports, the meter
hierarchy should not contain any meter having drop count.

Fixes: e8146c63 ("net/mlx5: support represented port item in flow rules")
Cc: stable@dpdk.org

Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-10-02 09:13:54 +02:00
Shun Hao
33d506b9e5 net/mlx5: fix meter hierarchy with represented port item
There is a new item type represented_port, and currently it will fail
when using meter hierarchy in flow using represented_port match.

This patch fixes this fail by adding support for represented_port item
in meter hierarchy flow split.

Fixes: e8146c63 ("net/mlx5: support represented port item in flow rules")
Cc: stable@dpdk.org

Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-10-02 09:13:54 +02:00
Jiawei Wang
9f71a297da net/mlx5: fix modify action with tunnel decapsulation
The driver splits the flow with sample action into two sub-flows,
sub prefix flow and sub suffix flow.

In the case of tunnel flow including a decap action, the driver should
translate the inner as outer for actions coming after the decap action.
In the case of flow splitting, the packet layers, used to detect the
attributes, are inherited from the prefix flow to the suffix flow but
the driver wrongly didn't handle the decap adjustment and the inner
layers didn't shift to the outer.

This patch adjusts the inherited layers in case of decap.

Fixes: 6e77151286 ("net/mlx5: fix match information in meter")
Cc: stable@dpdk.org

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-10-02 09:13:53 +02:00
Raja Zidane
130bb7da53 net/mlx5: fix Tx check for hardware descriptor length
If hardware descriptor (WQE) length exceeds one the HW can handle,
the Tx queue failure occurs. PMD does the length check but there was
a bug - the length limit was expressed in 16B units (WQEBB segments),
while the calculated WQE length and limit were in 64B units (WQEBBs).
Fix the condition to avoid subsequent Tx queue failure.

Fixes: 18a1c20 ("net/mlx5: implement Tx burst template")
Cc: stable@dpdk.org

Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-10-02 09:13:53 +02:00
Viacheslav Ovsiienko
d15bfd2930 net/mlx5: fix inline length exceeding descriptor limit
The hardware descriptor (WQE) length field is 6 bits wide
and we have the native limitation for the overall descriptor
length. To improve the PCIe bandwidth the packet data can be
inline into descriptor. If PMD was configured to inline large
amount of data it happened there was no enough space remaining
in the descriptor to specify all the packet data segments and
PMD rejected problematic packets.

The patch tries to adjust the inline data length conservatively
and allows to avoid error occurring.

Fixes: 18a1c20044 ("net/mlx5: implement Tx burst template")
Fixes: e2259f93ef ("net/mlx5: fix Tx when inlining is impossible")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Reviewed-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
2022-10-02 09:13:52 +02:00
Viacheslav Ovsiienko
166f185fef net/mlx5: fix single not inline packet storing
The mlx5 PMD can inline packet data into transmitting descriptor (WQE)
and free mbuf immediately as data no longer needed, for non-inline
packets the mbuf pointer should be stored in elts array for coming
freeing on send completion. There was an optimization on storing
pointers in batch and there was missed storing mbuf for single
packet if non-inline was explicitly requested by flag.

Fixes: cacb44a099 ("net/mlx5: add no-inline Tx flag")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-10-02 09:13:52 +02:00
Viacheslav Ovsiienko
37d6fc30c1 net/mlx5: fix check for orphan wait descriptor
The mlx5 PMD supports send scheduling feature, it allows
to send packets at specified moment of time, to do that
PMD pushes special wait descriptor (WQE) to the hardware
queue and then pushes descriptor for packet data as usual.
If queue is close to be full or there is no enough elts
buffers to store mbufs being sent the data descriptors might
be not pushed and the orphan wait WQE (not followed by the
data) might reside in queue on tx_burst routine exit.

To avoid orphan wait WQEs there was the check for enough
free space in the queue WQE buffer and enough amount of the
free elts in queue mbuf storage. This check was incomplete
and did not cover all the cases for Enhanced Multi-Packet
Write descriptors.

Fixes: 2f827f5ea6 ("net/mlx5: support scheduling on send routine template")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-10-02 09:13:52 +02:00
Bassam Zaid AlKilani
6fa815722e net/mlx5: fix flow matching priority for ESP item
ESP is one of IPSec protocols over both IPv4 and IPv6 and is considered
a tunnel layer that cannot be followed by any other layer. Taking that
into consideration, ESP is considered as a 4 layer.

Not defining ESP's priority will make it match with the same priority as
its prior IP layer, which has a layer 3 priority. This will lead to
issues in matching and will match the packet with the first matching
rule even if it doesn't have an esp layer in its pattern, disregarding
any following rules that could have an esp item and can be actually
a more accurate match since it will have a longer matching criterion.

This is fixed by defining the priority for the ESP item to have a
layer 4 priority, making the match be for the rule with the more
accurate and longer matching criteria.

Fixes: 18ca4a4ec7 ("net/mlx5: support ESP SPI match and RSS hash")
Cc: stable@dpdk.org

Signed-off-by: Bassam Zaid AlKilani <bzalkilani@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Raslan Darawsheh <rasland@nvidia.com>
2022-10-02 09:13:51 +02:00
Michael Baum
593f913a8e net/mlx5: fix LRO requirements check
One of the conditions to allow LRO offload is the DV configuration.

The function incorrectly checks the DV configuration before initializing
it by the user devarg; hence, LRO cannot be allowed.

This patch moves this check to mlx5_shared_dev_ctx_args_config, where DV
configuration is initialized.

Fixes: c4b8620135 ("net/mlx5: refactor to detect operation by DevX")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Reported-by: Gal Shalom <galshalom@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-10-02 09:13:51 +02:00
Gregory Etelson
2d8dde8d63 common/mlx5: lower some DevX log level
Current PMD logs all DevX errors at error level.

DevX interface can fail queue counters allocation on some hardware
types. That is a known issue.
PMD fallbacks to Verbs API to allocate queue counters
when it detects the fault.
That DevX failure should not be logged as PMD error.

The patch provides DevX with flexible API that selects log level.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-10-02 09:13:50 +02:00
Long Li
bc5d8fdb70 net/mlx5: fix Verbs FD leak in secondary process
FDs passed from rte_mp_msg are duplicated to the secondary process and
need to be closed.

Fixes: 9a8ab29b84 ("net/mlx5: replace IPC socket with EAL API")
Cc: stable@dpdk.org

Signed-off-by: Long Li <longli@microsoft.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-10-02 09:13:50 +02:00
Long Li
ff9c3548c0 net/mlx4: fix Verbs FD leak in secondary process
FDs passed from rte_mp_msg are duplicated to the secondary process and
need to be closed.

Fixes: 0203d33a10 ("net/mlx4: support secondary process")
Cc: stable@dpdk.org

Signed-off-by: Long Li <longli@microsoft.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-10-02 09:13:48 +02:00
Alexander Chernavin
52bd03e969 net/virtio: fix crash when configured twice
When first attempt to configure a device with RX interrupt enabled fails
for some reason (e.g. because "Multiple intr vector not supported"),
second attempt to configure the device with RX interrupt disabled and
feature set unchanged will succeed but will leave virtio queues not
allocated. Accessing the queues will cause a segfault.

First attempt:
  - virtio_dev_configure()
    - virtio_init_device() is called to reinit the device because
      "dev->data->dev_conf.intr_conf.rxq" is "1"
      - virtio_configure_intr() fails and returns an error
      - virtio_free_queues() frees previously allocated virtio queues
    - virtio_init_device() fails and returns an error
  - virtio_dev_configure() fails and returns an error

Second attempt:
  - virtio_dev_configure()
    - This time virtio_init_device() is not called, virtio queues
      are not allocated

With this fix, reinit the device during configuration if virtio queues
are not allocated.

Fixes: 2b38151f74 ("net/virtio: fix queue memory leak on error")
Cc: stable@dpdk.org

Signed-off-by: Alexander Chernavin <achernavin@netgate.com>
Reviewed-by: Chenbo Xia <chenbo.xia@intel.com>
2022-09-29 10:13:22 +02:00
Zhichao Zeng
f7c8c36fde net/iavf: enable inner and outer Tx checksum offload
This patch is to enable scalar path inner and outer Tx checksum offload
for tunnel packet by configure ol_flags.

Signed-off-by: Peng Zhang <peng1x.zhang@intel.com>
Signed-off-by: Zhichao Zeng <zhichaox.zeng@intel.com>
Tested-by: Ke Xu <ke1.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-25 16:07:02 +02:00
Zhichao Zeng
3b8c645afa net/iavf: fix outer checksum flags
When receiving tunneled packets, the testpmd output log shows 'ol_flags'
value always as 'RTE_MBUF_F_RX_OUTER_L4_CKSUM_UNKNOWN', but expected value
should be 'RX_OUTER_L4_CKSUM_GOOD' or 'RX_OUTER_L4_CKSUM_BAD'.

Adding 'RX_OUTER_L4_CKSUM_GOOD' and 'RX_OUTER_L4_CKSUM_BAD' to 'flags' for
normal path, 'l3_l4_flags_shuf' for AVX2 and AVX512 vector path and
'cksum_flags' for SSE vector path to ensure that the 'ol_flags'
can match correct flags.

Fixes: b8b4c54ef9 ("net/iavf: support flexible Rx descriptor in normal path")
Fixes: 1162f5a0ef ("net/iavf: support flexible Rx descriptor in SSE path")
Fixes: 5b6e885908 ("net/iavf: support flexible Rx descriptor in AVX path")
Fixes: 9c9aa00403 ("net/iavf: add offload path for Rx AVX512 flex descriptor")
Cc: stable@dpdk.org

Signed-off-by: Zhichao Zeng <zhichaox.zeng@intel.com>
Tested-by: Ke Xu <ke1.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-25 16:00:43 +02:00
Zhichao Zeng
1aaacea174 net/iavf: fix processing VLAN TCI in SSE path
The SSE RX path does not process the vlan tci correctly when it's stored
in L2TAG2, so the vlan tci could not be extracted from descriptor,
then would not be put into mbuf either.

Add processing when vlan tci is stored in L2TAG2.

Fixes: 1162f5a0ef ("net/iavf: support flexible Rx descriptor in SSE path")
Cc: stable@dpdk.org

Signed-off-by: Zhichao Zeng <zhichaox.zeng@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-23 10:47:08 +02:00
Simei Su
e35f6b1cd1 net/ice: fix PTP init
Because of base code update, "ice_ptp_init_phc" API for E810/E822 depends
on PHY configuration, not whether the device is E810 based. So before this
API is called, assign specific value to phy cfg.

Fixes: 646dcbe6c7 ("net/ice: support IEEE 1588 PTP")
Cc: stable@dpdk.org

Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-20 10:57:35 +02:00
Markus Theil
f082b51958 net/ice: support LED control
Added LED control support.

Signed-off-by: Markus Theil <markus.theil@secunet.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-20 10:44:57 +02:00
Qi Zhang
61da836257 net/ice/base: update copyright
Updated copyright to 2022 and update base code version.

Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
47bf7453a6 net/ice/base: clean up
1. remove unused code
2. reduce variable scope
3. fix comment

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
d56833508e net/ice/base: expose sched element move function
Exposed ice_aq_move_sched_elems to support sched element moving
by AQ command.

Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
41d843bd60 net/ice/base: check for PTP HW lock more frequently
PTP HW semaphore can be held for ~50 ms in worst case.
SW should wait longer and check more frequently if
the HW lock is held.

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
dbbf83ce0e net/ice/base: add GTP tunnel
Added GTP tunnel type and also re-order the code to align with
kernel driver.

Signed-off-by: Marcin Szycik <marcin.szycik@intel.com>
Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
a7b867e989 net/ice/base: remove unnecessary fields
Remove unnecessary fields in data structure for 1588 and QoS
func capabilities.

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
20c549a89d net/ice/base: convert 1588 structs to use bit fields
Use bitfields in 1588 structs so they don't waste too much space.

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
7ab3a759d4 net/ice/base: handle default VSI lookup type
ICE_SW_LKUP_DFLT is handled in ice_update_vsi_list_rule and
ice_aq_alloc_free_vsi_list.

Signed-off-by: Lukasz Kupczak <lukasz.kupczak@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
ed86e63543 net/ice/base: add function to parse DCBX config
LLDP MIB Change Event (opcode 0x0A01) already contains MIB, which
has been changed. Add ice_dcb_process_lldp_set_mib_change() function,
which will set local/remote DCBX config from LLDP MIB Change Event's
buffer.

This function will be used in a base driver handler for LLDP MIB
Change Event.

Signed-off-by: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
97e32e8d48 net/ice/base: complete pending LLDP MIB
Completed structure ice_aqc_lldp_get_mib.
Added 'Pending Event Enable' bit.

Signed-off-by: Tsotne Chakhvadze <tsotne.chakhvadze@intel.com>
Signed-off-by: Karen Sornek <karen.sornek@intel.com>
Signed-off-by: Anatolii Gerasymenko <anatolii.gerasymenko@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
04ab2b2f0b net/ice/base: fix comment of overloaded GCO bit
The bit that is overloaded is bit 11 in the flex descriptor,
updating the comment to have the right one reflected.

Signed-off-by: Alice Michael <alice.michael@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
3f34e62690 net/ice/base: add unload flag for control queue shutdown
Admin queue command for shutdown AQ contains flag to indicate
driver unload. However the flag is always set in driver, even
for the resets. It causes Firmware to consider driver as unloaded
once the PF reset is triggered on all ports of device. Firmware then
restores default configuration of some features like Tx Balancing,
which is not expected behavior.
This patch added an additional function parameter to indicate
driver unload.

Signed-off-by: Piotr Gardocki <piotrx.gardocki@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
b0472e210f net/ice/base: fix input set of GTPoGRE
For GTPoGRE, When setting the prot_id of prot, it should be
set to second inner.

Fixes: 34a0e7c44f ("net/ice/base: improve flow director masking")
Cc: stable@dpdk.org

Signed-off-by: Kevin Liu <kevinx.liu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
01aec828d9 net/ice/base: add GRE TAP tunnel type
Added new tunnel type to support NvGRE

Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
bf66265397 net/ice/base: support L2TPv2 flow rule
Add L2TPv2 (include PPP over L2TPv2) support for FDIR.

And add support PPPoL2TPv2oUDP with inner IPV4/IPV6/UDP/TCP for
FDIR.

The supported L2TPv2 packets are defined as below:
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_CONTROL
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV4
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV4_UDP
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV4_TCP
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV6
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV6_UDP
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV6_TCP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_CONTROL
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV4
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV4_UDP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV4_TCP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV6
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV6_UDP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV6_TCP

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
f203e2ba10 net/ice/base: support RSS with L2TPv2 session ID
Add L2TPv2 session ID field support for RSS.

Enable L2TPv2 non-tunneled packet types for UDP protocol header
bitmaps.

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
5aa6d76051 net/ice/base: add generic MAC with 3K signature segment
Define new type id ICE_MAC_GENERIC_3k in ice_mac_type enum, to
distinguish devices which use RSA-3K/SHA-384 segment signature type.
Use 3k signing type for E824S device.

Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
5a6a27c8fa net/ice/base: support custom WPC and LGB NICs
There are few custom Westport Channel (WPC) and Logan Beach (LGB)
network interface cards (NICs) - add their subdevice IDs to be
able to distinguish them.

Signed-off-by: Michal Michalik <michal.michalik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
b7a6a9733c net/ice/base: clean main timer command register
Clean the main timer command register after use to avoid residual
command execution, such as re-initialization of the main timer.

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
5f5b5d3f86 net/ice/base: update PHY type high max index
ICE_PHY_TYPE_HIGH_MAX_INDEX should be the maximum index value and
not the length/number of ICE_PHY_TYPE_HIGH.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
4b6ede113f net/ice/base: support auto FEC with FEC disabled
The default Link Establishment State Machine (LESM) behavior does
not allow the use of FEC disable mode if the media does not support
FEC disabled. However users may want to override this behavior.

Add support for setting Auto FEC with FEC disabled.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
2421af6c56 net/ice/base: clean up rule add without lookup
The add rule functionality works fine with a NULL lookups parameter.
However when running the undefined behavior sanitizer it noticed that
the function could trigger a memcpy from a NULL target.

Fix the code to handle NULL lkups and a zero lkups_cnt variable more
explicitly, and clean up the test to just directly pass a NULL value
instead of allocating a stack variable assigned to NULL and passing
that as a pointer.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
68834871b2 net/ice/base: ignore promiscuous already exist
Ignore ERR_ALREADY_EXISTS error when setting promiscuous mode.
This fix is needed because the driver could set promiscuous mode
when it still has not cleared properly.
Promiscuous mode could be set only once, so setting it second
time will be rejected.

Fixes: 60ff6f5ce2 ("net/ice/base: consolidate VF promiscuous mode")
Cc: stable@dpdk.org

Signed-off-by: Grzegorz Siwik <grzegorz.siwik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
3cfa5591b2 net/ice/base: refine header file include
The ice_switch.h and ice_fdir.h headers include ice_common.h. They
are both themselves included in ice_common.h. This causes a circular
dependency ordering.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
23351e2ae7 net/ice/base: update L2TPv2 packet type values
Because the macros of L2TPv2 packet type value were changed in
ice_ppp-o-l2tpv2-o-udp-1.3.4.0.pkg. So update the macros of L2TPv2
packet type value and the bitmaps of packet types for relevant
protocol header to match the new DDP package.

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
d308398cda net/ice/base: update definitions for AQ debug dump
Add defines for Queue Mng and Full CSR Space in debug
dump internal data. This defines are used in Lanconf for
debug dump. Added QV_SUPPORT macro in ifdef for ACL.

Signed-off-by: Dawid Zielinski <dawid.zielinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
e980509c3f net/ice/base: complete support for Tx balancing
Add module ID and struct necessary to read and save Tx Scheduler
Topology Tree User Selection data from PFA TLV.

Signed-off-by: Lukasz Czapnik <lukasz.czapnik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
0012bc2d87 net/ice/base: move functions
Move function ice_ptp_set_vernier_wl and ice_ptp_src_cmd to align with
kernel driver.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
40ff47dd4b net/ice/base: fix double VLAN in promiscuous mode
Avoid enabling or disabling vlan 0 when trying to set promiscuous
vlan mode if double vlan mode is enabled. This fix is needed
because the driver tries to add the vlan 0 filter twice (once for
inner and once for outer) when double VLAN mode is enabled. The
filter program is rejected by the firmware when double vlan is
enabled, because the promiscuous filter only needs to be set once.

This issue was missed in the initial implementation of double vlan
mode.

Fixes: 60ff6f5ce2 ("net/ice/base: consolidate VF promiscuous mode")
Cc: stable@dpdk.org

Signed-off-by: Grzegorz Siwik <grzegorz.siwik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
dcdbb1e405 net/ice/base: add low latency Tx timestamp read
E810 products can support low latency Tx timestamp register read.
Add a check for the device capability and use the new method if
supported.

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
de281096d1 net/ice/base: add helper to check device is E823
Add a simple function checking if the device is E823-L or E823-C
based.

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
97061639bc net/ice/base: cast types to match data sizes
Adding typecast to variables to avoid compiler warnings generated if
variables of a particular data type are assigned to ones of a
smaller data type. For example assigning an unsigned 16 bit integer
to an 8 bit integer could trigger data loss warnings or errors.

Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
c82b04c2d2 net/ice/base: adjust VSI/aggregator layers
Adjust the VSI/Aggregator layers based on the number of logical
layers supported by the FW. Currently the VSI and aggregator layers are
fixed based on the 9 layer scheduler tree layout. Due to performance
reasons the number of layers of the scheduler tree is changing from
9 to 5. It requires a readjument of these VSI/Aggregator layer
values.

Signed-off-by: Victor Raj <victor.raj@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
2be2fabdee net/ice/base: support Tx topology config
Complete the Tx topo config implementation.

Signed-off-by: Victor Raj <victor.raj@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
5dbc19cf43 net/ice/base: fix add MAC rule
Fix ice_add_mac_rule function by not overriding action value
with vsi id. It's possible to add MAC based switch filters
with action other than FWD_TO_VSI.
In current implementation fwd_id member of filter config
structure was always overwritten with hw vsi index, regardless
of action type.
Fix it, by setting hw vsi index only for FWD_TO_VSI action
filter and leave it as it is in case of other actions.

Fixes: 3ee1b0159e ("net/ice/base: support adding MAC rules on specific port")
Cc: stable@dpdk.org

Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
71dce67ab1 net/ice/base: refine default VSI config
Refine API ice_cfg_dflt_vsi and add new API
ice_check_if_dflt_vsi.

Signed-off-by: Michal Wilczynski <michal.wilczynski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
38ef9e1b99 net/ice/base: fix null pointer dereference
Sometimes, during the shutdown process, a PCIe unrecoverable error
occurs. This leads to the following NULL pointer dereference error
while clearing hardware tables:

The patch fixes this bug by checking every table pointer against
NULL before reference it, as some of them probably have been cleared
in advance.

Fixes: 969890d505 ("net/ice/base: enable clearing of HW tables")
Cc: stable@dpdk.org

Signed-off-by: Roman Storozhenko <roman.storozhenko@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
9ad9e34820 net/ice/base: add AQ command to config node attribute
Added AQ command to config nod attribute.

Signed-off-by: Ben Shelton <benjamin.h.shelton@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
7bbc85ce2c net/ice/base: rename PHY/QUAD/ports definitions
Rename PHY/QUAD/ports definitions to reflect the correct HW
specification.

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
c0ad102b47 net/ice/base: move function to internal
The function ice_disable_fd_swap should be defined as static.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
ac549a3249 net/ice/base: fix bit finding range over ptype bitmap
The 2nd argument to function ice_find_first_bit is the bitmap size,
(in bits) not a mask. Thus, use of UINT16_MAX or 0xFFFF will allow a
potential run off the end of the ptype array.
Also, the ptype bitmap (i.e., prof->ptypes) is declared with size
ICE_FLOW_PTYPE_MAX, thus finding the bits within this bitmap should
not exceed this bound.

Fixes: 8ebb93942b ("net/ice/base: add function to set HW profile for raw flow")
Cc: stable@dpdk.org

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
289b2846c1 net/ice/base: fix array overflow in add switch recipe
The array indexes in this function are used with a zero index in the
fv_idx table, and with a +1 index in the lkup_idx arrays. The code
was using the lookup index for the field vector in only one place in
this function, but the code was never used after this point so just
remove the bad line.

This was caught by the undefined behavior sanitizer.

Fixes: fed0c5ca5f ("net/ice/base: support programming a new switch recipe")
Cc: stable@dpdk.org

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
e48a4589b0 net/ice/base: convert array of u8 to bitmap
Previously the ice_add_prof function took an array of u8 and looped
over it with for_each_set_bit, examining each 8 bit value as a bitmap.

This was just hard to understand and unnecessary, and was triggering
undefined behavior sanitizers with unaligned accesses within bitmap
fields. Since the ptype being passed in was already declared as a
bitmap, refactor this to use native types with the advantage of
simplifying the code to use a single loop.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
d374022f21 net/ice/base: convert IO expander handle to u16
The io_expander_handle cached value is marked as an __le16, but
several places track the node handle with u16 values. Unify all
the interfaces so that it is stored and reported as a u16, and
keep the low level conversion to LE16 only at the direct firmware
interface.

This fixes warnings from sparse about mixing __le16 and u16, and
will fix related issues on platforms which use Big Endian format.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
843a099aa2 net/ice/base: fix endian format
A few functions failed to properly convert some values into Little
Endian format before sending them to the firmware. This will produce
incorrect results when running on a Big Endian platform.

Fix this by adding the necessary CPU_TO_LE* macros around the input
to firmware.

These issues were detected by sparse.

Fixes: 0f61c2af88 ("net/ice/base: add set/get GPIO helper functions")
Cc: stable@dpdk.org

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
0486c968f6 net/ice/base: fix function descriptions for parser
Some function descriptions for parser are mismatched, thus fixed
with this patch.

Fixes: 7fe2d98070 ("net/ice/base: add parser create and destroy skeleton")
Fixes: 1792942b2d ("net/ice/base: init boost TCAM table for parser")
Fixes: f787952d13 ("net/ice/base: init flag redirect table for parser")
Fixes: b3e73a812f ("net/ice/base: init IMEM table for parser")
Fixes: 2f7a1864cc ("net/ice/base: init metainit table for parser")
Fixes: 90bbd7d954 ("net/ice/base: init marker group table for parser")
Fixes: c55b1ba93f ("net/ice/base: init parse graph CAM table for parser")
Fixes: 7b61be517f ("net/ice/base: init protocol group table for parser")
Fixes: 111871087c ("net/ice/base: init ptype marker TCAM table for parser")
Fixes: 0cbacf60dc ("net/ice/base: init XLT key builder for parser")
Cc: stable@dpdk.org

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
8f43c8205c net/ice/base: detect duplicate ACL rules
Currently there is no check for adding duplicate ACL rules,
this creates subtle bugs, for example unability to remove
filters. Adding check + refactoring a redundant function.

Signed-off-by: Michal Wilczynski <michal.wilczynski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
234f985695 net/ice/base: report NVM version numbers on mismatch
Report NVM version numbers (both detected and expected) when a
mismatch b/w driver and firmware is detected.
This would provide more useful information about which NVM
version the driver expects instead of looking up the code

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
419aede32c net/ice/base: support double VLAN rules
Add support for double vlan rules with c-tag and s-tag in it.
Enable the caller to configure double vlan rules, and use extended
package capabilities to allow adding flow with double vlans.

The patch also re-order the code in ice_switch.c to align with
kernel driver.

Signed-off-by: Wiktor Pilarczyk <wiktor.pilarczyk@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
1b04de20a2 net/ice/base: add E822 generic PCI device ID
The E822 has a generic PCI device ID that can be used in the PLDM
header when updating the device so add it.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
ed3066a3b1 net/ice/base: refactor DDP code
Move DDP related into ice_ddp.c.
Refactor status flow for DDP load.
Also added support for DDP signature segments.

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Wojciech Drewek <wojciech.drewek@intel.com>
Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
ef12579699 net/ice/base: fix media type of PHY 10G SFI C2C
PHY type ICE_PHY_TYPE_LOW_10G_SFI_C2C is incorrectly mapped to media
type Fiber which results in ethtool reporting the wrong Supported
ports.

PHY type ICE_PHY_TYPE_LOW_10G_SFI_C2C should map to media type
Backplane.

Fixes: 453d087cca ("net/ice/base: add common functions")
Cc: stable@dpdk.org

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
cb02072170 net/ice/base: enable calling ETH56G functions
Enable calling of ETH56G functions in the base code when the
appropriate PHY has been detected

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
fb800fde66 net/ice/base: work around missing PTP capabilities
Provide a WA for missing PTP caps on Simics, this code shall be
removed after cap reporting is fixed

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
e05720c063 net/ice/base: implement 56G PHY setup functions
Implement setup functions for the 56G PHY Simics model

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
680793c782 net/ice/base: implement 56G PHY access functions
Implement 56G PHY register and memory read/write functions
to facilitate PTP support

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
88b32fd7cc net/ice/base: add 56G PHY register definitions
Add 56G PHY register address definitions to facilitate 56G PHY
support.

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
f4ce264ffe net/ice/base: add 56G PHY destination address
Add PHY 56G destination address. PHY56G is a single device
incorporating all SerDes lanes

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
85508ab0c7 net/ice/base: move code block
Move some code block to the beginning of ice_ptp_hw.c to align
with kernel driver.

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
0fb8370005 net/ice/base: add suffix to E822-specific functions
Add the suffix to E822 HW-dependent function names

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
5a71038ffa net/ice/base: complete health status codes
add definitions for async health status codes.

Signed-off-by: Leszek Zygo <leszek.zygo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
bc696378a9 net/ice/base: fix DSCP PFC TLV creation
When creating the TLV to send to the FW for configuring DSCP
mode PFC, the PFCENABLE field was being masked with a 4 bit
mask (0xF), but this is an 8 bit bitmask for enabled classes
for PFC.  This means that traffic classes 4-7 could not be
enabled for PFC.

Remove the mask completely, as it is not necessary, as we are
assigning 8bits to an 8 bit field.

Fixes: 8ea78b1696 ("net/ice/base: support L3 DSCP QoS")
Cc: stable@dpdk.org

Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
9066f200cb net/ice/base: support VXLAN and GRE for RSS
Add RSS of inner headers for VXLAN tunnel packet.

Add packet types for packets with outer IPv4/IPv6 header
support GRE and VXLAN tunnel packet.

Following rules can use new packet types:
    - eth / ipv4(6) / udp / vxlan / ipv4(6)
    - eth / ipv4(6) / udp / vxlan / ipv4(6) / tcp
    - eth / ipv4(6) / udp / vxlan / ipv4(6) / udp
    - eth / ipv4(6) / gre / ipv4(6)
    - eth / ipv4(6) / gre / ipv4(6) / tcp
    - eth / ipv4(6) / gre / ipv4(6) / udp

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
8f81056e5a net/ice/base: fix 100M speed capability
Couple of 10GBase-T devices don't support advertising 100M
speed. For these devices, ice_is_100m_speed_supported should
return false. Meanwhile add device that supports 100M speed.

Fixes: 486d29fda5 ("net/ice/base: add dedicate MAC type for E810")
Cc: stable@dpdk.org

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
0054012bd8 net/ice/base: add auto drop blocking packets
Extended ice_aq_set_mac_cfg()function to add support for
auto drop blocking packets.

Signed-off-by: Mateusz Rusinski <mateusz.rusinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
4e1d404e03 net/ice/base: fix division during E822 PTP init
When initializing the device hardware for PTP, the E822 devices
requirea number of values to be calculated and programmed to
hardware.These values are calculated using unsigned 64-bit
division.

The DIV_64BIT macro currently translates into a specific Linux
functionthat triggers a *signed* division. This produces incorrect
results when operating on a dividend larger than an s64. The
division calculation effectively overflows and results in totally
unexpected behavior.

In this case, the UIX value for 10Gb/40Gb link speeds are calculated
incorrectly. This ultimately cascades into a failure of the Tx
timestamps. Specifically, the reported Tx timestamps become wildly
inaccurate and not representing nominal time.

The root cause of this bug is the assumption that DIV_64BIT can
correctly handle both signed and unsigned division. In fact the
entire reason we need this is because the Linux kernel compilation
target does not provide native 64 bit division ops, and requires
explicit use of kernel functions which explicitly do either signed
or unsigned division.

To correctly solve this, introduce new functions, DIV_U64 and
DIV_S64 which are specifically intended for signed or unsigned
division. To help catch issues, use static inline functions so
that we get strict type checking.

Fixes: 97f4f78bbd ("net/ice/base: add functions for device clock control")
Cc: stable@dpdk.org

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
683b6ab56e net/ice/base: make function names more generic
Previously "e810t" was part of few function names.
In the future it will require to add similar functions
for different NIC types.
Make "NIC type" a suffix of the function name.

Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
f450334f47 net/ice/base: combine functions for VSI promiscuous
Remove ice_get_vsi_vlan_promisc,
cause of similar implementation as ice_get_vsi_promisc,
which will now handle the use case of ice_get_vsi_vlan_promisc.

Signed-off-by: Wiktor Pilarczyk <wiktor.pilarczyk@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
2146d23a18 net/ice/base: get NVM CSS header length from CSS header
The CSS Header length is defined as ICE_CSS_HEADER_LENGTH. To
support changes in CSS Header length, calculate the CSS Header
length from the NVM CSS Header length field plus the Authentication
Header length.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
10eddf13bd net/ice/base: add netlist helper functions
Add new functions to check in netlist if HW has:
- Recovered Clock device,
- Clock Generation Unit,
- Clock Multiplexer,
- GPS generic device.

Signed-off-by: Michal Michalik <michal.michalik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00