Commit Graph

34241 Commits

Author SHA1 Message Date
Vidya Sagar Velumuri
2eddc5942f test/crypto: check anti-replay capability in ingress
Antireplay is supported only for ingress.
Check this capability only for ingress.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
2022-10-29 13:01:41 +02:00
Vidya Sagar Velumuri
0f2748a096 test/security: update anti-replay cases for event mode
When event mode is enabled,
send and receive packets via event dev.
Updated the antireplay cases to enable event mode.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
2022-10-29 13:01:40 +02:00
Vidya Sagar Velumuri
5a23f6ea39 test/security: add MD5 cases
Add unit test cases for MD5 auth algo.
Add the test vectors for MD5 auth algo.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
2022-10-29 13:01:40 +02:00
Vidya Sagar Velumuri
d70018639e test/security: add DES and 3DES cases
Add unit test cases and test vectors for DES-CBC
and 3DES-CBC.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
2022-10-29 13:01:40 +02:00
Anoob Joseph
bb0e4a96d8 crypto/cnxk: remove dead code
Coverity issue: 381022
Fixes: d94414d162 ("crypto/cnxk: separate out PDCP cipher datapath")

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
2022-10-29 13:01:40 +02:00
Anoob Joseph
4f030d8674 crypto/cnxk: verify IV length during session create
For Kasumi cipher operation, IV is a must. Verify the arg provided in
session creation and remove datapath check.

Coverity issue: 381020, 381019
Fixes: 7a59ccc1b5 ("crypto/cnxk: remove extra indirection for FC and Kasumi")

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
2022-10-29 13:01:40 +02:00
Vidya Sagar Velumuri
e0cb7b8987 crypto/cnxk: acquire lock for anti-replay
Acquired locks in antireplay logic to avoid race condition.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
2022-10-29 13:01:40 +02:00
Tejasree Kondoj
5fc5e9d23b crypto/cnxk: support PDCP AAD in CPT
Adding support for PDCP AAD in 96xx crypto pmd.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
2022-10-29 13:01:40 +02:00
Vidya Sagar Velumuri
729085b508 common/cnxk: generate MD5 ipad opad
Add support to generate ipad and opad for MD5.
Skip the call to additional command WRITE_SA during SA creation.
Instead use the software defined function to generate opad and ipad.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
2022-10-29 13:01:40 +02:00
Vidya Sagar Velumuri
379bc7f43f crypto/cnxk: support DES and MD5 for IPsec offload
Add supoort for cipher DES and auth MD5 for IPsec offload.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
2022-10-29 13:01:40 +02:00
Vidya Sagar Velumuri
91c8925f99 crypto/cnxk: update lookaside RLEN calculation
For transport mode, IP header will not be part of encryption.
Update the response len calculation accordingly for transport mode.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
2022-10-29 13:01:40 +02:00
Vidya Sagar Velumuri
39ae58f294 common/cnxk: support custom UDP port values
Added support for custom port values for UDP encapsulation.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
2022-10-29 13:01:40 +02:00
Tejasree Kondoj
7c19abdd0c common/cnxk: support 103XX CPT
Added support for 103XX CPT variant.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
2022-10-29 13:01:40 +02:00
Tejasree Kondoj
cb6bfc96c3 crypto/cnxk: update capabilities as per firmware
Updated CPT engine capabilities structure as per microcode.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
2022-10-29 13:01:40 +02:00
Tejasree Kondoj
48c551761b common/cnxk: set in-place bit of lookaside IPsec
Set inplace bit of lookaside IPsec and
remove rptr population in datapath.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
2022-10-29 13:01:40 +02:00
Tejasree Kondoj
0b976b987f crypto/cnxk: fix AES-CMAC length
AES-CMAC uses PDCP opcode and hence
length should be passed in bits.

Fixes: 759b5e6535 ("crypto/cnxk: support AES-CMAC")
Cc: stable@dpdk.org

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
2022-10-29 13:01:40 +02:00
Arek Kusztal
b6ac58aee5 crypto/qat: read HW slice configuration
Read slice configuration of QAT capabilities.
This will allow to recognize if specific HW function
is available on particular generation of device.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
2022-10-29 13:01:40 +02:00
Arek Kusztal
b3cbbcdffa common/qat: read HW slice configuration
Read slice configuration of QAT capabilities.
This will allow to recognize if specific hw function
is available on particular generation of device.
Added function pointers for each QAT generations.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
2022-10-29 13:01:40 +02:00
Arek Kusztal
112b6215e0 crypto/qat: fix RSA length
Fixed not set output length in asym pmd when doing RSA.

Fixes: 002486db23 ("crypto/qat: refactor asymmetric session")
Cc: stable@dpdk.org

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Ciara Power <ciara.power@intel.com>
2022-10-29 13:01:40 +02:00
Arek Kusztal
521cd3f947 crypto/qat: fix unnecessary asymmetric session check
Removed unnecessary session check which could lead to segfault,
in case api was changed.

Fixes: 002486db23 ("crypto/qat: refactor asymmetric session")
Cc: stable@dpdk.org

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Ciara Power <ciara.power@intel.com>
2022-10-29 13:01:40 +02:00
Arek Kusztal
fdf9cdaca7 crypto/qat: fix asymmetric session cookie clearing
Fixed incorrectly placed clean function in asym response.

Fixes: 002486db23 ("crypto/qat: refactor asymmetric session")
Cc: stable@dpdk.org

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Ciara Power <ciara.power@intel.com>
2022-10-29 13:01:40 +02:00
Hernan Vargas
b4bd57b74c baseband/acc100: configure PMON control registers
Enable performance monitor control registers.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:40 +02:00
Hernan Vargas
989dec301a baseband/acc100: add ring companion address
Store the virtual address of companion ring as part of queue
information. Use this address to calculate the op address.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:40 +02:00
Hernan Vargas
8e71bfcebb baseband/acc100: update device info
Remove unused capabilities, use dummy operation as start count for
number of queues.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:40 +02:00
Hernan Vargas
3a77593b1e baseband/acc100: store FCW from first CB descriptor
Store the descriptor from the first code block from a transport block.
Copy the LDPC FCW from the first descriptor into the rest of the CBs in
that TB.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:40 +02:00
Hernan Vargas
69fbbc3f77 baseband/acc100: update log messages
Add extra values for some log messages. No functional impact.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:40 +02:00
Hernan Vargas
53352f6b69 baseband/acc100: update uplink CB input length
Use the FCW E parameter for rate matching
as the code block input length.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:40 +02:00
Hernan Vargas
ae555d42ec baseband/acc100: add queue stop operation
Implement new feature to stop queue operation.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:40 +02:00
Hernan Vargas
f3f66e827b baseband/acc100: implement configurable queue depth
Implement new feature to make queue depth configurable
based on decode or encode mode.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:40 +02:00
Hernan Vargas
39fe62d0ea baseband/acc100: update LDPC enc/dec validation
Update validate functions to check for valid LDPC parameters to avoid
any HW issues.
Adding protection for null corner case and for HARQ inbound size out
of range.
HARQ input size from application may be invalid and causing HW issue.
Add checks to ensure that if HARQ is invalid, set to some valid size to
ensure HW issues do not occur.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
c7847be75c baseband/acc100: support LDPC transport block
Added LDPC enqueue functions to handle transport blocks.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
4afc627f32 baseband/acc100: enable input validation by default
Enable validation functions by default and provide a new flag
RTE_LIBRTE_SKIP_VALIDATE if the user wants to run without
validating input to save cycles.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
7104c6b8d4 baseband/acc100: add HARQ index helper function
Refactor code to use the HARQ index helper function and make harq_idx
uint32.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
f7613291d5 baseband/acc100: support scatter-gather
Add flag to support scatter-gather for the mbuf

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
103161cc93 baseband/acc100: add enqueue status
Add enqueue status as part of rte_bbdev_queue_data.
This is a new feature to update queue status and indicate the reason why
a previous enqueue may or may not have consumed all requested operations.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
1884ff4f50 baseband/acc100: update debug print for LDPC FCW
Print full size of FCW LDPC structure on debug messages.
This is just a cosmetic fix, no need to fix on previous code base.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
ba2262fe16 baseband/acc100: fix close cleanup
Set local pointer to NULL after rte_free.
This needs to be set explicitly since logic may check for null pointers.

Fixes: 060e767293 ("baseband/acc100: add queue configuration")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
75114f78cf baseband/acc100: fix null HARQ input case
An invalid HW operation may be caused in case the user provide
the BBDEV API and HARQ operation with input enabled and zero input.
Added protection for that case.

Fixes: 5ad5060f8f ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
badb3b79b9 baseband/acc100: fix device minimum alignment
Historical mistakes, there should be no 64B alignment requirement for
the buffer being processed. Any 1B alignment is sufficient.

Fixes: 9200ffa5cd ("baseband/acc100: add info get function")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
935745f56b baseband/acc100: fix clearing PF IR outside handler
Clearing of PF info ring outside of handler may cause interrupt to be
missed.
A condition in the ACC100 PMD implementation may cause an interrupt
functional handler call to be missed due to related bit being cleared
when checking PF info ring status.

Fixes: 0653146415 ("baseband/acc100: support interrupt")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
ec1424fffa baseband/acc100: fix input length for CRC24B
Input length should be reduced only for CRC24B.

Fixes: 5ad5060f8f ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
e23491fc2e baseband/acc100: fix ring/queue allocation
Allocate info ring, tail pointers and HARQ layout memory
for a device only if it hasn't already been allocated.

Fixes: 0653146415 ("baseband/acc100: support interrupt")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
5802f36dd4 baseband/acc100: enforce additional check on FCW
Enforce additional check on Frame Control Word validity and
add stronger alignment for decompression mode.

Fixes: 5ad5060f8f ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
4a2f231ee1 baseband/acc100: add null checks
Add unlikely checks for NULL operation values.

Fixes: f404dfe35c ("baseband/acc100: support 4G processing")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
1d43b46139 baseband/acc100: check turbo dec/enc input
Add NULL check for the turbo decoder and encoder input length.

Fixes: 3bfc5f6040 ("baseband/acc100: add debug function to validate input")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
6f3325bbfa baseband/acc100: add LDPC encoder padding function
LDPC Encoder input may need to be padded to avoid small beat for ACC100.
Padding 5GDL input buffer length (BLEN) to avoid case (BLEN % 64) <= 8.
Adding protection for corner case to avoid for 5GDL occurrence of last
beat within the ACC100 fabric with <= 8B which might trigger a fabric
corner case hang issue.

Fixes: 5ad5060f8f ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
36341139e4 baseband/acc100: fix memory leak
Moved check for undefined device before allocating queue data structure.

Coverity issue: 375803, 375813, 375819, 375827, 375831
Fixes: 060e767293 ("baseband/acc100: add queue configuration")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
2df5fe2023 baseband/acc100: check AQ availability
In some corner case to run more batch enqueue than
supported. A protection is required to avoid that corner case.
Enhance all ACC100 enqueue operations with check to see if there is room
in the atomic queue(AQ) for enqueueing batches into the queue manager.

Fixes: 5ad5060f8f ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Hernan Vargas
c24d53b4cc baseband/acc100: fix ring availability calculation
Refactored queue availability computation to prevent the
application to dequeue more than what may have been enqueued.

Fixes: 5ad5060f8f ("baseband/acc100: add LDPC processing functions")
Cc: stable@dpdk.org

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:39 +02:00
Nicolas Chautru
9dcebacb0c baseband/acc: add descriptor index helpers
Added set of helper functions used through the code to
track descriptor indexes in a queue ring.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
2022-10-29 13:01:39 +02:00