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freebsd-dev/sys/dev/pci/pci.c

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Start each of the license/copyright comments with /*-, minor shuffle of lines
2005-01-06 01:43:34 +00:00
/*-
sys/dev: further adoption of SPDX licensing ID tags. Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
2017-11-27 14:52:40 +00:00
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
* Copyright (c) 2000, BSDi
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
Submitted by: Wolfgang Stanglmeier <wolf@dentaro.GUN.de> + Stefan Esser <se> Directory for PCI autoconfigure and device driver code.
1994-09-01 01:45:19 +00:00
Update the special handling code for ATA devices to allow usage of PCI native addressing. That means that if the HW says that using "real" addresses instead of the hardwired legacy compat ones is allowed, we will use them.
2004-06-29 20:25:43 +00:00
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
Devices behind downstream bridges should still get DMAR protection. Reviewed by: kib Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D19717
2019-04-01 19:08:05 +00:00
#include "opt_acpi.h"
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
#include "opt_bus.h"
Added a bit of missing functionality to make this work correctly on a wider variety of systems. Include the deivers from pci_intel.c in pci_config.c (I hope this is what was intended; my system works ok). Use pmap_mapdev(). Automatically map any large linear frame buffers or whatnot in VGA-style devices which ordinarily would not have their own drivers, and don't call not_supported() for them. (This shuts up complaints about my Matrox card.) Include the beginnings of what could eventually become dynamically-loadable PCI devices. Allow for the possibility of PCI devices simply providing a PCI veneer over an existing ISA device, and shut up about them, too. Make autoconfiguration text conform more to the style of other supported buses.
1994-09-14 01:34:51 +00:00
#include <sys/param.h>
Add support for ioctl() accesses to PCI config space registers. Garrett Wollman sent me this code a few weeks ago for review, and I made some significant changes, which he in turn accepted ... In order to make use of these changes, a device entry has to added to /dev. Submitted by: wollman
1996-10-22 20:20:14 +00:00
#include <sys/conf.h>
Extract eventfilter declarations to sys/_eventfilter.h This allows replacing "sys/eventfilter.h" includes with "sys/_eventfilter.h" in other header files (e.g., sys/{bus,conf,cpu}.h) and reduces header pollution substantially. EVENTHANDLER_DECLARE and EVENTHANDLER_LIST_DECLAREs were moved out of .c files into appropriate headers (e.g., sys/proc.h, powernv/opal.h). As a side effect of reduced header pollution, many .c files and headers no longer contain needed definitions. The remainder of the patch addresses adding appropriate includes to fix those files. LOCK_DEBUG and LOCK_FILE_LINE_ARG are moved to sys/_lock.h, as required by sys/mutex.h since r326106 (but silently protected by header pollution prior to this change). No functional change (intended). Of course, any out of tree modules that relied on header pollution for sys/eventhandler.h, sys/lock.h, or sys/mutex.h inclusion need to be fixed. __FreeBSD_version has been bumped.
2019-05-20 00:38:23 +00:00
#include <sys/endian.h>
#include <sys/eventhandler.h>
#include <sys/fcntl.h>
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
#include <sys/kernel.h>
Extract eventfilter declarations to sys/_eventfilter.h This allows replacing "sys/eventfilter.h" includes with "sys/_eventfilter.h" in other header files (e.g., sys/{bus,conf,cpu}.h) and reduces header pollution substantially. EVENTHANDLER_DECLARE and EVENTHANDLER_LIST_DECLAREs were moved out of .c files into appropriate headers (e.g., sys/proc.h, powernv/opal.h). As a side effect of reduced header pollution, many .c files and headers no longer contain needed definitions. The remainder of the patch addresses adding appropriate includes to fix those files. LOCK_DEBUG and LOCK_FILE_LINE_ARG are moved to sys/_lock.h, as required by sys/mutex.h since r326106 (but silently protected by header pollution prior to this change). No functional change (intended). Of course, any out of tree modules that relied on header pollution for sys/eventhandler.h, sys/lock.h, or sys/mutex.h inclusion need to be fixed. __FreeBSD_version has been bumped.
2019-05-20 00:38:23 +00:00
#include <sys/limits.h>
#include <sys/linker.h>
#include <sys/malloc.h>
#include <sys/module.h>
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
#include <sys/queue.h>
Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
2002-07-26 07:58:16 +00:00
#include <sys/sysctl.h>
Extract eventfilter declarations to sys/_eventfilter.h This allows replacing "sys/eventfilter.h" includes with "sys/_eventfilter.h" in other header files (e.g., sys/{bus,conf,cpu}.h) and reduces header pollution substantially. EVENTHANDLER_DECLARE and EVENTHANDLER_LIST_DECLAREs were moved out of .c files into appropriate headers (e.g., sys/proc.h, powernv/opal.h). As a side effect of reduced header pollution, many .c files and headers no longer contain needed definitions. The remainder of the patch addresses adding appropriate includes to fix those files. LOCK_DEBUG and LOCK_FILE_LINE_ARG are moved to sys/_lock.h, as required by sys/mutex.h since r326106 (but silently protected by header pollution prior to this change). No functional change (intended). Of course, any out of tree modules that relied on header pollution for sys/eventhandler.h, sys/lock.h, or sys/mutex.h inclusion need to be fixed. __FreeBSD_version has been bumped.
2019-05-20 00:38:23 +00:00
#include <sys/systm.h>
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
Submitted by: Wolfgang Stanglmeier <wolf@dentaro.GUN.de> + Stefan Esser <se> Directory for PCI autoconfigure and device driver code.
1994-09-01 01:45:19 +00:00
#include <vm/vm.h>
Untangled the vm.h include file spaghetti.
1995-12-07 12:48:31 +00:00
#include <vm/pmap.h>
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
#include <vm/vm_extern.h>
Submitted by: Wolfgang Stanglmeier <wolf@dentaro.GUN.de> + Stefan Esser <se> Directory for PCI autoconfigure and device driver code.
1994-09-01 01:45:19 +00:00
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
#include <sys/bus.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
Include <machine/stdarg.h> for va_*(). I'm not sure how this compiled on amd64 without this.
2009-06-02 12:35:04 +00:00
#include <machine/stdarg.h>
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
Add support for the U4 PCI-Express bridge chipset used in late-generation Powermac G5 systems. MSI and several other things are not presently supported. The U3/U4 internal device support portions of this change were contributed by Andreas Tobler. MFC after: 1 week
2010-05-16 15:18:25 +00:00
#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
- Add constants for HT PCI capability registers including the various subtypes of HT capabilities. - Add constants for the MSI mapping window HT PCI capability. - On i386 and amd64, enable the MSI mapping window on any HT bridges we encounter and report any non-standard mapping window addresses.
2006-12-12 19:33:25 +00:00
#include <machine/intr_machdep.h>
#endif
Encapsulate the old PCI compatability support and APIs completely under "options COMPAT_OLDPCI". This option already existed, but now also tidies up the declarations in #include <pci/pci*.h>. It is amazing how much stuff was using the old pre-FreeBSD 3.x names and going silently undetected.
2000-05-28 16:35:57 +00:00
#include <sys/pciio.h>
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pci_private.h>
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
Support for Enhanced Allocation in PCI On some platforms, BAR entries are hardcoded and must not be accessed using standard method. Add functionality to identify this situation and configure the bus based on Enhanced Allocation structure. Obtained from: Semihalf Sponsored by: Cavium Approved by: cognet (mentor) Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D5242
2016-03-02 09:54:58 +00:00
#ifdef PCI_IOV
#include <sys/nv.h>
#include <dev/pci/pci_iov_private.h>
#endif
Add missing XHCI early takeover code. The XHCI takeover code is supposed to disable the BIOS from using the XHCI controller after bootup. Approved by: re (kib) Reported by: Mike Tancsa MFC after: 1 week
2011-07-22 15:37:23 +00:00
#include <dev/usb/controller/xhcireg.h>
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
#include <dev/usb/controller/ehcireg.h>
#include <dev/usb/controller/ohcireg.h>
#include <dev/usb/controller/uhcireg.h>
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
#include "pcib_if.h"
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
#include "pci_if.h"
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
#define PCIR_IS_BIOS(cfg, reg) \
(((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
static int pci_has_quirk(uint32_t devid, int quirk);
Always read/write the full 64-bit value of 64-bit BARs. Specifically, when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
2009-03-05 15:33:04 +00:00
static pci_addr_t pci_mapbase(uint64_t mapreg);
static const char *pci_maptype(uint64_t mapreg);
static int pci_maprange(uint64_t mapreg);
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
static pci_addr_t pci_rombase(uint64_t mapreg);
static int pci_romsize(uint64_t testval);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
static void pci_fixancient(pcicfgregs *cfg);
Add an internal pci_printf() routine similar to device_printf() except that it prefixes the output with 'pci<domain>:<bus>:<device>:<function>: '.
2009-06-01 20:30:00 +00:00
static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
static int pci_porten(device_t dev);
static int pci_memen(device_t dev);
- Consolidate duplicated code for assigning interrupts to PCI devices via routing, etc. in a static pci_assign_interrupt() function. - Add a sledgehammer that allows the user to override the interrupt assignment of any PCI device via a tunable (e.g. "hw.pci0.7.INTB=5" would force any functions on the pci device in slot 7 of bus 0 that use B# to use IRQ 5). This should be used with great caution! Generally, if the interrupt routing in use provides specific tunables (such as hard-wiring the IRQ for a given $PIR or ACPI PCI link device), then those should be used instead. One instance where this tunable might be useful is if a box has an MPTable with duplicate entries for the same PCI device with different IRQs. MFC after: 1 week
2005-09-29 15:04:41 +00:00
static void pci_assign_interrupt(device_t bus, device_t dev,
int force_route);
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
static int pci_add_map(device_t bus, device_t dev, int reg,
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
struct resource_list *rl, int force, int prefetch);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
static int pci_probe(device_t dev);
- Make pci_load_vendor_data() static and do it during MOD_LOAD instead of when the first PCI bus attaches. - Create /dev/pci during MOD_LOAD as well. - Destroy /dev/pci during MOD_UNLOAD (not that you can kldunload pci, but might as well get the code right)
2002-09-04 03:13:16 +00:00
static void pci_load_vendor_data(void);
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
static int pci_describe_parse_line(char **ptr, int *vendor,
Minor whitespace changes to conform better to stlye(9) and reduce diffs with uncommitted changes I have in p4.
2003-12-24 02:01:22 +00:00
int *device, char **desc);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
static char *pci_describe_device(device_t dev);
static int pci_modevent(module_t mod, int what, void *arg);
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
Minor whitespace changes to conform better to stlye(9) and reduce diffs with uncommitted changes I have in p4.
2003-12-24 02:01:22 +00:00
pcicfgregs *cfg);
Rename pci_find_extcap() to pci_find_cap(). PCI now uses the term "extended capabilities" to refer to the new set of capability structures starting at offset 0x100 in config space for PCI-express devices. For now both function names will still work. I will merge this to older branches to ease driver portability, but 9.0 will ship with a new pci_find_extcap() function that locates extended capabilities instead. Reviewed by: imp MFC after: 1 week
2011-03-22 12:05:49 +00:00
static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
int reg, uint32_t *data);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
#if 0
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
int reg, uint32_t data);
#endif
static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
static void pci_mask_msix(device_t dev, u_int index);
static void pci_unmask_msix(device_t dev, u_int index);
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
static int pci_msi_blacklisted(void);
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
static int pci_msix_blacklisted(void);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
static void pci_resume_msi(device_t dev);
static void pci_resume_msix(device_t dev);
Virtualize pci_remap_msi_irq() call from general MSI code. It allows MSI (FSB interrupts) to be used by non-PCI devices, such as HPET.
2010-06-14 07:10:37 +00:00
static int pci_remap_intr_method(device_t bus, device_t dev,
u_int irq);
Add device location wiring to the pci bus. This allows one to specify, for example, that if there's an igb card in bus 12, slot 0, function 0, it should be assigned igb5. If there isn't, or there's one in a different slot, normal numbering rules apply (hinted units are skipped). Adding 'hint.igb.5.at="pci12:0:0"' or 'hint.igb.5.at="pci0:12:0:0"' to /boot/device.hints will accomplish this. The double quotes are important. The kernel only accepts the strings (in shell notation): pci$d:$b:$s:$f and pci$b:$s:$f where $d is the pci domain, $b is the pci bus number, $s is the slot number and $f is the function number. A string compare is done with the current device to avoid another string parser in the kernel. All numbers are unsigned decimal without leading zeros. Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D13546
2017-12-20 19:14:05 +00:00
static void pci_hint_device_unit(device_t acdev, device_t child,
const char *name, int *unitp);
Implement resets for PCI buses and PCIe bridges. For PCI device (i.e. child of a PCI bus), reset tries FLR if implemented and worked, and falls to power reset otherwise. For PCIe bus (child of a PCIe bridge or root port), reset disables PCIe link and then re-trains it, performing what is known as link-level reset. Reviewed by: imp (previous version), jhb (previous version) Sponsored by: Mellanox Technologies MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D19646
2019-04-05 19:25:26 +00:00
static int pci_reset_post(device_t dev, device_t child);
static int pci_reset_prepare(device_t dev, device_t child);
static int pci_reset_child(device_t dev, device_t child,
int flags);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
Re-commit r299467 having fixed the build: Add a new get_id interface to pci and pcib. This will allow us to both detect failures, and get different PCI IDs. For the former the interface returns an int to signal an error. The ID is returned at a uintptr_t * argument. For the latter there is a type argument that allows selecting the ID type. This only specifies a single type, however a MSI type will be added to handle the need to find the ID the hardware passes to the ARM GICv3 interrupt controller. A follow up commit will be made to remove pci_get_rid. Reviewed by: jhb, rstone (previous version) Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D6239
2016-05-16 09:15:50 +00:00
static int pci_get_id_method(device_t dev, device_t child,
enum pci_id_type type, uintptr_t *rid);
Add a method to get the PCI RID for a device. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 15:47:24 +00:00
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d,
int b, int s, int f, uint16_t vid, uint16_t did);
Refactor PCI device creation Refactor creation of PCI devices into helper methods that can be used by the VF creation code. Differential Revision: https://reviews.freebsd.org/D67 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:26 +00:00
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
static device_method_t pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, pci_probe),
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
DEVMETHOD(device_attach, pci_attach),
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
DEVMETHOD(device_detach, pci_detach),
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
DEVMETHOD(device_shutdown, bus_generic_shutdown),
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
DEVMETHOD(device_suspend, bus_generic_suspend),
Add pci_resume() to reestablish interrupt routing after suspend/resume. Especially after hibernation, interrupt routing went back to initial status on some machines.
2003-09-17 08:32:44 +00:00
DEVMETHOD(device_resume, pci_resume),
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
/* Bus interface */
DEVMETHOD(bus_print_child, pci_print_child),
DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
DEVMETHOD(bus_read_ivar, pci_read_ivar),
DEVMETHOD(bus_write_ivar, pci_write_ivar),
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
DEVMETHOD(bus_driver_added, pci_driver_added),
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
DEVMETHOD(bus_setup_intr, pci_setup_intr),
DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
Implement resets for PCI buses and PCIe bridges. For PCI device (i.e. child of a PCI bus), reset tries FLR if implemented and worked, and falls to power reset otherwise. For PCIe bus (child of a PCIe bridge or root port), reset disables PCIe link and then re-trains it, performing what is known as link-level reset. Reviewed by: imp (previous version), jhb (previous version) Sponsored by: Mellanox Technologies MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D19646
2019-04-05 19:25:26 +00:00
DEVMETHOD(bus_reset_prepare, pci_reset_prepare),
DEVMETHOD(bus_reset_post, pci_reset_post),
DEVMETHOD(bus_reset_child, pci_reset_child),
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag),
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
DEVMETHOD(bus_delete_resource, pci_delete_resource),
DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
Add implementations of BUS_ADJUST_RESOURCE() to the PCI bus driver, generic PCI-PCI bridge driver, x86 nexus driver, and x86 Host to PCI bridge drivers.
2011-05-02 14:13:12 +00:00
DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
Properly handle I/O windows in bridges with the ISA enable bit set. These beasts still exist unfortunately. More details can be found in other references, but the short version is that bridges with this bit set ignore I/O port ranges that alias to valid ISA I/O port ranges. In the driver this requires not allocating these alias regions from the parent device (so they are free to be acquired by ISA devices), and ensuring no child devices use resources from these alias regions. - Change the pcib_window structure to allow for an array of backing resources rather than a single resource and update the existing code to cope with this. Some of the coping requires using the saved base and limit values in pcib_window instead of using rman operations on the backing resource. - Add special handling for allocating and adjusting the I/O port window of an ISA-enabled bridge to only allocate the non-alias ranges and add those to the associated resource manager. - Reject I/O port allocations for a fixed request that conflicts with an ISA alias range. - Remove the "no prefected decode" verbose printf during boot. The absence of a "prefetched decode" line is sufficient. - Replace the "subtractively decoded bridge" verbose printf with a single printf that lists all the "special" decoding modes of a bridge: ISA, subtractive, and VGA. - Add a custom bus_release_resource() method to the PCI bus driver so that it can properly free resources for I/O windows of PCI-PCI bridges. (These resources are not stored in the bridge device's resource list.) PR: misc/179033 MFC after: 2 weeks
2013-07-18 15:17:11 +00:00
DEVMETHOD(bus_release_resource, pci_release_resource),
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
DEVMETHOD(bus_activate_resource, pci_activate_resource),
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
Convert pci_delete_child() to a bus_child_deleted() method. Instead of providing a wrapper around device_delete_child() that the PCI bus and child bus drivers must call explicitly, move the bulk of the logic from pci_delete_child() into a bus_child_deleted() method (pci_child_deleted()). This allows PCI devices to be safely deleted via device_delete_child(). - Add a bus_child_deleted method to the ACPI PCI bus which clears the device_t associated with the corresponding ACPI handle in addition to the normal PCI bus cleanup. - Change cardbus_detach_card to call device_delete_children() and move CardBus-specific delete logic into a new cardbus_child_deleted() method. - Use device_delete_child() instead of pci_delete_child() in the SRIOV code. - Add a bus_child_deleted method to the OpenFirmware PCI bus drivers which frees the OpenFirmware device info for each PCI device. Reviewed by: imp Tested on: amd64 (CardBus and PCI-e hotplug) Differential Revision: https://reviews.freebsd.org/D5831
2016-04-06 04:10:22 +00:00
DEVMETHOD(bus_child_deleted, pci_child_deleted),
Make detaching drivers from PCI devices more robust. While here, fix a bug where a PCI device would be powered down if it failed to probe, but not when its driver was detached (e.g. via kldunload). - Add a new helper method resource_list_release_active() which forcefully releases any active resources of a specified type from a resource list. - Add a bus_child_detached method for the PCI bus driver which forces any active resources to be released (and whines to the console if it finds any) and then powers the device down. - Call pci_child_detached() if we fail to probe a device when a driver is kldloaded. This isn't perfect but can avoid leaking resources from a probe() routine in the kldload case. Reviewed by: imp, brooks MFC after: 1 month
2013-06-27 20:21:54 +00:00
DEVMETHOD(bus_child_detached, pci_child_detached),
Move the pnp and location info into the common pci bus. Make all known pci busses implement this. Also minor comment smithing in cardbus. Fix copyright to this year with my name on it since I've been doing a lot to this file. Reviewed by: jhb
2003-02-17 21:20:35 +00:00
DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
Add device location wiring to the pci bus. This allows one to specify, for example, that if there's an igb card in bus 12, slot 0, function 0, it should be assigned igb5. If there isn't, or there's one in a different slot, normal numbering rules apply (hinted units are skipped). Adding 'hint.igb.5.at="pci12:0:0"' or 'hint.igb.5.at="pci0:12:0:0"' to /boot/device.hints will accomplish this. The double quotes are important. The kernel only accepts the strings (in shell notation): pci$d:$b:$s:$f and pci$b:$s:$f where $d is the pci domain, $b is the pci bus number, $s is the slot number and $f is the function number. A string compare is done with the current device to avoid another string parser in the kernel. All numbers are unsigned decimal without leading zeros. Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D13546
2017-12-20 19:14:05 +00:00
DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit),
Virtualize pci_remap_msi_irq() call from general MSI code. It allows MSI (FSB interrupts) to be used by non-PCI devices, such as HPET.
2010-06-14 07:10:37 +00:00
DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
DEVMETHOD(bus_suspend_child, pci_suspend_child),
DEVMETHOD(bus_resume_child, pci_resume_child),
Implement a PCI bus rescan method. Rescanning a PCI bus uses the following steps: - Fetch the current set of child devices and save it in the 'devlist' array. - Allocate a parallel array 'unchanged' initalized with NULL pointers. - Scan the bus checking each slot (and each function on slots with a multifunction device). - If a valid function is found, look for a matching device in the 'devlist' array. If a device is found, save the pointer in the 'unchanged' array. If a device is not found, add a new device. - After the scan has finished, walk the 'devlist' array deleting any devices that do not have a matching pointer in the 'unchanged' array. - Finally, fetch an updated set of child devices and explicitly attach any devices that are not present in the 'unchanged' array. This builds on the previous changes to move subclass data management into pci_alloc_devinfo(), pci_child_added(), and bus_child_deleted(). Subclasses of the PCI bus use custom rescan logic explicitly override the rescan method to disable rescans. Differential Revision: https://reviews.freebsd.org/D6018
2016-04-27 16:31:12 +00:00
DEVMETHOD(bus_rescan, pci_rescan_method),
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
/* PCI interface */
DEVMETHOD(pci_read_config, pci_read_config_method),
DEVMETHOD(pci_write_config, pci_write_config_method),
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
DEVMETHOD(pci_enable_io, pci_enable_io_method),
DEVMETHOD(pci_disable_io, pci_disable_io_method),
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
Add a new PCI interface method, assign_interrupt, to determine the interrupt to be used for a device. This is intended solely for internal use of PCI bus implementations, and exists so that PCI bus drivers implementing special interrupt assignment methods which require additional work at the bus level to work right can be easily derived from the generic driver (or any other one) without resorting to hacks. It will be used in the sparc64 ofw_pcibus driver, which will be committed shortly. Make use of this method in the generic implementation, and add it to the method table of bus drivers derived from the PCI one. Reviewed by: imp, -hackers
2003-07-01 14:08:33 +00:00
DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
DEVMETHOD(pci_find_cap, pci_find_cap_method),
Add PCI methods to iterate over the PCI capabilities VirtIO V1 provides configuration in multiple VENDOR capabilities so this allows all of the configuration to be discovered. Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D14325
2018-02-19 18:41:56 +00:00
DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method),
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
2005-12-20 19:57:47 +00:00
DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
Add PCI methods to iterate over the PCI capabilities VirtIO V1 provides configuration in multiple VENDOR capabilities so this allows all of the configuration to be discovered. Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D14325
2018-02-19 18:41:56 +00:00
DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method),
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
DEVMETHOD(pci_find_htcap, pci_find_htcap_method),
Add PCI methods to iterate over the PCI capabilities VirtIO V1 provides configuration in multiple VENDOR capabilities so this allows all of the configuration to be discovered. Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D14325
2018-02-19 18:41:56 +00:00
DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method),
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
DEVMETHOD(pci_enable_msi, pci_enable_msi_method),
DEVMETHOD(pci_enable_msix, pci_enable_msix_method),
DEVMETHOD(pci_disable_msi, pci_disable_msi_method),
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
DEVMETHOD(pci_release_msi, pci_release_msi_method),
DEVMETHOD(pci_msi_count, pci_msi_count_method),
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
DEVMETHOD(pci_msix_count, pci_msix_count_method),
Add accessor methods to fetch the BAR holding the MSI-X table and PBA. While here, explicitly note the requirement that the BAR(s) must be allocated prior to calling pci_alloc_msix(). Reviewed by: andrew, emaste MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D4688
2015-12-23 21:51:10 +00:00
DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method),
DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method),
Re-commit r299467 having fixed the build: Add a new get_id interface to pci and pcib. This will allow us to both detect failures, and get different PCI IDs. For the former the interface returns an int to signal an error. The ID is returned at a uintptr_t * argument. For the latter there is a type argument that allows selecting the ID type. This only specifies a single type, however a MSI type will be added to handle the need to find the ID the hardware passes to the ARM GICv3 interrupt controller. A follow up commit will be made to remove pci_get_rid. Reviewed by: jhb, rstone (previous version) Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D6239
2016-05-16 09:15:50 +00:00
DEVMETHOD(pci_get_id, pci_get_id_method),
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method),
pci: add a new pci_child_added newbus method. This is needed so when running under Xen the calls to pci_child_added can be intercepted and a custom Xen method can be used to register those devices with Xen. This should not include any functional change, since the Xen implementation will be added in a following patch and the native implementation is a noop. Sponsored by: Citrix Systems R&D Reviewed by: jhb dev/pci/pci.c: dev/pci/pci_if.m: dev/pci/pci_private.h: dev/pci/pcivar.h: - Add the pci_child_added newbus method.
2014-08-22 15:05:51 +00:00
DEVMETHOD(pci_child_added, pci_child_added_method),
Implement interface to create SR-IOV Virtual Functions Implement the interace to create SR-IOV Virtual Functions (VFs). When a driver registers that they support SR-IOV by calling pci_setup_iov(), the SR-IOV code creates a new node in /dev/iov for that device. An ioctl can be invoked on that device to create VFs and have the driver initialize them. At this point, allocating memory I/O windows (BARs) is not supported. Differential Revision: https://reviews.freebsd.org/D76 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:09 +00:00
#ifdef PCI_IOV
DEVMETHOD(pci_iov_attach, pci_iov_attach_method),
DEVMETHOD(pci_iov_detach, pci_iov_detach_method),
DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method),
#endif
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
- As it turns out, MSI-X is broken for at least LSI SAS1068E when passed through by VMware so blacklist their PCI-PCI bridge for MSI/MSI-X here. Note that besides currently there not being a quirk type that disables MSI-X only and there's no evidence that MSI doesn't work with the VMware pass-through, it's really questionable whether MSI generally works in that setup as VMware only mention three know working devices [1, p. 4]. Also not that this quirk entry currently doesn't affect the devices emulated by VMware in any way as these don't claim support MSI/MSI-X to begin with. [2] While at it, make the PCI quirk table const and static. - Remove some duplicated empty lines. - Use DEVMETHOD_END. PR: 163812, http://forums.freebsd.org/showthread.php?t=27899 [2] Reviewed by: jhb MFC after: 3 days
2012-02-14 00:18:35 +00:00
DEVMETHOD_END
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
};
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc));
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
Make the 'pci_devclass' pointer variable private (drivers really shouldn't share devclass pointers, a mistake I've encouraged in the past) and move the declaration of the pci_driver kobj class from cardbus.c to pci_private.h so that other drivers can inherit from pci_driver.
2006-01-20 22:00:50 +00:00
static devclass_t pci_devclass;
Sprinkle EARLY_DRIVER_MODULE around the tree Mark some buses as BUS_PASS_BUS, and some resources as BUS_PASS_RESOURCE. This also decouples some resource attachment orderings from being races by device tree ordering, instead relying on the bus pass to provide the ordering. This was originally intended to support multipass suspend/resume, but it's also needed on PowerMacs when using fdt, as the device tree seems to get created in reverse of the OFW tree. Reviewed by: nwhitehorn (long ago) Differential Revision: https://reviews.freebsd.org/D918
2018-12-04 04:55:49 +00:00
EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL,
BUS_PASS_BUS);
Add MODULE_VERSION.
2002-04-17 00:31:32 +00:00
MODULE_VERSION(pci, 1);
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
static char *pci_vendordata;
static size_t pci_vendordata_size;
Modified to use renamed get_pci_apic_irq() -> pci_apic_pin() function.
1997-06-25 20:56:29 +00:00
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
struct pci_quirk {
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint32_t devid; /* Vendor/device of the card */
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
int type;
Replace #define<space> with #define<tab> so the code is consistent with style(9) and avoids mixing the two formats.
2006-12-14 16:53:48 +00:00
#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
#define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
- Add a new PCI quirk to whitelist an old chipset that doesn't support PCI-express or PCI-X capabilities if we are running in a virtual machine. - Whitelist the Intel 82440 chipset used by QEMU. Tested by: jfv MFC after: 1 week
2010-10-22 11:42:02 +00:00
#define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
Add a PCI quirk to ignore PCI map registers from configuration space. For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base address as a memory BAR for SMBus controller depending on a PM register configuration. Before r231161 (and r232086, subsequent MFC to stable/9), it was not fatal but hpet(4) just failed to attach. Since we probe and attach HPET earlier than PCI devices now, it caused unfortunate hard lockup. With this patch, it does not hang any more and HPET works at the same time. Clean up some style nits while I am in the neighborhood. PR: kern/165647 Reviewed by: jhb MFC after: 3 days
2012-03-14 23:25:46 +00:00
#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
Oops, fix typo made in r272729.
2014-10-08 05:53:04 +00:00
#define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */
Work around BIOS quirks on HPE Proliant MicroServer Gen10 PR: 221350 Submitted by: Bob Bishop Reported by: Rafal Lukawiecki Reviewed by: jhb MFC after: 2 weeks
2018-12-17 07:09:46 +00:00
#define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
int arg1;
int arg2;
};
Remove duplicate const specifiers in many drivers (I hope I got all of them, please let me know if not). Most of these are of the form: static const struct bzzt_type { [...list of members...] } const bzzt_devs[] = { [...list of initializers...] }; The second const is unnecessary, as arrays cannot be modified anyway, and if the elements are const, the whole thing is const automatically (e.g. it is placed in .rodata). I have verified this does not change the binary output of a full kernel build (except for build timestamps embedded in the object files). Reviewed by: yongari, marius MFC after: 1 week
2012-11-05 19:16:27 +00:00
static const struct pci_quirk pci_quirks[] = {
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
Add support for the Intel 82443MX chipset PR: kern/33032 MFC after: 1 month
2001-12-21 01:28:59 +00:00
{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
The serverworks OSB4 pci->isa bridge has the same mapping register at offset 0x90 for the SMBus device as the PIIX4.
2001-03-15 06:51:45 +00:00
/* As does the Serverworks OSB4 (the SMBus mapping register) */
{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
Disable MSI for two ServerWorks chipsets. The first is based on a user report. The second is blacklisted in Linux.
2007-01-12 21:37:51 +00:00
/*
* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
* or the CMIC-SL (AKA ServerWorks GC_LE).
*/
{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
Disable MSI for the Intel E7501 chipset. Reported by: jdp
2006-12-14 19:59:29 +00:00
/*
Blacklist a few more Intel chipsets re: MSI based on user reports: E7500 and 855.
2007-01-12 21:30:25 +00:00
* MSI doesn't work on earlier Intel chipsets including
Disable MSI for the Intel 845 and 865 chipsets and update comment for E7210 to note it is the same devid as the 875 chipset.
2007-01-16 19:44:45 +00:00
* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
Disable MSI for the Intel E7501 chipset. Reported by: jdp
2006-12-14 19:59:29 +00:00
*/
Blacklist a few more Intel chipsets re: MSI based on user reports: E7500 and 855.
2007-01-12 21:30:25 +00:00
{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
Disable MSI for the Intel E7501 chipset. Reported by: jdp
2006-12-14 19:59:29 +00:00
{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
Disable MSI on the Intel E7505 chipset. It is reported broken on a Tyan S2665ANF motherboard. Reported by: "Eugene M. Kim" <blue at white lv>
2006-12-28 06:14:42 +00:00
{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
Disable MSI for the Intel 845 and 865 chipsets and update comment for E7210 to note it is the same devid as the 875 chipset.
2007-01-16 19:44:45 +00:00
{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
- Condense the comment for Intel chipset MSI blacklist entries. - Blacklist the E7210. PR: kern/105768 (2) Reported by: marcus (2)
2007-01-12 13:33:56 +00:00
{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
Blacklist a few more Intel chipsets re: MSI based on user reports: E7500 and 855.
2007-01-12 21:30:25 +00:00
{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
Disable MSI on the Intel E7505 chipset. It is reported broken on a Tyan S2665ANF motherboard. Reported by: "Eugene M. Kim" <blue at white lv>
2006-12-28 06:14:42 +00:00
- Add a new flag to the PCI-PCI driver to disable MSI on devices behind the bridge if it doesn't pass MSI messages up correctly. We set the flag in pcib_attach() if the device ID is disabled via a PCI quirk. - Disable MSI for devices behind the AMD 8131 HT-PCIX bridge. Linux has the same quirk. Tested by: no one despite repeated calls for testers
2007-01-13 04:57:37 +00:00
/*
* MSI doesn't work with devices behind the AMD 8131 HT-PCIX
* bridge.
*/
{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
- Add a new PCI quirk to whitelist an old chipset that doesn't support PCI-express or PCI-X capabilities if we are running in a virtual machine. - Whitelist the Intel 82440 chipset used by QEMU. Tested by: jfv MFC after: 1 week
2010-10-22 11:42:02 +00:00
/*
* Some virtualization environments emulate an older chipset
* but support MSI just fine. QEMU uses the Intel 82440.
*/
{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
Add a PCI quirk to ignore PCI map registers from configuration space. For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base address as a memory BAR for SMBus controller depending on a PM register configuration. Before r231161 (and r232086, subsequent MFC to stable/9), it was not fatal but hpet(4) just failed to attach. Since we probe and attach HPET earlier than PCI devices now, it caused unfortunate hard lockup. With this patch, it does not hang any more and HPET works at the same time. Clean up some style nits while I am in the neighborhood. PR: kern/165647 Reviewed by: jhb MFC after: 3 days
2012-03-14 23:25:46 +00:00
/*
* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
* controller depending on SoftPciRst register (PM_IO 0x55 [7]).
* It prevents us from attaching hpet(4) when the bit is unset.
* Note this quirk only affects SB600 revision A13 and earlier.
* For SB600 A21 and later, firmware must set the bit to hide it.
* For SB700 and later, it is unused and hardcoded to zero.
*/
{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
Add new quirk PCI_QUIRK_MSI_INTX_BUG to pci(4). QAC AR816x/E2200 controller has a silicon bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of command register is set. Reviewed by: jhb
2014-10-08 05:34:39 +00:00
/*
alc: Add Killer E2500 support Reviewed by: jhb, yongari MFC after: 1 week Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D9058
2017-01-16 03:03:47 +00:00
* Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have
* a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit
Add Killer E2400 Gigabit Ethernet support. It seems Killer E2200/E2400 has a BIOS misconfiguration or silicon bug which triggers DMA write errors when driver uses advertised maximum payload size. Force the maximum payload size to 128 bytes in DMA configuration. This change should fix occasional DMA write errors reported on Killer E2200. Tested by: <psy0nic@sys-tek.org>
2016-08-22 01:19:05 +00:00
* of the command register is set.
Add new quirk PCI_QUIRK_MSI_INTX_BUG to pci(4). QAC AR816x/E2200 controller has a silicon bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of command register is set. Reviewed by: jhb
2014-10-08 05:34:39 +00:00
*/
{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
Add Killer E2400 Gigabit Ethernet support. It seems Killer E2200/E2400 has a BIOS misconfiguration or silicon bug which triggers DMA write errors when driver uses advertised maximum payload size. Force the maximum payload size to 128 bytes in DMA configuration. This change should fix occasional DMA write errors reported on Killer E2200. Tested by: <psy0nic@sys-tek.org>
2016-08-22 01:19:05 +00:00
{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
alc: Add Killer E2500 support Reviewed by: jhb, yongari MFC after: 1 week Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D9058
2017-01-16 03:03:47 +00:00
{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
Add new quirk PCI_QUIRK_MSI_INTX_BUG to pci(4). QAC AR816x/E2200 controller has a silicon bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of command register is set. Reviewed by: jhb
2014-10-08 05:34:39 +00:00
{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
- Make PCI_QUIRK_MSI_INTX_BUG work by using the ID of the actual PCI device for the lookup. - For devices affected by PCI_QUIRK_MSI_INTX_BUG, ensure PCIM_CMD_INTxDIS is cleared when using MSI/MSI-X. - Employ PCI_QUIRK_MSI_INTX_BUG for BCM5714(S)/BCM5715(S)/BCM5780(S) rather than clearing PCIM_CMD_INTxDIS unconditionally for all devices in bge(4). MFC after: 3 days
2014-12-27 14:26:18 +00:00
/*
* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
* issue MSI interrupts with PCIM_CMD_INTxDIS set either.
*/
{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */
{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */
{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */
{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */
{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */
{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */
Work around BIOS quirks on HPE Proliant MicroServer Gen10 PR: 221350 Submitted by: Bob Bishop Reported by: Rafal Lukawiecki Reviewed by: jhb MFC after: 2 weeks
2018-12-17 07:09:46 +00:00
/*
* HPE Gen 10 VGA has a memory range that can't be allocated in the
* expected place.
*/
{ 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 },
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
{ 0 }
};
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
/* map register information */
Replace #define<space> with #define<tab> so the code is consistent with style(9) and avoids mixing the two formats.
2006-12-14 16:53:48 +00:00
#define PCI_MAPMEM 0x01 /* memory map */
#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
#define PCI_MAPPORT 0x04 /* port map */
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
Don't put variable declarations in header files, put prototypes. 'pci_devq' provides useful information now.
2001-12-19 08:49:11 +00:00
struct devlist pci_devq;
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint32_t pci_generation;
uint32_t pci_numdevs = 0;
Partially revert previous change. Drop the quirk to disable MSI for HT chipsets that do not have an HT slave at 0:0:0:0. The Linux quirk is actually specific to Nvidia chipsets and the check I had added was in the wrong place. Prodded by: nathanw
2011-03-18 14:06:12 +00:00
static int pcie_chipset, pcix_chipset;
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
2002-07-26 07:58:16 +00:00
/* sysctl vars */
Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (5 of many) r357614 added CTLFLAG_NEEDGIANT to make it easier to find nodes that are still not MPSAFE (or already are but aren’t properly marked). Use it in preparation for a general review of all nodes. This is non-functional change that adds annotations to SYSCTL_NODE and SYSCTL_PROC nodes using one of the soon-to-be-required flags. Reviewed by: imp, kib Approved by: kib (mentor) Differential Revision: https://reviews.freebsd.org/D23633
2020-02-16 17:11:54 +00:00
SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
"PCI bus tuning parameters");
Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
2002-07-26 07:58:16 +00:00
ooops. I disabled pci_enable_io_modes not pci_do_powerstate in the last commit. That was in error. Noticed by: sos
2004-04-16 15:01:54 +00:00
static int pci_enable_io_modes = 1;
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN,
ooops. I disabled pci_enable_io_modes not pci_do_powerstate in the last commit. That was in error. Noticed by: sos
2004-04-16 15:01:54 +00:00
&pci_enable_io_modes, 1,
Remove embedded newlines from sysctl variable descriptions PR: 112556 Submitted by: Willem Jan Withagen <wjw@digiware.nl> (earlier version) Reported by: Willem Jan Withagen, ighighi@gmail.com MFC after: 3 weeks Sponsored by: Spectra Logic Corp
2017-10-09 22:27:38 +00:00
"Enable I/O and memory bits in the config register. Some BIOSes do not"
" enable these bits correctly. We'd like to do this all the time, but"
" there are some peripherals that this causes problems with.");
Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
2002-07-26 07:58:16 +00:00
Enable PCI BAR reallocation by default. When pci_realloc_bars was first added, the intention was to eventually enable it by default, but it was left disabled to preserve existing behavior. The setting is pretty conservative in that it does not attempt to allocate resources for BARs that the BIOS/firmware leaves disabled. It only attempts to reallocate resources for a BAR that the firmware programmed during boot but that conflicts with another resource during the kernel's device scan. PR 221350 is an example of a machine that this knob fixes. Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D18965
2019-02-11 20:47:09 +00:00
static int pci_do_realloc_bars = 1;
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN,
Revision 233677 broke certain machines. Specifically, if the firmware/BIOS assigned conflicting ranges to BARs then leaving the BARs alone could result in one device stealing mmio accesses intended to go to a second device. Prior to 233677 the PCI bus driver attempted to handle this case by clearing the BAR to 0 depending on BARs based at 0 not decoding (which is not guaranteed to be true). Now when a conflicting BAR is detected the following steps are taken: 1) If hw.pci.realloc_bars (a new tunable) is enabled (default is enabled), then ignore the current BAR setting from the firmware and attempt to allocate a fresh resource range for the BAR. 2) If 1) failed (or was disabled), disable decoding for the relevant BAR type (e.g. disable mem decoding for a memory BAR) and emit a warning if booting verbose. Tested by: Alex Keda <admin@lissyara.su> MFC after: 1 week
2013-05-09 19:24:50 +00:00
&pci_do_realloc_bars, 0,
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
"Attempt to allocate a new range for any BARs whose original "
"firmware-assigned ranges fail to allocate during the initial device scan.");
Revision 233677 broke certain machines. Specifically, if the firmware/BIOS assigned conflicting ranges to BARs then leaving the BARs alone could result in one device stealing mmio accesses intended to go to a second device. Prior to 233677 the PCI bus driver attempted to handle this case by clearing the BAR to 0 depending on BARs based at 0 not decoding (which is not guaranteed to be true). Now when a conflicting BAR is detected the following steps are taken: 1) If hw.pci.realloc_bars (a new tunable) is enabled (default is enabled), then ignore the current BAR setting from the firmware and attempt to allocate a fresh resource range for the BAR. 2) If 1) failed (or was disabled), disable decoding for the relevant BAR type (e.g. disable mem decoding for a memory BAR) and emit a warning if booting verbose. Tested by: Alex Keda <admin@lissyara.su> MFC after: 1 week
2013-05-09 19:24:50 +00:00
Split power state control into two variables. hw.pci.do_powerstate has been removed. It has been replaced by hw.pci.do_power_nodriver and hw.pci.do_power_resume. The former defaults to 0 while the latter defaults to 1. When do_powerstate was set to 0, it broke suspend/resume for a lot of people as an unintended consequence. This change will only affect the areas that were intended to affect. This change will have no effect on servers, but will help laptops quite a bit. MFC After: 3 days.
2005-09-21 19:47:00 +00:00
static int pci_do_power_nodriver = 0;
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN,
Split power state control into two variables. hw.pci.do_powerstate has been removed. It has been replaced by hw.pci.do_power_nodriver and hw.pci.do_power_resume. The former defaults to 0 while the latter defaults to 1. When do_powerstate was set to 0, it broke suspend/resume for a lot of people as an unintended consequence. This change will only affect the areas that were intended to affect. This change will have no effect on servers, but will help laptops quite a bit. MFC After: 3 days.
2005-09-21 19:47:00 +00:00
&pci_do_power_nodriver, 0,
Remove embedded newlines from sysctl variable descriptions PR: 112556 Submitted by: Willem Jan Withagen <wjw@digiware.nl> (earlier version) Reported by: Willem Jan Withagen, ighighi@gmail.com MFC after: 3 weeks Sponsored by: Spectra Logic Corp
2017-10-09 22:27:38 +00:00
"Place a function into D3 state when no driver attaches to it. 0 means"
" disable. 1 means conservatively place devices into D3 state. 2 means"
" aggressively place devices into D3 state. 3 means put absolutely"
" everything in D3 state.");
Split power state control into two variables. hw.pci.do_powerstate has been removed. It has been replaced by hw.pci.do_power_nodriver and hw.pci.do_power_resume. The former defaults to 0 while the latter defaults to 1. When do_powerstate was set to 0, it broke suspend/resume for a lot of people as an unintended consequence. This change will only affect the areas that were intended to affect. This change will have no effect on servers, but will help laptops quite a bit. MFC After: 3 days.
2005-09-21 19:47:00 +00:00
Implement a rudimentary suspend/resume methods for PCI P2P bridge. Reviewed by: jhb, imp
2009-12-10 01:01:53 +00:00
int pci_do_power_resume = 1;
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN,
Split power state control into two variables. hw.pci.do_powerstate has been removed. It has been replaced by hw.pci.do_power_nodriver and hw.pci.do_power_resume. The former defaults to 0 while the latter defaults to 1. When do_powerstate was set to 0, it broke suspend/resume for a lot of people as an unintended consequence. This change will only affect the areas that were intended to affect. This change will have no effect on servers, but will help laptops quite a bit. MFC After: 3 days.
2005-09-21 19:47:00 +00:00
&pci_do_power_resume, 1,
"Transition from D3 -> D0 on resume.");
Add system tunable to turn off power state changes. Default to off until we get the resource allocation stuff hammered out. Fix and off by one error that caused unnecessary filtering of valid BARs for only 4 bytes than ICH3 and other PCI IDE controllers have. Andrew Gallatin submitted this, although it doesn't solve the problems ICH3 controllers have with the new code, it does restore the former resource list on the probe line.
2004-04-11 07:02:49 +00:00
Introduce a new tunable 'hw.pci.do_power_suspend'. This tunable lets you avoid PCI power state transition from D0 to D3 for suspending case. Default is 1 or enabled.
2010-10-20 16:47:09 +00:00
int pci_do_power_suspend = 1;
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN,
Introduce a new tunable 'hw.pci.do_power_suspend'. This tunable lets you avoid PCI power state transition from D0 to D3 for suspending case. Default is 1 or enabled.
2010-10-20 16:47:09 +00:00
&pci_do_power_suspend, 1,
"Transition from D0 -> D3 on suspend.");
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
static int pci_do_msi = 1;
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1,
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
"Enable support for MSI interrupts");
static int pci_do_msix = 1;
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1,
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
"Enable support for MSI-X interrupts");
Add MSIX rewrite table quirk for use with VMs. This patch solves IRQ generation problems using the mlx5en(4) driver with xenserver v6.5.0 in SRIOV and PCI-passthrough modes. Until further the hw.pci.msix_rewrite_table quirk must be set manually in /boot/loader.conf . Reviewed by: jhb @ Sponsored by: Mellanox Technologies MFC after: 2 weeks
2016-12-30 08:37:30 +00:00
static int pci_msix_rewrite_table = 0;
SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN,
&pci_msix_rewrite_table, 0,
"Rewrite entire MSI-X table when updating MSI-X entries");
Add a first pass at a way to blacklist MSI on systems where it doesn't work: - A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table. - A new pci_msi_device_blacklisted() determines if a passed in device matches an MSI quirk in the quirk table. This can be overridden (all quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0. - A global blacklist check is performed in the MI PCI bus code by checking to see if the device at 0:0:0 is blacklisted. Tested by: jdp
2006-12-14 19:57:06 +00:00
static int pci_honor_msi_blacklist = 1;
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN,
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
&pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
Add a first pass at a way to blacklist MSI on systems where it doesn't work: - A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table. - A new pci_msi_device_blacklisted() determines if a passed in device matches an MSI quirk in the quirk table. This can be overridden (all quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0. - A global blacklist check is performed in the MI PCI bus code by checking to see if the device at 0:0:0 is blacklisted. Tested by: jdp
2006-12-14 19:57:06 +00:00
BIOSes, buggy or otherwise, are i386 or amd64 specific. Have the early USB takeover enabled for i386 and amd64 by default. This also avoids a panic on PowerPC where the resource isn't released properly and we find a busy resource when the USB host controller wants to allocate it...
2009-10-23 22:53:01 +00:00
#if defined(__i386__) || defined(__amd64__)
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
static int pci_usb_takeover = 1;
BIOSes, buggy or otherwise, are i386 or amd64 specific. Have the early USB takeover enabled for i386 and amd64 by default. This also avoids a panic on PowerPC where the resource isn't released properly and we find a busy resource when the USB host controller wants to allocate it...
2009-10-23 22:53:01 +00:00
#else
static int pci_usb_takeover = 0;
#endif
Minor whitespace and style fixes.
2011-06-21 19:31:31 +00:00
SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN,
Remove embedded newlines from sysctl variable descriptions PR: 112556 Submitted by: Willem Jan Withagen <wjw@digiware.nl> (earlier version) Reported by: Willem Jan Withagen, ighighi@gmail.com MFC after: 3 weeks Sponsored by: Spectra Logic Corp
2017-10-09 22:27:38 +00:00
&pci_usb_takeover, 1,
"Enable early takeover of USB controllers. Disable this if you depend on"
" BIOS emulation of USB devices, that is you use USB devices (like"
" keyboard or mouse) but do not load USB drivers");
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
Add two tunables to ignore certain firmware-assigned resources. These are mostly useful for debugging. - hw.pci.clear_bars ignores all firmware-assigned ranges for BARs when set. - hw.pci.clear_pcib ignores all firmware-assigned ranges for PCI-PCI bridge I/O windows when set. MFC after: 1 week
2014-02-05 20:52:12 +00:00
static int pci_clear_bars;
SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
"Ignore firmware-assigned resources for BARs.");
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
static int pci_clear_buses;
SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0,
"Ignore firmware-assigned bus numbers.");
#endif
Add support for PCIe ARI PCIe Alternate RID Interpretation (ARI) is an optional feature that allows devices to have up to 256 different functions. It is implemented by always setting the PCI slot number to 0 and re-purposing the 5 bits used to encode the slot number to instead contain the function number. Combined with the original 3 bits allocated for the function number, this allows for 256 functions. This is enabled by default, but it's expected to be a no-op on currently supported hardware. It's a prerequisite for supporting PCI SR-IOV, and I want the ARI support to go in early to help shake out any bugs in it. ARI can be disabled by setting the tunable hw.pci.enable_ari=0. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 16:02:02 +00:00
static int pci_enable_ari = 1;
SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari,
0, "Enable support for PCIe Alternative RID Interpretation");
Add mostly dummy hw.pci.enable_aspm tunable. The only thing this tunable enables now is reporting to ACPI _OSC that Active State Power Management and Clock Power Management Capability are "supported" by the OS. I've found that at least some Supermicro server boards do not allow OS to support native PCIe hot-plug unless it reports those capabilities. After spending significant time in PCIe specs I have found very little motivation for that, and none of it applies to those motherboards, not enabling ASPM themselves. So unless OS explicitly wants to save power, I see nothing for it to do there actually. I guess it may get sense to support ASPM when we get Thunderbolt support. Otherwise I have no system with PCIe hot-plug where power saving matters. It would be nice to enable this by default, but I worry that it affect power saving of some laptops, even though I haven't noticed that myself.
2020-06-26 19:55:11 +00:00
int pci_enable_aspm;
SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm,
0, "Enable support for PCIe Active State Power Management");
Rudimentary AER reading code for ddb(4). This is very primitive code to inspect the PCI error state and AER error state, dump the log and clear errors, from ddb. pci_print_faulted_dev() is made external to allow calling it from other places. It was called from NMI handler but this chunk is not included. Also there is a tunable-controlled code to clear AER on device attach, disabled by default. All this code was useful to me when I debugged ACPI_DMAR failures (not faults) long time ago. Reviewed by: cem, imp (previous version) Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D7813
2018-08-18 20:35:19 +00:00
static int pci_clear_aer_on_attach = 0;
SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN,
&pci_clear_aer_on_attach, 0,
"Clear port and device AER state on driver attach");
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
static int
pci_has_quirk(uint32_t devid, int quirk)
{
const struct pci_quirk *q;
for (q = &pci_quirks[0]; q->devid; q++) {
if (q->devid == devid && q->type == quirk)
return (1);
}
return (0);
}
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
/* Find a device_t by bus/slot/function in domain 0 */
Implement 2 small helper functions: pci_find_bsf() - Find a device_t by bus/slot/function. pci_find_device() - Find a device_t by vendor/device ID.
2002-01-10 00:56:02 +00:00
device_t
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
{
return (pci_find_dbsf(0, bus, slot, func));
}
/* Find a device_t by domain/bus/slot/function */
device_t
pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
Implement 2 small helper functions: pci_find_bsf() - Find a device_t by bus/slot/function. pci_find_device() - Find a device_t by vendor/device ID.
2002-01-10 00:56:02 +00:00
{
Push Giant down one layer The /dev/pci device doesn't need GIANT, per se. However, one routine that it calls, pci_find_dbsf implicitly does. It walks a list that can change when PCI scans a new bus. With hotplug, this means we could have a race with that scanning. To prevent that, take out Giant around scanning the list. However, given that we have places in the tree that drop giant, if held when we call into them, the whole use of Giant to protect newbus may be less effective that we desire, so add a comment about why we're talking it out, and we'll address the issue when we lock newbus with something other than Giant.
2019-11-23 23:43:52 +00:00
struct pci_devinfo *dinfo = NULL;
Implement 2 small helper functions: pci_find_bsf() - Find a device_t by bus/slot/function. pci_find_device() - Find a device_t by vendor/device ID.
2002-01-10 00:56:02 +00:00
STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
if ((dinfo->cfg.domain == domain) &&
(dinfo->cfg.bus == bus) &&
Implement 2 small helper functions: pci_find_bsf() - Find a device_t by bus/slot/function. pci_find_device() - Find a device_t by vendor/device ID.
2002-01-10 00:56:02 +00:00
(dinfo->cfg.slot == slot) &&
(dinfo->cfg.func == func)) {
Push Giant down one layer The /dev/pci device doesn't need GIANT, per se. However, one routine that it calls, pci_find_dbsf implicitly does. It walks a list that can change when PCI scans a new bus. With hotplug, this means we could have a race with that scanning. To prevent that, take out Giant around scanning the list. However, given that we have places in the tree that drop giant, if held when we call into them, the whole use of Giant to protect newbus may be less effective that we desire, so add a comment about why we're talking it out, and we'll address the issue when we lock newbus with something other than Giant.
2019-11-23 23:43:52 +00:00
break;
Implement 2 small helper functions: pci_find_bsf() - Find a device_t by bus/slot/function. pci_find_device() - Find a device_t by vendor/device ID.
2002-01-10 00:56:02 +00:00
}
}
Push Giant down one layer The /dev/pci device doesn't need GIANT, per se. However, one routine that it calls, pci_find_dbsf implicitly does. It walks a list that can change when PCI scans a new bus. With hotplug, this means we could have a race with that scanning. To prevent that, take out Giant around scanning the list. However, given that we have places in the tree that drop giant, if held when we call into them, the whole use of Giant to protect newbus may be less effective that we desire, so add a comment about why we're talking it out, and we'll address the issue when we lock newbus with something other than Giant.
2019-11-23 23:43:52 +00:00
return (dinfo != NULL ? dinfo->cfg.dev : NULL);
Implement 2 small helper functions: pci_find_bsf() - Find a device_t by bus/slot/function. pci_find_device() - Find a device_t by vendor/device ID.
2002-01-10 00:56:02 +00:00
}
/* Find a device_t by vendor/device ID */
device_t
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
pci_find_device(uint16_t vendor, uint16_t device)
Implement 2 small helper functions: pci_find_bsf() - Find a device_t by bus/slot/function. pci_find_device() - Find a device_t by vendor/device ID.
2002-01-10 00:56:02 +00:00
{
struct pci_devinfo *dinfo;
STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
if ((dinfo->cfg.vendor == vendor) &&
(dinfo->cfg.device == device)) {
return (dinfo->cfg.dev);
}
}
return (NULL);
}
Implement pci_find_class(9), the function to find a pci device by its class. Sponsored by: The FreeBSD Foundation Reviewed by: jhb MFC after: 1 week
2011-07-09 14:30:13 +00:00
device_t
pci_find_class(uint8_t class, uint8_t subclass)
{
struct pci_devinfo *dinfo;
STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
if (dinfo->cfg.baseclass == class &&
dinfo->cfg.subclass == subclass) {
return (dinfo->cfg.dev);
}
}
return (NULL);
}
Add an internal pci_printf() routine similar to device_printf() except that it prefixes the output with 'pci<domain>:<bus>:<device>:<function>: '.
2009-06-01 20:30:00 +00:00
static int
pci_printf(pcicfgregs *cfg, const char *fmt, ...)
{
va_list ap;
int retval;
retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
cfg->func);
va_start(ap, fmt);
retval += vprintf(fmt, ap);
va_end(ap);
return (retval);
}
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
/* return base address of memory or port map */
Submitted by: Wolfgang Stanglmeier <wolf@dentaro.GUN.de> Bug fixed, that caused system hang on first interrupt on some motherboards. New version of PCI bus configuration code, now supports dynamic interrupt configuration (using BIOS supplied values). NCR SCSI and DEC Ethernet driver patched to use this feature. *** Remove PCI IRQ specifications from your kernel config file ! ***
1994-10-12 02:33:23 +00:00
Always read/write the full 64-bit value of 64-bit BARs. Specifically, when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
2009-03-05 15:33:04 +00:00
static pci_addr_t
pci_mapbase(uint64_t mapreg)
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
{
Add constants for the fields in a BAR. Also, add two new macros PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR is for an IO or memory BAR, respectively. Reviewed by: imp
2007-03-31 21:39:02 +00:00
if (PCI_BAR_MEM(mapreg))
return (mapreg & PCIM_BAR_MEM_BASE);
else
return (mapreg & PCIM_BAR_IO_BASE);
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
}
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
/* return map type of memory or port map */
Update PCI bus code from my current sources: - always use pci_conf_read() and pci_conf_write(). (This is required to simulate non-existant devices in my system for PCI bridge code tests.) - reorder some functions (put the main functions at the end). - correct off by one bug in the code dealing with unitialized PCI to PCI bridge chips. (Bug found by ASAMI Satoshi.) - print function number for multi-function devices.
1996-04-14 20:14:36 +00:00
Add constants for the fields in a BAR. Also, add two new macros PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR is for an IO or memory BAR, respectively. Reviewed by: imp
2007-03-31 21:39:02 +00:00
static const char *
Always read/write the full 64-bit value of 64-bit BARs. Specifically, when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
2009-03-05 15:33:04 +00:00
pci_maptype(uint64_t mapreg)
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
{
Add constants for the fields in a BAR. Also, add two new macros PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR is for an IO or memory BAR, respectively. Reviewed by: imp
2007-03-31 21:39:02 +00:00
if (PCI_BAR_IO(mapreg))
return ("I/O Port");
if (mapreg & PCIM_BAR_MEM_PREFETCH)
return ("Prefetchable Memory");
return ("Memory");
Add PCI LKM support.
1997-01-21 23:23:40 +00:00
}
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
/* return log2 of map size decoded for memory or port map */
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
int
Always read/write the full 64-bit value of 64-bit BARs. Specifically, when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
2009-03-05 15:33:04 +00:00
pci_mapsize(uint64_t testval)
Add heuristic to detect multi-function devices that don't announce this feature in the header type register, though it is required by the PCI spec. This should correctly probe both functions of the Intel 82371FB chip, without the need for a special case based on the device ID.
1996-01-30 01:14:29 +00:00
{
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
int ln2size;
Add heuristic to detect multi-function devices that don't announce this feature in the header type register, though it is required by the PCI spec. This should correctly probe both functions of the Intel 82371FB chip, without the need for a special case based on the device ID.
1996-01-30 01:14:29 +00:00
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
testval = pci_mapbase(testval);
Two minor changes to the code that builds the pci map array: 1) Stop at the first map register that contains a zero value. 2) When testing for the map size work up from low values, since this works around a bug in some BusLogic SCSI card, which has the 16 upper port base address bits hardwired to zero. The config register dump printed in the bootverbose case has been slightly rearranged.
1997-05-28 10:01:03 +00:00
ln2size = 0;
if (testval != 0) {
while ((testval & 1) == 0)
{
ln2size++;
testval >>= 1;
}
Make mapping messages depend on bootverbose flag. Add PCI subclass to unknown device message.
1995-09-07 15:20:53 +00:00
}
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
return (ln2size);
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
}
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
/* return base address of device ROM */
static pci_addr_t
pci_rombase(uint64_t mapreg)
{
return (mapreg & PCIM_BIOS_ADDR_MASK);
}
/* return log2 of map size decided for device ROM */
static int
pci_romsize(uint64_t testval)
{
int ln2size;
testval = pci_rombase(testval);
ln2size = 0;
if (testval != 0) {
while ((testval & 1) == 0)
{
ln2size++;
testval >>= 1;
}
}
return (ln2size);
}
drop a bunch of white space at end of lines and end of files... -x -wb apparently doesn't hide end of file white space changes.. This is to reduce the amount of diff for my PCIe HP changes..
2015-10-18 08:13:51 +00:00
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
/* return log2 of address range supported by map register */
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
static int
Always read/write the full 64-bit value of 64-bit BARs. Specifically, when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
2009-03-05 15:33:04 +00:00
pci_maprange(uint64_t mapreg)
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
{
int ln2range = 0;
Add constants for the fields in a BAR. Also, add two new macros PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR is for an IO or memory BAR, respectively. Reviewed by: imp
2007-03-31 21:39:02 +00:00
if (PCI_BAR_IO(mapreg))
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
ln2range = 32;
Add constants for the fields in a BAR. Also, add two new macros PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR is for an IO or memory BAR, respectively. Reviewed by: imp
2007-03-31 21:39:02 +00:00
else
switch (mapreg & PCIM_BAR_MEM_TYPE) {
case PCIM_BAR_MEM_32:
ln2range = 32;
break;
case PCIM_BAR_MEM_1MB:
ln2range = 20;
break;
case PCIM_BAR_MEM_64:
ln2range = 64;
break;
}
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
return (ln2range);
Reapplied all of Stefan's changes. What a mess - the files were modified and moved at the same time. This made it *very* difficult to fix the revision log lossage that happend when the files were moved. SIGH.
1995-02-02 13:12:18 +00:00
}
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
Add PCI LKM support.
1997-01-21 23:23:40 +00:00
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
static void
pci_fixancient(pcicfgregs *cfg)
Add PCI LKM support.
1997-01-21 23:23:40 +00:00
{
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
return;
Add PCI LKM support.
1997-01-21 23:23:40 +00:00
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
/* PCI to PCI bridges use header type 1 */
Use "baseclass" instead of "class" for storing the contents of PCI register 0xB so that C++ programs can use the PCI conf interface.
1998-08-13 19:12:20 +00:00
if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
Add PCI LKM support.
1997-01-21 23:23:40 +00:00
}
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
/* extract header type specific config data */
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
These don't need to be semi-public after all.
2003-02-17 19:47:02 +00:00
static void
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
{
Replace #define<space> with #define<tab> so the code is consistent with style(9) and avoids mixing the two formats.
2006-12-14 16:53:48 +00:00
#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
switch (cfg->hdrtype & PCIM_HDRTYPE) {
case PCIM_HDRTYPE_NORMAL:
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
The minimim grant and maximum latency PCI config registers are only valid for type 0 devices, not type 1 or 2 bridges. Don't read them for bridge devices during bus scans and return an error when attempting to read them as ivars for bridge devices.
2015-04-22 21:41:59 +00:00
cfg->mingnt = REG(PCIR_MINGNT, 1);
cfg->maxlat = REG(PCIR_MAXLAT, 1);
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
cfg->nummaps = PCI_MAXMAPS_0;
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
break;
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
case PCIM_HDRTYPE_BRIDGE:
Update the pci_cfg_save/restore routines to operate on bridge devices (type 1 and type 2) as well as leaf devices (type 0). In particular, this allows the existing PCI bus logic to save and restore capability registers such as MSI and PCI-express work for bridge devices rather than requiring that code to be duplicated in bridge drivers. It also means that bridge drivers no longer need to save and restore basic registers such as the PCI command register or BARs nor manage powerstates for the bridge device. While here, pci_setup_secbus() has been changed to initialize the 'sec' and 'sub' fields in the 'secbus' structure instead of requiring the pcib and pccbb drivers to do this in the NEW_PCIB + PCI_RES_BUS case. Differential Revision: https://reviews.freebsd.org/D2240 Reviewed by: imp, jmg MFC after: 2 weeks
2015-04-22 22:02:27 +00:00
cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1);
cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1);
cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1);
cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1);
cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2);
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
cfg->nummaps = PCI_MAXMAPS_1;
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
break;
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
case PCIM_HDRTYPE_CARDBUS:
Update the pci_cfg_save/restore routines to operate on bridge devices (type 1 and type 2) as well as leaf devices (type 0). In particular, this allows the existing PCI bus logic to save and restore capability registers such as MSI and PCI-express work for bridge devices rather than requiring that code to be duplicated in bridge drivers. It also means that bridge drivers no longer need to save and restore basic registers such as the PCI command register or BARs nor manage powerstates for the bridge device. While here, pci_setup_secbus() has been changed to initialize the 'sec' and 'sub' fields in the 'secbus' structure instead of requiring the pcib and pccbb drivers to do this in the NEW_PCIB + PCI_RES_BUS case. Differential Revision: https://reviews.freebsd.org/D2240 Reviewed by: imp, jmg MFC after: 2 weeks
2015-04-22 22:02:27 +00:00
cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1);
cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1);
cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1);
cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1);
cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2);
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
cfg->nummaps = PCI_MAXMAPS_2;
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
break;
Make mapping messages depend on bootverbose flag. Add PCI subclass to unknown device message.
1995-09-07 15:20:53 +00:00
}
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
#undef REG
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
}
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
/* read configuration header into pcicfgregs structure */
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
struct pci_devinfo *
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f)
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
{
Replace #define<space> with #define<tab> so the code is consistent with style(9) and avoids mixing the two formats.
2006-12-14 16:53:48 +00:00
#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
Refactor PCI device creation Refactor creation of PCI devices into helper methods that can be used by the VF creation code. Differential Revision: https://reviews.freebsd.org/D67 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:26 +00:00
uint16_t vid, did;
vid = REG(PCIR_VENDOR, 2);
did = REG(PCIR_DEVICE, 2);
if (vid != 0xffff)
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did));
Refactor PCI device creation Refactor creation of PCI devices into helper methods that can be used by the VF creation code. Differential Revision: https://reviews.freebsd.org/D67 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:26 +00:00
return (NULL);
}
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
struct pci_devinfo *
pci_alloc_devinfo_method(device_t dev)
{
return (malloc(sizeof(struct pci_devinfo), M_DEVBUF,
M_WAITOK | M_ZERO));
}
Refactor PCI device creation Refactor creation of PCI devices into helper methods that can be used by the VF creation code. Differential Revision: https://reviews.freebsd.org/D67 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:26 +00:00
static struct pci_devinfo *
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f,
uint16_t vid, uint16_t did)
Refactor PCI device creation Refactor creation of PCI devices into helper methods that can be used by the VF creation code. Differential Revision: https://reviews.freebsd.org/D67 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:26 +00:00
{
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
struct pci_devinfo *devlist_entry;
Refactor PCI device creation Refactor creation of PCI devices into helper methods that can be used by the VF creation code. Differential Revision: https://reviews.freebsd.org/D67 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:26 +00:00
pcicfgregs *cfg;
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
devlist_entry = PCI_ALLOC_DEVINFO(bus);
Refactor PCI device creation Refactor creation of PCI devices into helper methods that can be used by the VF creation code. Differential Revision: https://reviews.freebsd.org/D67 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:26 +00:00
cfg = &devlist_entry->cfg;
cfg->domain = d;
cfg->bus = b;
cfg->slot = s;
cfg->func = f;
cfg->vendor = vid;
cfg->device = did;
cfg->cmdreg = REG(PCIR_COMMAND, 2);
cfg->statreg = REG(PCIR_STATUS, 2);
cfg->baseclass = REG(PCIR_CLASS, 1);
cfg->subclass = REG(PCIR_SUBCLASS, 1);
cfg->progif = REG(PCIR_PROGIF, 1);
cfg->revid = REG(PCIR_REVID, 1);
cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
cfg->lattimer = REG(PCIR_LATTIMER, 1);
cfg->intpin = REG(PCIR_INTPIN, 1);
cfg->intline = REG(PCIR_INTLINE, 1);
cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
cfg->hdrtype &= ~PCIM_MFDEV;
STAILQ_INIT(&cfg->maps);
Implement interface to create SR-IOV Virtual Functions Implement the interace to create SR-IOV Virtual Functions (VFs). When a driver registers that they support SR-IOV by calling pci_setup_iov(), the SR-IOV code creates a new node in /dev/iov for that device. An ioctl can be invoked on that device to create VFs and have the driver initialize them. At this point, allocating memory I/O windows (BARs) is not supported. Differential Revision: https://reviews.freebsd.org/D76 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:09 +00:00
cfg->iov = NULL;
Refactor PCI device creation Refactor creation of PCI devices into helper methods that can be used by the VF creation code. Differential Revision: https://reviews.freebsd.org/D67 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:26 +00:00
pci_fixancient(cfg);
pci_hdrtypedata(pcib, b, s, f, cfg);
if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
pci_read_cap(pcib, cfg);
STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links);
devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
devlist_entry->conf.pc_sel.pc_func = cfg->func;
devlist_entry->conf.pc_hdr = cfg->hdrtype;
devlist_entry->conf.pc_subvendor = cfg->subvendor;
devlist_entry->conf.pc_subdevice = cfg->subdevice;
devlist_entry->conf.pc_vendor = cfg->vendor;
devlist_entry->conf.pc_device = cfg->device;
devlist_entry->conf.pc_class = cfg->baseclass;
devlist_entry->conf.pc_subclass = cfg->subclass;
devlist_entry->conf.pc_progif = cfg->progif;
devlist_entry->conf.pc_revid = cfg->revid;
pci_numdevs++;
pci_generation++;
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
return (devlist_entry);
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
}
Refactor PCI device creation Refactor creation of PCI devices into helper methods that can be used by the VF creation code. Differential Revision: https://reviews.freebsd.org/D67 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:26 +00:00
#undef REG
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
Support for Enhanced Allocation in PCI On some platforms, BAR entries are hardcoded and must not be accessed using standard method. Add functionality to identify this situation and configure the bus based on Enhanced Allocation structure. Obtained from: Semihalf Sponsored by: Cavium Approved by: cognet (mentor) Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D5242
2016-03-02 09:54:58 +00:00
static void
pci_ea_fill_info(device_t pcib, pcicfgregs *cfg)
{
#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \
cfg->ea.ea_location + (n), w)
int num_ent;
int ptr;
int a, b;
uint32_t val;
int ent_size;
uint32_t dw[4];
uint64_t base, max_offset;
struct pci_ea_entry *eae;
if (cfg->ea.ea_location == 0)
return;
STAILQ_INIT(&cfg->ea.ea_entries);
/* Determine the number of entries */
num_ent = REG(PCIR_EA_NUM_ENT, 2);
num_ent &= PCIM_EA_NUM_ENT_MASK;
/* Find the first entry to care of */
ptr = PCIR_EA_FIRST_ENT;
/* Skip DWORD 2 for type 1 functions */
if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE)
ptr += 4;
for (a = 0; a < num_ent; a++) {
eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO);
eae->eae_cfg_offset = cfg->ea.ea_location + ptr;
/* Read a number of dwords in the entry */
val = REG(ptr, 4);
ptr += 4;
ent_size = (val & PCIM_EA_ES);
for (b = 0; b < ent_size; b++) {
dw[b] = REG(ptr, 4);
ptr += 4;
}
eae->eae_flags = val;
eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET;
base = dw[0] & PCIM_EA_FIELD_MASK;
max_offset = dw[1] | ~PCIM_EA_FIELD_MASK;
b = 2;
if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) {
base |= (uint64_t)dw[b] << 32UL;
b++;
}
if (((dw[1] & PCIM_EA_IS_64) != 0)
&& (b < ent_size)) {
max_offset |= (uint64_t)dw[b] << 32UL;
b++;
}
eae->eae_base = base;
eae->eae_max_offset = max_offset;
STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link);
if (bootverbose) {
printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n",
cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags,
(uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset);
}
}
}
#undef REG
These don't need to be semi-public after all.
2003-02-17 19:47:02 +00:00
static void
Rename pci_find_extcap() to pci_find_cap(). PCI now uses the term "extended capabilities" to refer to the new set of capability structures starting at offset 0x100 in config space for PCI-express devices. For now both function names will still work. I will merge this to older branches to ease driver portability, but 9.0 will ship with a new pci_find_extcap() function that locates extended capabilities instead. Reviewed by: imp MFC after: 1 week
2011-03-22 12:05:49 +00:00
pci_read_cap(device_t pcib, pcicfgregs *cfg)
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
{
Replace #define<space> with #define<tab> so the code is consistent with style(9) and avoids mixing the two formats.
2006-12-14 16:53:48 +00:00
#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
Add support for the U4 PCI-Express bridge chipset used in late-generation Powermac G5 systems. MSI and several other things are not presently supported. The U3/U4 internal device support portions of this change were contributed by Andreas Tobler. MFC after: 1 week
2010-05-16 15:18:25 +00:00
#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
- Add constants for HT PCI capability registers including the various subtypes of HT capabilities. - Add constants for the MSI mapping window HT PCI capability. - On i386 and amd64, enable the MSI mapping window on any HT bridges we encounter and report any non-standard mapping window addresses.
2006-12-12 19:33:25 +00:00
uint64_t addr;
#endif
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
uint32_t val;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
int ptr, nextptr, ptrptr;
Remove most of the magic constants from the extcap parsing code.
2003-09-14 06:23:19 +00:00
switch (cfg->hdrtype & PCIM_HDRTYPE) {
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
case PCIM_HDRTYPE_NORMAL:
case PCIM_HDRTYPE_BRIDGE:
Remove most of the magic constants from the extcap parsing code.
2003-09-14 06:23:19 +00:00
ptrptr = PCIR_CAP_PTR;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
break;
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
case PCIM_HDRTYPE_CARDBUS:
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
break;
default:
return; /* no extended capabilities support */
}
nextptr = REG(ptrptr, 1); /* sanity check? */
/*
* Read capability entries.
*/
while (nextptr != 0) {
Sanity check ptr for legal values so it is less likely (but not impossible) to get stuck in an infinite loop. Obtained from: msmith@freebsd.org
2001-01-01 16:49:31 +00:00
/* Sanity check */
if (nextptr > 255) {
printf("illegal PCI extended capability offset %d\n",
nextptr);
return;
}
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
/* Find the next entry */
ptr = nextptr;
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
2005-12-20 19:57:47 +00:00
nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
/* Process this entry */
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
2005-12-20 19:57:47 +00:00
switch (REG(ptr + PCICAP_ID, 1)) {
Remove most of the magic constants from the extcap parsing code.
2003-09-14 06:23:19 +00:00
case PCIY_PMG: /* PCI power management */
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
if (cfg->pp.pp_cap == 0) {
cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
Update PCI power management registers per PCI Bus Power Management Interface Specification Rev. 1.2. Rename pp_pcmcsr field of PM capabilities to pp_bse to avoid further confusions and adjust some comments accordingly. The real PMCSR (Power Management Control/Status Register) is PCIR_POWER_STATUS and it is actually BSE (PCI-to-PCI Bridge Support Extensions) register.
2010-10-20 23:41:16 +00:00
cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
if ((nextptr - ptr) > PCIR_POWER_DATA)
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
}
break;
- Add constants for HT PCI capability registers including the various subtypes of HT capabilities. - Add constants for the MSI mapping window HT PCI capability. - On i386 and amd64, enable the MSI mapping window on any HT bridges we encounter and report any non-standard mapping window addresses.
2006-12-12 19:33:25 +00:00
case PCIY_HT: /* HyperTransport */
/* Determine HT-specific capability type. */
val = REG(ptr + PCIR_HT_COMMAND, 2);
Fix a few issues with HyperTransport devices and MSI interrupts: - Always enable the HyperTransport MSI mapping window for HyperTransport to PCI bridges (these show up as HyperTransport slave devices). The mapping windows in PCI-PCI bridges are enabled by existing code in the PCI-PCI bridge driver as MSI requests propagate up the device tree, but Host-PCI bridges don't really show up in that tree. - If the PCI device at domain 0 bus 0 slot 0 function 0 is not a HyperTransport device, then blacklist MSI on any other HT devices in the system. Linux has a similar quirk. PR: kern/155442 Tested by: Zack Dannar zdannar of gmail MFC after: 1 week
2011-03-18 12:13:04 +00:00
Partially revert previous change. Drop the quirk to disable MSI for HT chipsets that do not have an HT slave at 0:0:0:0. The Linux quirk is actually specific to Nvidia chipsets and the check I had added was in the wrong place. Prodded by: nathanw
2011-03-18 14:06:12 +00:00
if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
Fix a few issues with HyperTransport devices and MSI interrupts: - Always enable the HyperTransport MSI mapping window for HyperTransport to PCI bridges (these show up as HyperTransport slave devices). The mapping windows in PCI-PCI bridges are enabled by existing code in the PCI-PCI bridge driver as MSI requests propagate up the device tree, but Host-PCI bridges don't really show up in that tree. - If the PCI device at domain 0 bus 0 slot 0 function 0 is not a HyperTransport device, then blacklist MSI on any other HT devices in the system. Linux has a similar quirk. PR: kern/155442 Tested by: Zack Dannar zdannar of gmail MFC after: 1 week
2011-03-18 12:13:04 +00:00
cfg->ht.ht_slave = ptr;
#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
- Add constants for HT PCI capability registers including the various subtypes of HT capabilities. - Add constants for the MSI mapping window HT PCI capability. - On i386 and amd64, enable the MSI mapping window on any HT bridges we encounter and report any non-standard mapping window addresses.
2006-12-12 19:33:25 +00:00
switch (val & PCIM_HTCMD_CAP_MASK) {
case PCIM_HTCAP_MSI_MAPPING:
- HT 2.00b added a new flag to the MSI mapping HT capability to indicate that the MSI mapping window is fixed at 0xfee00000 and the capability does not include two more dwords used to program the address. Supporting this mostly results in quieting spurious warnings during boot about non-default MSI mapping windows. - HT 2.00b also added a new HT capability type, so support that in pciconf. MFC after: 3 days Tested by: jmg
2007-04-25 14:45:46 +00:00
if (!(val & PCIM_HTCMD_MSI_FIXED)) {
/* Sanity check the mapping window. */
addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
4);
addr <<= 32;
Don't throw away upper 32-bits of the HT MSI address window. In practice this is harmless since the address window for MSI on x86 is in the lower 4 GB. Submitted by: mav MFC after: 1 week
2009-02-26 14:32:14 +00:00
addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
- HT 2.00b added a new flag to the MSI mapping HT capability to indicate that the MSI mapping window is fixed at 0xfee00000 and the capability does not include two more dwords used to program the address. Supporting this mostly results in quieting spurious warnings during boot about non-default MSI mapping windows. - HT 2.00b also added a new HT capability type, so support that in pciconf. MFC after: 3 days Tested by: jmg
2007-04-25 14:45:46 +00:00
4);
if (addr != MSI_INTEL_ADDR_BASE)
device_printf(pcib,
Fix a few issues with HyperTransport devices and MSI interrupts: - Always enable the HyperTransport MSI mapping window for HyperTransport to PCI bridges (these show up as HyperTransport slave devices). The mapping windows in PCI-PCI bridges are enabled by existing code in the PCI-PCI bridge driver as MSI requests propagate up the device tree, but Host-PCI bridges don't really show up in that tree. - If the PCI device at domain 0 bus 0 slot 0 function 0 is not a HyperTransport device, then blacklist MSI on any other HT devices in the system. Linux has a similar quirk. PR: kern/155442 Tested by: Zack Dannar zdannar of gmail MFC after: 1 week
2011-03-18 12:13:04 +00:00
"HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
cfg->domain, cfg->bus,
cfg->slot, cfg->func,
(long long)addr);
SATA device on some nForce based boards could get confused if MSI is not used but MSI to HyperTransport IRQ mapping is enabled, and would act as if MSI is turned on, resulting in interrupt loss. This commit will, 1. enable MSI mapping on a device only when MSI is enabled for that device and the MSI address matches the HT mapping window. 2. enable MSI mapping on a bridge only when a downstream device is allocated an MSI address in the mapping window PR: kern/118842 Reviewed by: jhb MFC after: 1 week
2008-07-23 09:44:36 +00:00
} else
addr = MSI_INTEL_ADDR_BASE;
- Add constants for HT PCI capability registers including the various subtypes of HT capabilities. - Add constants for the MSI mapping window HT PCI capability. - On i386 and amd64, enable the MSI mapping window on any HT bridges we encounter and report any non-standard mapping window addresses.
2006-12-12 19:33:25 +00:00
SATA device on some nForce based boards could get confused if MSI is not used but MSI to HyperTransport IRQ mapping is enabled, and would act as if MSI is turned on, resulting in interrupt loss. This commit will, 1. enable MSI mapping on a device only when MSI is enabled for that device and the MSI address matches the HT mapping window. 2. enable MSI mapping on a bridge only when a downstream device is allocated an MSI address in the mapping window PR: kern/118842 Reviewed by: jhb MFC after: 1 week
2008-07-23 09:44:36 +00:00
cfg->ht.ht_msimap = ptr;
cfg->ht.ht_msictrl = val;
cfg->ht.ht_msiaddr = addr;
- Add constants for HT PCI capability registers including the various subtypes of HT capabilities. - Add constants for the MSI mapping window HT PCI capability. - On i386 and amd64, enable the MSI mapping window on any HT bridges we encounter and report any non-standard mapping window addresses.
2006-12-12 19:33:25 +00:00
break;
}
#endif
Fix a few issues with HyperTransport devices and MSI interrupts: - Always enable the HyperTransport MSI mapping window for HyperTransport to PCI bridges (these show up as HyperTransport slave devices). The mapping windows in PCI-PCI bridges are enabled by existing code in the PCI-PCI bridge driver as MSI requests propagate up the device tree, but Host-PCI bridges don't really show up in that tree. - If the PCI device at domain 0 bus 0 slot 0 function 0 is not a HyperTransport device, then blacklist MSI on any other HT devices in the system. Linux has a similar quirk. PR: kern/155442 Tested by: Zack Dannar zdannar of gmail MFC after: 1 week
2011-03-18 12:13:04 +00:00
break;
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
case PCIY_MSI: /* PCI MSI */
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
cfg->msi.msi_location = ptr;
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
PCIM_MSICTRL_MMC_MASK)>>1);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
break;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
case PCIY_MSIX: /* PCI MSI-X */
cfg->msix.msix_location = ptr;
cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
PCIM_MSIXCTRL_TABLE_SIZE) + 1;
val = REG(ptr + PCIR_MSIX_TABLE, 4);
cfg->msix.msix_table_bar = PCIR_BAR(val &
PCIM_MSIX_BIR_MASK);
cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
val = REG(ptr + PCIR_MSIX_PBA, 4);
cfg->msix.msix_pba_bar = PCIR_BAR(val &
PCIM_MSIX_BIR_MASK);
cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
break;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
case PCIY_VPD: /* PCI Vital Product Data */
Change the VPD code to read the VPD data on-demand when a driver asks for it via pci_get_vpd_*() rather than always reading it for each device during boot. I've left the tunable so that it can still be turned off if a device driver causes a lockup via a query to a broken device, but devices whose drivers do not use VPD (the vast majority) should no longer result in lockups during boot, and most folks should not need to tweak the tunable now. Tested on: bge(4) Silence from: jmg
2007-03-26 20:18:52 +00:00
cfg->vpd.vpd_reg = ptr;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
break;
Fix the subvendor ID for PCI-PCI bridges. - Retire the PCI_SUB*_1 constants and don't try to read a subvendor ID out of them. There isn't a standard subvendor ID field for PCI-PCI bridges. Instead, the dword at offset 0x34 is actually mostly reserved except for the LSB which is the capabilities pointer. - Add support for the PCI-PCI bridge subvendor ID capability (13) and use it to set the subvendor ID for PCI-PCI bridges. MFC after: 1 month
2007-01-16 17:04:42 +00:00
case PCIY_SUBVENDOR:
/* Should always be true. */
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
if ((cfg->hdrtype & PCIM_HDRTYPE) ==
PCIM_HDRTYPE_BRIDGE) {
Fix the subvendor ID for PCI-PCI bridges. - Retire the PCI_SUB*_1 constants and don't try to read a subvendor ID out of them. There isn't a standard subvendor ID field for PCI-PCI bridges. Instead, the dword at offset 0x34 is actually mostly reserved except for the LSB which is the capabilities pointer. - Add support for the PCI-PCI bridge subvendor ID capability (13) and use it to set the subvendor ID for PCI-PCI bridges. MFC after: 1 month
2007-01-16 17:04:42 +00:00
val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
cfg->subvendor = val & 0xffff;
cfg->subdevice = val >> 16;
}
Add missing 'break' that in this case is harmless.
2007-02-14 17:02:15 +00:00
break;
Adjust the global MSI blacklisting strategy so we don't have to explicitly blacklist a bunch of old chipsets. If a system contains a PCI-PCI bridge that supports PCI-X, assume the chipset supports PCI-X. If a system contains a PCI-express root port, assume the chipset supports PCI-express. If the chipset doesn't support either PCI-X or PCI-express, then blacklist it by default. We should now only need to explicitly blacklist PCI-X or PCI-express chipsets that don't properly handle MSI.
2007-02-14 22:36:27 +00:00
case PCIY_PCIX: /* PCI-X */
/*
* Assume we have a PCI-X chipset if we have
* at least one PCI-PCI bridge with a PCI-X
* capability. Note that some systems with
* PCI-express or HT chipsets might match on
* this check as well.
*/
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
if ((cfg->hdrtype & PCIM_HDRTYPE) ==
PCIM_HDRTYPE_BRIDGE)
Adjust the global MSI blacklisting strategy so we don't have to explicitly blacklist a bunch of old chipsets. If a system contains a PCI-PCI bridge that supports PCI-X, assume the chipset supports PCI-X. If a system contains a PCI-express root port, assume the chipset supports PCI-express. If the chipset doesn't support either PCI-X or PCI-express, then blacklist it by default. We should now only need to explicitly blacklist PCI-X or PCI-express chipsets that don't properly handle MSI.
2007-02-14 22:36:27 +00:00
pcix_chipset = 1;
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
cfg->pcix.pcix_location = ptr;
Adjust the global MSI blacklisting strategy so we don't have to explicitly blacklist a bunch of old chipsets. If a system contains a PCI-PCI bridge that supports PCI-X, assume the chipset supports PCI-X. If a system contains a PCI-express root port, assume the chipset supports PCI-express. If the chipset doesn't support either PCI-X or PCI-express, then blacklist it by default. We should now only need to explicitly blacklist PCI-X or PCI-express chipsets that don't properly handle MSI.
2007-02-14 22:36:27 +00:00
break;
case PCIY_EXPRESS: /* PCI-express */
/*
* Assume we have a PCI-express chipset if we have
Relax the check for a PCI-express chipset by assuming the system is a PCI-express chipset (and thus has functional MSI) if there are any PCI-express devices in the system, not requiring a root port device. With PCI-X the chipset detection has to be very conservative because there are known systems with PCI-X devices that do not appear to have PCI-X chipsets. However, with PCI-express I'm not sure it is possible to have a PCI-express device in a system with a non-PCI-express chipset. If we assume that is the case then this change is valid. It is also required for at least some PCI-express systems that don't have any devices with a root port capability (some ICH9 systems). MFC after: 1 week Reported by: jfv
2008-02-01 20:31:09 +00:00
* at least one PCI-express device.
Adjust the global MSI blacklisting strategy so we don't have to explicitly blacklist a bunch of old chipsets. If a system contains a PCI-PCI bridge that supports PCI-X, assume the chipset supports PCI-X. If a system contains a PCI-express root port, assume the chipset supports PCI-express. If the chipset doesn't support either PCI-X or PCI-express, then blacklist it by default. We should now only need to explicitly blacklist PCI-X or PCI-express chipsets that don't properly handle MSI.
2007-02-14 22:36:27 +00:00
*/
Relax the check for a PCI-express chipset by assuming the system is a PCI-express chipset (and thus has functional MSI) if there are any PCI-express devices in the system, not requiring a root port device. With PCI-X the chipset detection has to be very conservative because there are known systems with PCI-X devices that do not appear to have PCI-X chipsets. However, with PCI-express I'm not sure it is possible to have a PCI-express device in a system with a non-PCI-express chipset. If we assume that is the case then this change is valid. It is also required for at least some PCI-express systems that don't have any devices with a root port capability (some ICH9 systems). MFC after: 1 week Reported by: jfv
2008-02-01 20:31:09 +00:00
pcie_chipset = 1;
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
cfg->pcie.pcie_location = ptr;
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
val = REG(ptr + PCIER_FLAGS, 2);
cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
Adjust the global MSI blacklisting strategy so we don't have to explicitly blacklist a bunch of old chipsets. If a system contains a PCI-PCI bridge that supports PCI-X, assume the chipset supports PCI-X. If a system contains a PCI-express root port, assume the chipset supports PCI-express. If the chipset doesn't support either PCI-X or PCI-express, then blacklist it by default. We should now only need to explicitly blacklist PCI-X or PCI-express chipsets that don't properly handle MSI.
2007-02-14 22:36:27 +00:00
break;
Support for Enhanced Allocation in PCI On some platforms, BAR entries are hardcoded and must not be accessed using standard method. Add functionality to identify this situation and configure the bus based on Enhanced Allocation structure. Obtained from: Semihalf Sponsored by: Cavium Approved by: cognet (mentor) Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D5242
2016-03-02 09:54:58 +00:00
case PCIY_EA: /* Enhanced Allocation */
cfg->ea.ea_location = ptr;
pci_ea_fill_info(pcib, cfg);
break;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
default:
break;
}
}
Fix a few issues with HyperTransport devices and MSI interrupts: - Always enable the HyperTransport MSI mapping window for HyperTransport to PCI bridges (these show up as HyperTransport slave devices). The mapping windows in PCI-PCI bridges are enabled by existing code in the PCI-PCI bridge driver as MSI requests propagate up the device tree, but Host-PCI bridges don't really show up in that tree. - If the PCI device at domain 0 bus 0 slot 0 function 0 is not a HyperTransport device, then blacklist MSI on any other HT devices in the system. Linux has a similar quirk. PR: kern/155442 Tested by: Zack Dannar zdannar of gmail MFC after: 1 week
2011-03-18 12:13:04 +00:00
Use a more proper fix for enabling HT MSI mapping windows on Host-PCI bridges. Rather than blindly enabling the windows on all of them, only enable the window when an MSI interrupt is enabled for a device behind the bridge, similar to what already happens for HT PCI-PCI bridges. To implement this, each x86 Host-PCI bridge driver has to be able to locate it's actual backing device on bus 0. For ACPI, use the _ADR method to find the slot and function of the device. For the non-ACPI case, the legacy(4) driver already scans bus 0 looking for Host-PCI bridge devices. Now it saves the slot and function of each bridge that it finds as ivars that the Host-PCI bridge driver can then use in its pcib_map_msi() method. This fixes machines where non-MSI interrupts were broken by the previous round of HT MSI changes. Tested by: bapt MFC after: 1 week
2012-03-29 19:03:22 +00:00
#if defined(__powerpc__)
Fix a few issues with HyperTransport devices and MSI interrupts: - Always enable the HyperTransport MSI mapping window for HyperTransport to PCI bridges (these show up as HyperTransport slave devices). The mapping windows in PCI-PCI bridges are enabled by existing code in the PCI-PCI bridge driver as MSI requests propagate up the device tree, but Host-PCI bridges don't really show up in that tree. - If the PCI device at domain 0 bus 0 slot 0 function 0 is not a HyperTransport device, then blacklist MSI on any other HT devices in the system. Linux has a similar quirk. PR: kern/155442 Tested by: Zack Dannar zdannar of gmail MFC after: 1 week
2011-03-18 12:13:04 +00:00
/*
* Enable the MSI mapping window for all HyperTransport
* slaves. PCI-PCI bridges have their windows enabled via
* PCIB_MAP_MSI().
*/
if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
!(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
device_printf(pcib,
"Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
cfg->domain, cfg->bus, cfg->slot, cfg->func);
cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
2);
}
#endif
Give the WREG() macro the same lifetime as the REG() macro.
2006-12-12 19:30:40 +00:00
/* REG and WREG use carry through to next functions */
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
/*
* PCI Vital Product Data
*/
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
#define PCI_VPD_TIMEOUT 1000000
static int
pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
{
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
int count = PCI_VPD_TIMEOUT;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
- Use constants for VPD capability register offsets. - Add missing ()'s around return values.
2007-03-05 16:21:59 +00:00
WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
if (--count < 0)
return (ENXIO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
DELAY(1); /* limit looping */
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
}
*data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
return (0);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
#if 0
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
static int
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
{
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
int count = PCI_VPD_TIMEOUT;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
- Use constants for VPD capability register offsets. - Add missing ()'s around return values.
2007-03-05 16:21:59 +00:00
WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
if (--count < 0)
return (ENXIO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
DELAY(1); /* limit looping */
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
}
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
return (0);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
#endif
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
#undef PCI_VPD_TIMEOUT
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
struct vpd_readstate {
device_t pcib;
pcicfgregs *cfg;
uint32_t val;
int bytesinval;
int off;
uint8_t cksum;
};
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
static int
vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
{
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
uint32_t reg;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
uint8_t byte;
if (vrs->bytesinval == 0) {
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, &reg))
return (ENXIO);
vrs->val = le32toh(reg);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
vrs->off += 4;
byte = vrs->val & 0xff;
vrs->bytesinval = 3;
} else {
vrs->val = vrs->val >> 8;
byte = vrs->val & 0xff;
vrs->bytesinval--;
}
vrs->cksum += byte;
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
*data = byte;
return (0);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
static void
pci_read_vpd(device_t pcib, pcicfgregs *cfg)
{
struct vpd_readstate vrs;
int state;
int name;
int remain;
int i;
int alloc, off; /* alloc/off for RO/W arrays */
int cksumvalid;
int dflen;
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
uint8_t byte;
uint8_t byte2;
Change the VPD code to read the VPD data on-demand when a driver asks for it via pci_get_vpd_*() rather than always reading it for each device during boot. I've left the tunable so that it can still be turned off if a device driver causes a lockup via a query to a broken device, but devices whose drivers do not use VPD (the vast majority) should no longer result in lockups during boot, and most folks should not need to tweak the tunable now. Tested on: bge(4) Silence from: jmg
2007-03-26 20:18:52 +00:00
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
/* init vpd reader */
vrs.bytesinval = 0;
vrs.off = 0;
vrs.pcib = pcib;
vrs.cfg = cfg;
vrs.cksum = 0;
state = 0;
name = remain = i = 0; /* shut up stupid gcc */
alloc = off = 0; /* shut up stupid gcc */
dflen = 0; /* shut up stupid gcc */
cksumvalid = -1;
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
while (state >= 0) {
if (vpd_nextbyte(&vrs, &byte)) {
state = -2;
break;
}
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
#if 0
printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
"state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
vrs.off, vrs.bytesinval, byte, state, remain, name, i);
#endif
switch (state) {
case 0: /* item name */
if (byte & 0x80) {
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
if (vpd_nextbyte(&vrs, &byte2)) {
state = -2;
break;
}
remain = byte2;
if (vpd_nextbyte(&vrs, &byte2)) {
state = -2;
break;
}
remain |= byte2 << 8;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
name = byte & 0x7f;
} else {
remain = byte & 0x7;
name = (byte >> 3) & 0xf;
}
Remove spurious warning about invalid VPD data. The warning used to be displayed for valid VPDs about 512B or above in size. Fix the size check and add a break while here so that the routine stops if if detects any problem. Tested with "pciconf -lV" Reviewed by: kib@, jhb@ MFC after: 1 week Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D23679
2020-03-18 01:09:40 +00:00
if (vrs.off + remain - vrs.bytesinval > 0x8000) {
pci_printf(cfg,
"VPD data overflow, remain %#x\n", remain);
state = -1;
break;
}
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
switch (name) {
case 0x2: /* String */
cfg->vpd.vpd_ident = malloc(remain + 1,
M_DEVBUF, M_WAITOK);
i = 0;
state = 1;
break;
case 0xf: /* End */
state = -1;
break;
case 0x10: /* VPD-R */
alloc = 8;
off = 0;
cfg->vpd.vpd_ros = malloc(alloc *
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
M_WAITOK | M_ZERO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
state = 2;
break;
case 0x11: /* VPD-W */
alloc = 8;
off = 0;
cfg->vpd.vpd_w = malloc(alloc *
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
M_WAITOK | M_ZERO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
state = 5;
break;
fix hanging on invalid data... (This doesn't fix hanging due to broken hardware)... Tested by: Ian Dowse, Adam K Kirchhoff and Vladimir Kushnir
2006-11-09 21:05:32 +00:00
default: /* Invalid data, abort */
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
state = -1;
break;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
break;
case 1: /* Identifier String */
cfg->vpd.vpd_ident[i++] = byte;
remain--;
if (remain == 0) {
cfg->vpd.vpd_ident[i] = '\0';
state = 0;
}
break;
case 2: /* VPD-R Keyword Header */
if (off == alloc) {
cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
(alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
M_DEVBUF, M_WAITOK | M_ZERO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
cfg->vpd.vpd_ros[off].keyword[0] = byte;
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
if (vpd_nextbyte(&vrs, &byte2)) {
state = -2;
break;
}
cfg->vpd.vpd_ros[off].keyword[1] = byte2;
if (vpd_nextbyte(&vrs, &byte2)) {
state = -2;
break;
}
Add support for displaying VPD for PCI devices via pciconf. - Store the length of each read-only VPD value since not all values are guaranteed to be ASCII values (though most are). - Add a new pciio ioctl to fetch VPD for a single PCI device. The values are returned as a list of variable length records, one for the device name and each keyword. - Add a new -V flag to pciconf's list mode which displays VPD data for each device. MFC after: 1 week
2014-01-20 20:56:09 +00:00
cfg->vpd.vpd_ros[off].len = dflen = byte2;
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
if (dflen == 0 &&
strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
2) == 0) {
/*
* if this happens, we can't trust the rest
* of the VPD.
*/
Use pci_printf() instead of a home-rolled version in the VPD parsing code.
2012-02-29 22:06:44 +00:00
pci_printf(cfg, "bad keyword length: %d\n",
dflen);
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
cksumvalid = 0;
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
state = -1;
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
break;
} else if (dflen == 0) {
cfg->vpd.vpd_ros[off].value = malloc(1 *
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
sizeof(*cfg->vpd.vpd_ros[off].value),
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
M_DEVBUF, M_WAITOK);
cfg->vpd.vpd_ros[off].value[0] = '\x00';
} else
cfg->vpd.vpd_ros[off].value = malloc(
(dflen + 1) *
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
sizeof(*cfg->vpd.vpd_ros[off].value),
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
M_DEVBUF, M_WAITOK);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
remain -= 3;
i = 0;
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
/* keep in sync w/ state 3's transistions */
if (dflen == 0 && remain == 0)
state = 0;
else if (dflen == 0)
state = 2;
else
state = 3;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
break;
case 3: /* VPD-R Keyword Value */
cfg->vpd.vpd_ros[off].value[i++] = byte;
if (strncmp(cfg->vpd.vpd_ros[off].keyword,
"RV", 2) == 0 && cksumvalid == -1) {
if (vrs.cksum == 0)
cksumvalid = 1;
else {
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
if (bootverbose)
Use pci_printf() instead of a home-rolled version in the VPD parsing code.
2012-02-29 22:06:44 +00:00
pci_printf(cfg,
"bad VPD cksum, remain %hhu\n",
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
vrs.cksum);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
cksumvalid = 0;
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
state = -1;
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
break;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
}
dflen--;
remain--;
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
/* keep in sync w/ state 2's transistions */
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
if (dflen == 0)
cfg->vpd.vpd_ros[off++].value[i++] = '\0';
if (dflen == 0 && remain == 0) {
cfg->vpd.vpd_rocnt = off;
cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
off * sizeof(*cfg->vpd.vpd_ros),
M_DEVBUF, M_WAITOK | M_ZERO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
state = 0;
} else if (dflen == 0)
state = 2;
break;
case 4:
remain--;
if (remain == 0)
state = 0;
break;
case 5: /* VPD-W Keyword Header */
if (off == alloc) {
cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
(alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
M_DEVBUF, M_WAITOK | M_ZERO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
cfg->vpd.vpd_w[off].keyword[0] = byte;
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
if (vpd_nextbyte(&vrs, &byte2)) {
state = -2;
break;
}
cfg->vpd.vpd_w[off].keyword[1] = byte2;
if (vpd_nextbyte(&vrs, &byte2)) {
state = -2;
break;
}
cfg->vpd.vpd_w[off].len = dflen = byte2;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
sizeof(*cfg->vpd.vpd_w[off].value),
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
M_DEVBUF, M_WAITOK);
remain -= 3;
i = 0;
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
/* keep in sync w/ state 6's transistions */
if (dflen == 0 && remain == 0)
state = 0;
else if (dflen == 0)
state = 5;
else
state = 6;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
break;
case 6: /* VPD-W Keyword Value */
cfg->vpd.vpd_w[off].value[i++] = byte;
dflen--;
remain--;
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
/* keep in sync w/ state 5's transistions */
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
if (dflen == 0)
cfg->vpd.vpd_w[off++].value[i++] = '\0';
if (dflen == 0 && remain == 0) {
cfg->vpd.vpd_wcnt = off;
cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
off * sizeof(*cfg->vpd.vpd_w),
M_DEVBUF, M_WAITOK | M_ZERO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
state = 0;
} else if (dflen == 0)
state = 5;
break;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
default:
Use pci_printf() instead of a home-rolled version in the VPD parsing code.
2012-02-29 22:06:44 +00:00
pci_printf(cfg, "invalid state: %d\n", state);
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
state = -1;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
break;
}
}
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
if (cksumvalid == 0 || state < -1) {
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
/* read-only data bad, clean up */
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
if (cfg->vpd.vpd_ros != NULL) {
for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
free(cfg->vpd.vpd_ros, M_DEVBUF);
cfg->vpd.vpd_ros = NULL;
}
}
if (state < -1) {
/* I/O error, clean up */
Use pci_printf() instead of a home-rolled version in the VPD parsing code.
2012-02-29 22:06:44 +00:00
pci_printf(cfg, "failed to read VPD data.\n");
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
if (cfg->vpd.vpd_ident != NULL) {
free(cfg->vpd.vpd_ident, M_DEVBUF);
cfg->vpd.vpd_ident = NULL;
}
if (cfg->vpd.vpd_w != NULL) {
for (off = 0; cfg->vpd.vpd_w[off].value; off++)
free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
free(cfg->vpd.vpd_w, M_DEVBUF);
cfg->vpd.vpd_w = NULL;
}
fix tab indentation for CP and RV... If the length is zero, catch this early, instead of making dflen go negative and letting bad things happen... We also check to see if RV (checksum) is 0, and handle that has a checksum failure... Properly handle checksum failures by not processing read-write VPD data, and removing all the found read-only data... Tested by: oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
}
Change the VPD code to read the VPD data on-demand when a driver asks for it via pci_get_vpd_*() rather than always reading it for each device during boot. I've left the tunable so that it can still be turned off if a device driver causes a lockup via a query to a broken device, but devices whose drivers do not use VPD (the vast majority) should no longer result in lockups during boot, and most folks should not need to tweak the tunable now. Tested on: bge(4) Silence from: jmg
2007-03-26 20:18:52 +00:00
cfg->vpd.vpd_cached = 1;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
#undef REG
Give the WREG() macro the same lifetime as the REG() macro.
2006-12-12 19:30:40 +00:00
#undef WREG
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
}
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
int
pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
Change the VPD code to read the VPD data on-demand when a driver asks for it via pci_get_vpd_*() rather than always reading it for each device during boot. I've left the tunable so that it can still be turned off if a device driver causes a lockup via a query to a broken device, but devices whose drivers do not use VPD (the vast majority) should no longer result in lockups during boot, and most folks should not need to tweak the tunable now. Tested on: bge(4) Silence from: jmg
2007-03-26 20:18:52 +00:00
if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
pci_read_vpd(device_get_parent(dev), cfg);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
*identptr = cfg->vpd.vpd_ident;
if (*identptr == NULL)
- Use constants for VPD capability register offsets. - Add missing ()'s around return values.
2007-03-05 16:21:59 +00:00
return (ENXIO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
- Use constants for VPD capability register offsets. - Add missing ()'s around return values.
2007-03-05 16:21:59 +00:00
return (0);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
int
pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
const char **vptr)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
int i;
Change the VPD code to read the VPD data on-demand when a driver asks for it via pci_get_vpd_*() rather than always reading it for each device during boot. I've left the tunable so that it can still be turned off if a device driver causes a lockup via a query to a broken device, but devices whose drivers do not use VPD (the vast majority) should no longer result in lockups during boot, and most folks should not need to tweak the tunable now. Tested on: bge(4) Silence from: jmg
2007-03-26 20:18:52 +00:00
if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
pci_read_vpd(device_get_parent(dev), cfg);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
Make VPD register access more robust: - Implement timing out of VPD register access.[1] - Fix an off-by-one error of freeing malloc'd space when checksum is invalid. - Fix style(9) bugs, i.e., sizeof cannot be followed by space. - Retire now obsolete 'hw.pci.enable_vpd' tunable. Submitted by: cokane (initial revision)[1] Reviewed by: marius (intermediate revision) Silence from: jhb, jmg, rwatson Tested by: cokane, jkim MFC after: 3 days
2007-11-16 20:49:34 +00:00
sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
*vptr = cfg->vpd.vpd_ros[i].value;
Properly return success once a matching VPD entry is found in pci_get_vpd_readonly_method(). Previously the loop was always running to completion and falling through to failing with ENXIO. PR: kern/164313 Submitted by: Chuck Tuffli chuck tuffli net MFC after: 1 week
2012-01-19 21:38:19 +00:00
return (0);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
*vptr = NULL;
- Use constants for VPD capability register offsets. - Add missing ()'s around return values.
2007-03-05 16:21:59 +00:00
return (ENXIO);
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
}
Add support for displaying VPD for PCI devices via pciconf. - Store the length of each read-only VPD value since not all values are guaranteed to be ASCII values (though most are). - Add a new pciio ioctl to fetch VPD for a single PCI device. The values are returned as a list of variable length records, one for the device name and each keyword. - Add a new -V flag to pciconf's list mode which displays VPD data for each device. MFC after: 1 week
2014-01-20 20:56:09 +00:00
struct pcicfg_vpd *
pci_fetch_vpd_list(device_t dev)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
pcicfgregs *cfg = &dinfo->cfg;
if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg);
return (&cfg->vpd);
}
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
2005-12-20 19:57:47 +00:00
/*
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
* Find the requested HyperTransport capability and return the offset
* in configuration space via the pointer provided. The function
* returns 0 on success and an error code otherwise.
- Fix spacing in the comment. Reported by: jhb
2009-04-03 13:35:54 +00:00
*/
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
2005-12-20 19:57:47 +00:00
int
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
{
int ptr, error;
uint16_t val;
error = pci_find_cap(child, PCIY_HT, &ptr);
if (error)
return (error);
/*
* Traverse the capabilities list checking each HT capability
* to see if it matches the requested HT capability.
*/
Add PCI methods to iterate over the PCI capabilities VirtIO V1 provides configuration in multiple VENDOR capabilities so this allows all of the configuration to be discovered. Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D14325
2018-02-19 18:41:56 +00:00
for (;;) {
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
if (capability == PCIM_HTCAP_SLAVE ||
capability == PCIM_HTCAP_HOST)
val &= 0xe000;
else
val &= PCIM_HTCMD_CAP_MASK;
if (val == capability) {
if (capreg != NULL)
*capreg = ptr;
return (0);
}
/* Skip to the next HT capability. */
Add PCI methods to iterate over the PCI capabilities VirtIO V1 provides configuration in multiple VENDOR capabilities so this allows all of the configuration to be discovered. Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D14325
2018-02-19 18:41:56 +00:00
if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0)
break;
}
return (ENOENT);
}
/*
* Find the next requested HyperTransport capability after start and return
* the offset in configuration space via the pointer provided. The function
* returns 0 on success and an error code otherwise.
*/
int
pci_find_next_htcap_method(device_t dev, device_t child, int capability,
int start, int *capreg)
{
int ptr;
uint16_t val;
KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT,
("start capability is not HyperTransport capability"));
ptr = start;
/*
* Traverse the capabilities list checking each HT capability
* to see if it matches the requested HT capability.
*/
for (;;) {
/* Skip to the next HT capability. */
if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0)
break;
val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
if (capability == PCIM_HTCAP_SLAVE ||
capability == PCIM_HTCAP_HOST)
val &= 0xe000;
else
val &= PCIM_HTCMD_CAP_MASK;
if (val == capability) {
if (capreg != NULL)
*capreg = ptr;
return (0);
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
}
}
Add PCI methods to iterate over the PCI capabilities VirtIO V1 provides configuration in multiple VENDOR capabilities so this allows all of the configuration to be discovered. Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D14325
2018-02-19 18:41:56 +00:00
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
return (ENOENT);
}
/*
* Find the requested capability and return the offset in
* configuration space via the pointer provided. The function returns
* 0 on success and an error code otherwise.
*/
int
pci_find_cap_method(device_t dev, device_t child, int capability,
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
2005-12-20 19:57:47 +00:00
int *capreg)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
Add PCI methods to iterate over the PCI capabilities VirtIO V1 provides configuration in multiple VENDOR capabilities so this allows all of the configuration to be discovered. Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D14325
2018-02-19 18:41:56 +00:00
uint32_t status;
uint8_t ptr;
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
2005-12-20 19:57:47 +00:00
/*
* Check the CAP_LIST bit of the PCI status register first.
*/
status = pci_read_config(child, PCIR_STATUS, 2);
if (!(status & PCIM_STATUS_CAPPRESENT))
return (ENXIO);
/*
* Determine the start pointer of the capabilities list.
*/
switch (cfg->hdrtype & PCIM_HDRTYPE) {
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
case PCIM_HDRTYPE_NORMAL:
case PCIM_HDRTYPE_BRIDGE:
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
2005-12-20 19:57:47 +00:00
ptr = PCIR_CAP_PTR;
break;
Consistently check header type after reading PCIR_HDRTYPE register. While I'm here use defined macro instead of using magic numbers for header type. Reviewed by: jhb
2010-07-29 20:42:38 +00:00
case PCIM_HDRTYPE_CARDBUS:
Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
2005-12-20 19:57:47 +00:00
ptr = PCIR_CAP_PTR_2;
break;
default:
/* XXX: panic? */
return (ENXIO); /* no extended capabilities support */
}
ptr = pci_read_config(child, ptr, 1);
/*
* Traverse the capabilities list.
*/
while (ptr != 0) {
if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
if (capreg != NULL)
*capreg = ptr;
return (0);
}
ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
}
return (ENOENT);
}
Add PCI methods to iterate over the PCI capabilities VirtIO V1 provides configuration in multiple VENDOR capabilities so this allows all of the configuration to be discovered. Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D14325
2018-02-19 18:41:56 +00:00
/*
* Find the next requested capability after start and return the offset in
* configuration space via the pointer provided. The function returns
* 0 on success and an error code otherwise.
*/
int
pci_find_next_cap_method(device_t dev, device_t child, int capability,
int start, int *capreg)
{
uint8_t ptr;
KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability,
("start capability is not expected capability"));
ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1);
while (ptr != 0) {
if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
if (capreg != NULL)
*capreg = ptr;
return (0);
}
ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
}
return (ENOENT);
}
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
/*
* Find the requested extended capability and return the offset in
* configuration space via the pointer provided. The function returns
* 0 on success and an error code otherwise.
*/
int
pci_find_extcap_method(device_t dev, device_t child, int capability,
int *capreg)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
uint32_t ecap;
uint16_t ptr;
/* Only supported for PCI-express devices. */
if (cfg->pcie.pcie_location == 0)
return (ENXIO);
ptr = PCIR_EXTCAP;
ecap = pci_read_config(child, ptr, 4);
if (ecap == 0xffffffff || ecap == 0)
return (ENOENT);
for (;;) {
if (PCI_EXTCAP_ID(ecap) == capability) {
if (capreg != NULL)
*capreg = ptr;
return (0);
}
ptr = PCI_EXTCAP_NEXTPTR(ecap);
if (ptr == 0)
break;
ecap = pci_read_config(child, ptr, 4);
}
return (ENOENT);
}
Add PCI methods to iterate over the PCI capabilities VirtIO V1 provides configuration in multiple VENDOR capabilities so this allows all of the configuration to be discovered. Reviewed by: jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D14325
2018-02-19 18:41:56 +00:00
/*
* Find the next requested extended capability after start and return the
* offset in configuration space via the pointer provided. The function
* returns 0 on success and an error code otherwise.
*/
int
pci_find_next_extcap_method(device_t dev, device_t child, int capability,
int start, int *capreg)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
uint32_t ecap;
uint16_t ptr;
/* Only supported for PCI-express devices. */
if (cfg->pcie.pcie_location == 0)
return (ENXIO);
ecap = pci_read_config(child, start, 4);
KASSERT(PCI_EXTCAP_ID(ecap) == capability,
("start extended capability is not expected capability"));
ptr = PCI_EXTCAP_NEXTPTR(ecap);
while (ptr != 0) {
ecap = pci_read_config(child, ptr, 4);
if (PCI_EXTCAP_ID(ecap) == capability) {
if (capreg != NULL)
*capreg = ptr;
return (0);
}
ptr = PCI_EXTCAP_NEXTPTR(ecap);
}
return (ENOENT);
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/*
* Support for MSI-X message interrupts.
*/
Add MSIX rewrite table quirk for use with VMs. This patch solves IRQ generation problems using the mlx5en(4) driver with xenserver v6.5.0 in SRIOV and PCI-passthrough modes. Until further the hw.pci.msix_rewrite_table quirk must be set manually in /boot/loader.conf . Reviewed by: jhb @ Sponsored by: Mellanox Technologies MFC after: 2 weeks
2016-12-30 08:37:30 +00:00
static void
pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data)
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
{
Add MSIX rewrite table quirk for use with VMs. This patch solves IRQ generation problems using the mlx5en(4) driver with xenserver v6.5.0 in SRIOV and PCI-passthrough modes. Until further the hw.pci.msix_rewrite_table quirk must be set manually in /boot/loader.conf . Reviewed by: jhb @ Sponsored by: Mellanox Technologies MFC after: 2 weeks
2016-12-30 08:37:30 +00:00
struct pci_devinfo *dinfo = device_get_ivars(dev);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msix *msix = &dinfo->cfg.msix;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
uint32_t offset;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
KASSERT(msix->msix_table_len > index, ("bogus index"));
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
offset = msix->msix_table_offset + index * 16;
bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
bus_write_4(msix->msix_table_res, offset + 8, data);
Add MSIX rewrite table quirk for use with VMs. This patch solves IRQ generation problems using the mlx5en(4) driver with xenserver v6.5.0 in SRIOV and PCI-passthrough modes. Until further the hw.pci.msix_rewrite_table quirk must be set manually in /boot/loader.conf . Reviewed by: jhb @ Sponsored by: Mellanox Technologies MFC after: 2 weeks
2016-12-30 08:37:30 +00:00
}
void
pci_enable_msix_method(device_t dev, device_t child, u_int index,
uint64_t address, uint32_t data)
{
if (pci_msix_rewrite_table) {
struct pci_devinfo *dinfo = device_get_ivars(child);
struct pcicfg_msix *msix = &dinfo->cfg.msix;
/*
* Some VM hosts require MSIX to be disabled in the
* control register before updating the MSIX table
* entries are allowed. It is not enough to only
* disable MSIX while updating a single entry. MSIX
* must be disabled while updating all entries in the
* table.
*/
pci_write_config(child,
msix->msix_location + PCIR_MSIX_CTRL,
msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2);
pci_resume_msix(child);
} else
pci_write_msix_entry(child, index, address, data);
SATA device on some nForce based boards could get confused if MSI is not used but MSI to HyperTransport IRQ mapping is enabled, and would act as if MSI is turned on, resulting in interrupt loss. This commit will, 1. enable MSI mapping on a device only when MSI is enabled for that device and the MSI address matches the HT mapping window. 2. enable MSI mapping on a bridge only when a downstream device is allocated an MSI address in the mapping window PR: kern/118842 Reviewed by: jhb MFC after: 1 week
2008-07-23 09:44:36 +00:00
/* Enable MSI -> HT mapping. */
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_ht_map_msi(child, address);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
}
void
pci_mask_msix(device_t dev, u_int index)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msix *msix = &dinfo->cfg.msix;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
uint32_t offset, val;
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
KASSERT(msix->msix_msgnum > index, ("bogus index"));
offset = msix->msix_table_offset + index * 16 + 12;
val = bus_read_4(msix->msix_table_res, offset);
Work around devices which return all zeros for reads of existing MSI-X table VCTRL registers. Unconditionally program the MSI-X vector control Mask field for MSI-X table entries without regarud for Mask's previous value. Some devices return all zeros on reads of the VCTRL registers, which would cause us to skip disabling interrupts. This fixes the Samsung SM961/PM961 SSDs which are return zero starting from offset 0x3084 within the memory region specified by BAR0, even when they are active MSI-X vectors. The Illumos kernel writes these unconditionally to 0 or 1. However, section 6.8.2.9 of the PCI Local Bus 3.0 spec (dated Feb 3, 2004) states for bits 31::01: After reset, the state of these bits must be 0. However, for potential future use, software must preserve the value of these reserved bits when modifying the value of other Vector Control bits. If software modifies the value of these reserved bits, the result is undefined." so we always set or clear the Mask bit, but otherwise preserves the old value. PR: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=211713 Reviewed By: imp, jhb Submitted by: Ka Ho Ng MFC After: 1 week Differential Revision: https://reviews.freebsd.org/D20873
2019-07-08 19:38:49 +00:00
val |= PCIM_MSIX_VCTRL_MASK;
/*
* Some devices (e.g. Samsung PM961) do not support reads of this
* register, so always write the new value.
*/
bus_write_4(msix->msix_table_res, offset, val);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
}
void
pci_unmask_msix(device_t dev, u_int index)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msix *msix = &dinfo->cfg.msix;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
uint32_t offset, val;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
KASSERT(msix->msix_table_len > index, ("bogus index"));
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
offset = msix->msix_table_offset + index * 16 + 12;
val = bus_read_4(msix->msix_table_res, offset);
Work around devices which return all zeros for reads of existing MSI-X table VCTRL registers. Unconditionally program the MSI-X vector control Mask field for MSI-X table entries without regarud for Mask's previous value. Some devices return all zeros on reads of the VCTRL registers, which would cause us to skip disabling interrupts. This fixes the Samsung SM961/PM961 SSDs which are return zero starting from offset 0x3084 within the memory region specified by BAR0, even when they are active MSI-X vectors. The Illumos kernel writes these unconditionally to 0 or 1. However, section 6.8.2.9 of the PCI Local Bus 3.0 spec (dated Feb 3, 2004) states for bits 31::01: After reset, the state of these bits must be 0. However, for potential future use, software must preserve the value of these reserved bits when modifying the value of other Vector Control bits. If software modifies the value of these reserved bits, the result is undefined." so we always set or clear the Mask bit, but otherwise preserves the old value. PR: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=211713 Reviewed By: imp, jhb Submitted by: Ka Ho Ng MFC After: 1 week Differential Revision: https://reviews.freebsd.org/D20873
2019-07-08 19:38:49 +00:00
val &= ~PCIM_MSIX_VCTRL_MASK;
/*
* Some devices (e.g. Samsung PM961) do not support reads of this
* register, so always write the new value.
*/
bus_write_4(msix->msix_table_res, offset, val);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
}
int
pci_pending_msix(device_t dev, u_int index)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msix *msix = &dinfo->cfg.msix;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
uint32_t offset, bit;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
KASSERT(msix->msix_table_len > index, ("bogus index"));
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
offset = msix->msix_pba_offset + (index / 32) * 4;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
bit = 1 << index % 32;
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
return (bus_read_4(msix->msix_pba_res, offset) & bit);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/*
* Restore MSI-X registers and table during resume. If MSI-X is
* enabled then walk the virtual table to restore the actual MSI-X
* table.
*/
static void
pci_resume_msix(device_t dev)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
struct pcicfg_msix *msix = &dinfo->cfg.msix;
struct msix_table_entry *mte;
struct msix_vector *mv;
int i;
if (msix->msix_alloc > 0) {
/* First, mask all vectors. */
for (i = 0; i < msix->msix_msgnum; i++)
pci_mask_msix(dev, i);
/* Second, program any messages with at least one handler. */
for (i = 0; i < msix->msix_table_len; i++) {
mte = &msix->msix_table[i];
if (mte->mte_vector == 0 || mte->mte_handlers == 0)
continue;
mv = &msix->msix_vectors[mte->mte_vector - 1];
Add MSIX rewrite table quirk for use with VMs. This patch solves IRQ generation problems using the mlx5en(4) driver with xenserver v6.5.0 in SRIOV and PCI-passthrough modes. Until further the hw.pci.msix_rewrite_table quirk must be set manually in /boot/loader.conf . Reviewed by: jhb @ Sponsored by: Mellanox Technologies MFC after: 2 weeks
2016-12-30 08:37:30 +00:00
pci_write_msix_entry(dev, i, mv->mv_address,
mv->mv_data);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
pci_unmask_msix(dev, i);
}
}
pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
msix->msix_ctrl, 2);
}
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
/*
* Attempt to allocate *count MSI-X messages. The actual number allocated is
* returned in *count. After this function returns, each message will be
* available to the driver as SYS_RES_IRQ resources starting at rid 1.
*/
int
pci_alloc_msix_method(device_t dev, device_t child, int *count)
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
struct resource_list_entry *rle;
int actual, error, i, irq, max;
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
/* Don't let count == 0 get us into trouble. */
if (*count == 0)
return (EINVAL);
/* If rid 0 is allocated, then fail. */
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
if (rle != NULL && rle->res != NULL)
return (ENXIO);
/* Already have allocated messages? */
if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
return (ENXIO);
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
/* If MSI-X is blacklisted for this system, fail. */
if (pci_msix_blacklisted())
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
return (ENXIO);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* MSI-X capability present? */
if (cfg->msix.msix_location == 0 || !pci_do_msix)
return (ENODEV);
/* Make sure the appropriate BARs are mapped. */
rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
cfg->msix.msix_table_bar);
if (rle == NULL || rle->res == NULL ||
!(rman_get_flags(rle->res) & RF_ACTIVE))
return (ENXIO);
cfg->msix.msix_table_res = rle->res;
if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
cfg->msix.msix_pba_bar);
if (rle == NULL || rle->res == NULL ||
!(rman_get_flags(rle->res) & RF_ACTIVE))
return (ENXIO);
}
cfg->msix.msix_pba_res = rle->res;
Add some bootverbose printf's to detail how many MSI messages are allocated and to which IRQs. Requested by: scottl
2006-12-12 19:29:01 +00:00
if (bootverbose)
device_printf(child,
"attempting to allocate %d MSI-X vectors (%d supported)\n",
*count, cfg->msix.msix_msgnum);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
max = min(*count, cfg->msix.msix_msgnum);
for (i = 0; i < max; i++) {
/* Allocate a message. */
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
PCIB_ALLOC_MSIX() may already fail on the first pass, f.e. when the PCI-PCI bridge is blacklisted. In that case just return from pci_alloc_msix_method(), otherwise we continue without a single MSI-X resource, causing subsequent attempts to use the seemingly available resource to fail or when booting verbose a NULL-pointer dereference of rle->start when trying to print the IRQ in pci_alloc_msix_method(). Reviewed by: jhb MFC after: 1 week
2011-07-13 18:35:47 +00:00
if (error) {
if (i == 0)
return (error);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
break;
PCIB_ALLOC_MSIX() may already fail on the first pass, f.e. when the PCI-PCI bridge is blacklisted. In that case just return from pci_alloc_msix_method(), otherwise we continue without a single MSI-X resource, causing subsequent attempts to use the seemingly available resource to fail or when booting verbose a NULL-pointer dereference of rle->start when trying to print the IRQ in pci_alloc_msix_method(). Reviewed by: jhb MFC after: 1 week
2011-07-13 18:35:47 +00:00
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
irq, 1);
}
actual = i;
Add some bootverbose printf's to detail how many MSI messages are allocated and to which IRQs. Requested by: scottl
2006-12-12 19:29:01 +00:00
if (bootverbose) {
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
if (actual == 1)
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
device_printf(child, "using IRQ %ju for MSI-X\n",
Add some bootverbose printf's to detail how many MSI messages are allocated and to which IRQs. Requested by: scottl
2006-12-12 19:29:01 +00:00
rle->start);
else {
int run;
/*
* Be fancy and try to print contiguous runs of
* IRQ values as ranges. 'irq' is the previous IRQ.
* 'run' is true if we are in a range.
*/
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
device_printf(child, "using IRQs %ju", rle->start);
Add some bootverbose printf's to detail how many MSI messages are allocated and to which IRQs. Requested by: scottl
2006-12-12 19:29:01 +00:00
irq = rle->start;
run = 0;
for (i = 1; i < actual; i++) {
rle = resource_list_find(&dinfo->resources,
SYS_RES_IRQ, i + 1);
/* Still in a run? */
if (rle->start == irq + 1) {
run = 1;
irq++;
continue;
}
/* Finish previous range. */
if (run) {
printf("-%d", irq);
run = 0;
}
/* Start new range. */
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
printf(",%ju", rle->start);
Add some bootverbose printf's to detail how many MSI messages are allocated and to which IRQs. Requested by: scottl
2006-12-12 19:29:01 +00:00
irq = rle->start;
}
/* Unfinished range? */
if (run)
- Fix an off by one error in pci_remap_msix_method() that effectively broke the method as all the MSI-X table indices were off by one in the backend MD code. - Fix a cosmetic nit in the bootverbose printf in pci_alloc_msix_method().
2007-02-14 22:32:55 +00:00
printf("-%d", irq);
Add some bootverbose printf's to detail how many MSI messages are allocated and to which IRQs. Requested by: scottl
2006-12-12 19:29:01 +00:00
printf(" for MSI-X\n");
}
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* Mask all vectors. */
for (i = 0; i < cfg->msix.msix_msgnum; i++)
pci_mask_msix(child, i);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/* Allocate and initialize vector data and virtual table. */
cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
M_DEVBUF, M_WAITOK | M_ZERO);
cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
M_DEVBUF, M_WAITOK | M_ZERO);
for (i = 0; i < actual; i++) {
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
cfg->msix.msix_vectors[i].mv_irq = rle->start;
cfg->msix.msix_table[i].mte_vector = i + 1;
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* Update control register to enable MSI-X. */
cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
cfg->msix.msix_ctrl, 2);
/* Update counts of alloc'd messages. */
cfg->msix.msix_alloc = actual;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
cfg->msix.msix_table_len = actual;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
*count = actual;
return (0);
}
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
/*
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
* By default, pci_alloc_msix() will assign the allocated IRQ
* resources consecutively to the first N messages in the MSI-X table.
* However, device drivers may want to use different layouts if they
* either receive fewer messages than they asked for, or they wish to
* populate the MSI-X table sparsely. This method allows the driver
* to specify what layout it wants. It must be called after a
* successful pci_alloc_msix() but before any of the associated
* SYS_RES_IRQ resources are allocated via bus_alloc_resource().
*
* The 'vectors' array contains 'count' message vectors. The array
* maps directly to the MSI-X table in that index 0 in the array
* specifies the vector for the first message in the MSI-X table, etc.
* The vector value in each array index can either be 0 to indicate
* that no vector should be assigned to a message slot, or it can be a
* number from 1 to N (where N is the count returned from a
* succcessful call to pci_alloc_msix()) to indicate which message
* vector (IRQ) to be used for the corresponding message.
*
* On successful return, each message with a non-zero vector will have
* an associated SYS_RES_IRQ whose rid is equal to the array index +
* 1. Additionally, if any of the IRQs allocated via the previous
* call to pci_alloc_msix() are not used in the mapping, those IRQs
* will be freed back to the system automatically.
*
* For example, suppose a driver has a MSI-X table with 6 messages and
* asks for 6 messages, but pci_alloc_msix() only returns a count of
* 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
* C. After the call to pci_alloc_msix(), the device will be setup to
* have an MSI-X table of ABC--- (where - means no vector assigned).
Fix a typo.
2012-03-03 14:24:39 +00:00
* If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 },
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
* then the MSI-X table will look like A-AB-B, and the 'C' vector will
* be freed back to the system. This device will also have valid
* SYS_RES_IRQ rids of 1, 3, 4, and 6.
*
* In any case, the SYS_RES_IRQ rid X will always map to the message
* at MSI-X table index X - 1 and will only be valid if a vector is
* assigned to that table entry.
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
*/
int
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
pci_remap_msix_method(device_t dev, device_t child, int count,
const u_int *vectors)
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
{
struct pci_devinfo *dinfo = device_get_ivars(child);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
struct pcicfg_msix *msix = &dinfo->cfg.msix;
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
struct resource_list_entry *rle;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
int i, irq, j, *used;
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/*
* Have to have at least one message in the table but the
* table can't be bigger than the actual MSI-X table in the
* device.
*/
if (count == 0 || count > msix->msix_msgnum)
return (EINVAL);
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/* Sanity check the vectors. */
for (i = 0; i < count; i++)
if (vectors[i] > msix->msix_alloc)
return (EINVAL);
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/*
* Make sure there aren't any holes in the vectors to be used.
* It's a big pain to support it, and it doesn't really make
* sense anyway. Also, at least one vector must be used.
*/
used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
M_ZERO);
for (i = 0; i < count; i++)
if (vectors[i] != 0)
used[vectors[i] - 1] = 1;
for (i = 0; i < msix->msix_alloc - 1; i++)
if (used[i] == 0 && used[i + 1] == 1) {
free(used, M_DEVBUF);
return (EINVAL);
}
if (used[0] != 1) {
free(used, M_DEVBUF);
return (EINVAL);
}
drop a bunch of white space at end of lines and end of files... -x -wb apparently doesn't hide end of file white space changes.. This is to reduce the amount of diff for my PCIe HP changes..
2015-10-18 08:13:51 +00:00
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
/* Make sure none of the resources are allocated. */
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
for (i = 0; i < msix->msix_table_len; i++) {
if (msix->msix_table[i].mte_vector == 0)
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
continue;
Don't leak 'used' in a few error cases. Reported by: Maxime Villard
2015-03-01 21:41:35 +00:00
if (msix->msix_table[i].mte_handlers > 0) {
free(used, M_DEVBUF);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
return (EBUSY);
Don't leak 'used' in a few error cases. Reported by: Maxime Villard
2015-03-01 21:41:35 +00:00
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
KASSERT(rle != NULL, ("missing resource"));
Don't leak 'used' in a few error cases. Reported by: Maxime Villard
2015-03-01 21:41:35 +00:00
if (rle->res != NULL) {
free(used, M_DEVBUF);
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
return (EBUSY);
Don't leak 'used' in a few error cases. Reported by: Maxime Villard
2015-03-01 21:41:35 +00:00
}
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/* Free the existing resource list entries. */
for (i = 0; i < msix->msix_table_len; i++) {
if (msix->msix_table[i].mte_vector == 0)
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
continue;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/*
* Build the new virtual table keeping track of which vectors are
* used.
*/
free(msix->msix_table, M_DEVBUF);
msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
M_DEVBUF, M_WAITOK | M_ZERO);
for (i = 0; i < count; i++)
msix->msix_table[i].mte_vector = vectors[i];
msix->msix_table_len = count;
/* Free any unused IRQs and resize the vectors array if necessary. */
j = msix->msix_alloc - 1;
if (used[j] == 0) {
struct msix_vector *vec;
while (used[j] == 0) {
PCIB_RELEASE_MSIX(device_get_parent(dev), child,
msix->msix_vectors[j].mv_irq);
j--;
}
vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
M_WAITOK);
bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
(j + 1));
free(msix->msix_vectors, M_DEVBUF);
msix->msix_vectors = vec;
msix->msix_alloc = j + 1;
}
free(used, M_DEVBUF);
/* Map the IRQs onto the rids. */
for (i = 0; i < count; i++) {
if (vectors[i] == 0)
continue;
Fix an off by one error when remapping MSI-X vectors. pci_remap_msix() can be used to alter the mapping of allocated MSI-X vectors to the MSI-X table. The code had an off by one error when adding the IRQ resources after performing a remap. This was fatal for any vectors in the table that used the "last" valid IRQ as those vectors were assigned a garbage IRQ value. MFC after: 3 days
2016-05-03 00:35:11 +00:00
irq = msix->msix_vectors[vectors[i] - 1].mv_irq;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
irq, 1);
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
if (bootverbose) {
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
device_printf(child, "Remapped MSI-X IRQs as: ");
for (i = 0; i < count; i++) {
if (i != 0)
printf(", ");
if (vectors[i] == 0)
printf("---");
else
printf("%d",
Fix an off by one error when remapping MSI-X vectors. pci_remap_msix() can be used to alter the mapping of allocated MSI-X vectors to the MSI-X table. The code had an off by one error when adding the IRQ resources after performing a remap. This was fatal for any vectors in the table that used the "last" valid IRQ as those vectors were assigned a garbage IRQ value. MFC after: 3 days
2016-05-03 00:35:11 +00:00
msix->msix_vectors[vectors[i] - 1].mv_irq);
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
printf("\n");
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
}
return (0);
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
static int
pci_release_msix(device_t dev, device_t child)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msix *msix = &dinfo->cfg.msix;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
struct resource_list_entry *rle;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
int i;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* Do we have any messages to release? */
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
if (msix->msix_alloc == 0)
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
return (ENODEV);
/* Make sure none of the resources are allocated. */
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
for (i = 0; i < msix->msix_table_len; i++) {
if (msix->msix_table[i].mte_vector == 0)
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
continue;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
if (msix->msix_table[i].mte_handlers > 0)
return (EBUSY);
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
KASSERT(rle != NULL, ("missing resource"));
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
if (rle->res != NULL)
return (EBUSY);
}
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
/* Update control register to disable MSI-X. */
msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
msix->msix_ctrl, 2);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/* Free the resource list entries. */
for (i = 0; i < msix->msix_table_len; i++) {
if (msix->msix_table[i].mte_vector == 0)
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
continue;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
free(msix->msix_table, M_DEVBUF);
msix->msix_table_len = 0;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/* Release the IRQs. */
for (i = 0; i < msix->msix_alloc; i++)
PCIB_RELEASE_MSIX(device_get_parent(dev), child,
msix->msix_vectors[i].mv_irq);
free(msix->msix_vectors, M_DEVBUF);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
msix->msix_alloc = 0;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
return (0);
}
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
/*
* Return the max supported MSI-X messages this device supports.
* Basically, assuming the MD code can alloc messages, this function
* should return the maximum value that pci_alloc_msix() can return.
* Thus, it is subject to the tunables, etc.
*/
int
pci_msix_count_method(device_t dev, device_t child)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msix *msix = &dinfo->cfg.msix;
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
if (pci_do_msix && msix->msix_location != 0)
return (msix->msix_msgnum);
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
return (0);
}
Add accessor methods to fetch the BAR holding the MSI-X table and PBA. While here, explicitly note the requirement that the BAR(s) must be allocated prior to calling pci_alloc_msix(). Reviewed by: andrew, emaste MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D4688
2015-12-23 21:51:10 +00:00
int
pci_msix_pba_bar_method(device_t dev, device_t child)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
struct pcicfg_msix *msix = &dinfo->cfg.msix;
if (pci_do_msix && msix->msix_location != 0)
return (msix->msix_pba_bar);
return (-1);
}
int
pci_msix_table_bar_method(device_t dev, device_t child)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
struct pcicfg_msix *msix = &dinfo->cfg.msix;
if (pci_do_msix && msix->msix_location != 0)
return (msix->msix_table_bar);
return (-1);
}
SATA device on some nForce based boards could get confused if MSI is not used but MSI to HyperTransport IRQ mapping is enabled, and would act as if MSI is turned on, resulting in interrupt loss. This commit will, 1. enable MSI mapping on a device only when MSI is enabled for that device and the MSI address matches the HT mapping window. 2. enable MSI mapping on a bridge only when a downstream device is allocated an MSI address in the mapping window PR: kern/118842 Reviewed by: jhb MFC after: 1 week
2008-07-23 09:44:36 +00:00
/*
* HyperTransport MSI mapping control
*/
void
pci_ht_map_msi(device_t dev, uint64_t addr)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
struct pcicfg_ht *ht = &dinfo->cfg.ht;
if (!ht->ht_msimap)
return;
if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
ht->ht_msiaddr >> 20 == addr >> 20) {
/* Enable MSI -> HT mapping. */
ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
ht->ht_msictrl, 2);
}
if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
/* Disable MSI -> HT mapping. */
ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
ht->ht_msictrl, 2);
}
}
Add pci_get_max_payload() to fetch the PCI-express maximum payload size. Approved by: re (gjb) MFC after: 2 weeks Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D6951
2016-06-24 17:26:42 +00:00
int
pci_get_max_payload(device_t dev)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
int cap;
uint16_t val;
cap = dinfo->cfg.pcie.pcie_location;
if (cap == 0)
return (0);
val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
val &= PCIEM_CTL_MAX_PAYLOAD;
val >>= 5;
return (1 << (val + 7));
}
Add pci_get|set_max_read_req() helper functions to control maximum PCIe read request size. Reviewed by: jhb@
2010-02-05 17:18:48 +00:00
int
pci_get_max_read_req(device_t dev)
{
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
struct pci_devinfo *dinfo = device_get_ivars(dev);
Add pci_get|set_max_read_req() helper functions to control maximum PCIe read request size. Reviewed by: jhb@
2010-02-05 17:18:48 +00:00
int cap;
uint16_t val;
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
cap = dinfo->cfg.pcie.pcie_location;
if (cap == 0)
Add pci_get|set_max_read_req() helper functions to control maximum PCIe read request size. Reviewed by: jhb@
2010-02-05 17:18:48 +00:00
return (0);
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
val &= PCIEM_CTL_MAX_READ_REQUEST;
Add pci_get|set_max_read_req() helper functions to control maximum PCIe read request size. Reviewed by: jhb@
2010-02-05 17:18:48 +00:00
val >>= 12;
return (1 << (val + 7));
}
int
pci_set_max_read_req(device_t dev, int size)
{
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
struct pci_devinfo *dinfo = device_get_ivars(dev);
Add pci_get|set_max_read_req() helper functions to control maximum PCIe read request size. Reviewed by: jhb@
2010-02-05 17:18:48 +00:00
int cap;
uint16_t val;
Expand the set of APIs available for locating PCI capabilities: - pci_find_extcap() is repurposed to be used for fetching PCI-express extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>). - pci_find_htcap() can be used to locate a specific HyperTransport capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>). - Cache the starting location of the PCI-express capability for PCI-express devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
cap = dinfo->cfg.pcie.pcie_location;
if (cap == 0)
Add pci_get|set_max_read_req() helper functions to control maximum PCIe read request size. Reviewed by: jhb@
2010-02-05 17:18:48 +00:00
return (0);
if (size < 128)
size = 128;
if (size > 4096)
size = 4096;
size = (1 << (fls(size) - 1));
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
val &= ~PCIEM_CTL_MAX_READ_REQUEST;
Add pci_get|set_max_read_req() helper functions to control maximum PCIe read request size. Reviewed by: jhb@
2010-02-05 17:18:48 +00:00
val |= (fls(size) - 8) << 12;
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
Add pci_get|set_max_read_req() helper functions to control maximum PCIe read request size. Reviewed by: jhb@
2010-02-05 17:18:48 +00:00
return (size);
}
Add helper routines for PCI device drivers to read, write, and modify PCI-Express capability registers (that is, PCI config registers in the standard PCI config space belonging to the PCI-Express capability register set). Note that all of the current PCI-e registers are either 16 or 32-bits, so only widths of 2 or 4 bytes are supported. Reviewed by: imp MFC after: 1 week Sponsored by: Chelsio Differential Revision: https://reviews.freebsd.org/D4088
2015-11-05 21:26:06 +00:00
uint32_t
pcie_read_config(device_t dev, int reg, int width)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
int cap;
cap = dinfo->cfg.pcie.pcie_location;
if (cap == 0) {
if (width == 2)
return (0xffff);
return (0xffffffff);
}
return (pci_read_config(dev, cap + reg, width));
}
void
pcie_write_config(device_t dev, int reg, uint32_t value, int width)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
int cap;
cap = dinfo->cfg.pcie.pcie_location;
if (cap == 0)
return;
pci_write_config(dev, cap + reg, value, width);
}
/*
* Adjusts a PCI-e capability register by clearing the bits in mask
* and setting the bits in (value & mask). Bits not set in mask are
* not adjusted.
*
* Returns the old value on success or all ones on failure.
*/
uint32_t
pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value,
int width)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
uint32_t old, new;
int cap;
cap = dinfo->cfg.pcie.pcie_location;
if (cap == 0) {
if (width == 2)
return (0xffff);
return (0xffffffff);
}
old = pci_read_config(dev, cap + reg, width);
new = old & ~mask;
new |= (value & mask);
pci_write_config(dev, cap + reg, new, width);
return (old);
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/*
* Support for MSI message signalled interrupts.
*/
void
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_enable_msi_method(device_t dev, device_t child, uint64_t address,
uint16_t data)
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
{
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
struct pci_devinfo *dinfo = device_get_ivars(child);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msi *msi = &dinfo->cfg.msi;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* Write data and address values. */
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR,
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
address & 0xffffffff, 4);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH,
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
address >> 32, 4);
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT,
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
data, 2);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
} else
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data,
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
2);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* Enable MSI in the control register. */
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
msi->msi_ctrl, 2);
SATA device on some nForce based boards could get confused if MSI is not used but MSI to HyperTransport IRQ mapping is enabled, and would act as if MSI is turned on, resulting in interrupt loss. This commit will, 1. enable MSI mapping on a device only when MSI is enabled for that device and the MSI address matches the HT mapping window. 2. enable MSI mapping on a bridge only when a downstream device is allocated an MSI address in the mapping window PR: kern/118842 Reviewed by: jhb MFC after: 1 week
2008-07-23 09:44:36 +00:00
/* Enable MSI -> HT mapping. */
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_ht_map_msi(child, address);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
void
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_disable_msi_method(device_t dev, device_t child)
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
{
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
struct pci_devinfo *dinfo = device_get_ivars(child);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
struct pcicfg_msi *msi = &dinfo->cfg.msi;
SATA device on some nForce based boards could get confused if MSI is not used but MSI to HyperTransport IRQ mapping is enabled, and would act as if MSI is turned on, resulting in interrupt loss. This commit will, 1. enable MSI mapping on a device only when MSI is enabled for that device and the MSI address matches the HT mapping window. 2. enable MSI mapping on a bridge only when a downstream device is allocated an MSI address in the mapping window PR: kern/118842 Reviewed by: jhb MFC after: 1 week
2008-07-23 09:44:36 +00:00
/* Disable MSI -> HT mapping. */
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_ht_map_msi(child, 0);
SATA device on some nForce based boards could get confused if MSI is not used but MSI to HyperTransport IRQ mapping is enabled, and would act as if MSI is turned on, resulting in interrupt loss. This commit will, 1. enable MSI mapping on a device only when MSI is enabled for that device and the MSI address matches the HT mapping window. 2. enable MSI mapping on a bridge only when a downstream device is allocated an MSI address in the mapping window PR: kern/118842 Reviewed by: jhb MFC after: 1 week
2008-07-23 09:44:36 +00:00
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/* Disable MSI in the control register. */
msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
pci: make MSI(-X) enable and disable methods of the PCI bus Make the functions pci_disable_msi, pci_enable_msi and pci_enable_msix methods of the newbus PCI bus. This code should not include any functional change. Sponsored by: Citrix Systems R&D Reviewed by: imp, jhb Differential Revision: https://reviews.freebsd.org/D354 dev/pci/pci.c: - Convert the mentioned functions to newbus methods. - Fix the callers of the converted functions. sys/dev/pci/pci_private.h: dev/pci/pci_if.m: - Declare the new methods. dev/pci/pcivar.h: - Add helpers to call the newbus methods. ofed/include/linux/pci.h: - Add define to prevent the ofed version of pci_enable_msix from clashing with the FreeBSD native version.
2014-08-20 14:57:20 +00:00
pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
msi->msi_ctrl, 2);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/*
* Restore MSI registers during resume. If MSI is enabled then
* restore the data and address registers in addition to the control
* register.
*/
static void
pci_resume_msi(device_t dev)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msi *msi = &dinfo->cfg.msi;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
uint64_t address;
uint16_t data;
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
address = msi->msi_addr;
data = msi->msi_data;
pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
address & 0xffffffff, 4);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
pci_write_config(dev, msi->msi_location +
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
PCIR_MSI_ADDR_HIGH, address >> 32, 4);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
pci_write_config(dev, msi->msi_location +
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
PCIR_MSI_DATA_64BIT, data, 2);
} else
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
data, 2);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
}
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
2);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
}
Virtualize pci_remap_msi_irq() call from general MSI code. It allows MSI (FSB interrupts) to be used by non-PCI devices, such as HPET.
2010-06-14 07:10:37 +00:00
static int
pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
pcicfgregs *cfg = &dinfo->cfg;
struct resource_list_entry *rle;
struct msix_table_entry *mte;
struct msix_vector *mv;
uint64_t addr;
drop a bunch of white space at end of lines and end of files... -x -wb apparently doesn't hide end of file white space changes.. This is to reduce the amount of diff for my PCIe HP changes..
2015-10-18 08:13:51 +00:00
uint32_t data;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
int error, i, j;
/*
* Handle MSI first. We try to find this IRQ among our list
* of MSI IRQs. If we find it, we request updated address and
* data registers and apply the results.
*/
if (cfg->msi.msi_alloc > 0) {
/* If we don't have any active handlers, nothing to do. */
if (cfg->msi.msi_handlers == 0)
return (0);
for (i = 0; i < cfg->msi.msi_alloc; i++) {
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
i + 1);
if (rle->start == irq) {
error = PCIB_MAP_MSI(device_get_parent(bus),
dev, irq, &addr, &data);
if (error)
return (error);
pci_disable_msi(dev);
dinfo->cfg.msi.msi_addr = addr;
dinfo->cfg.msi.msi_data = data;
pci_enable_msi(dev, addr, data);
return (0);
}
}
return (ENOENT);
}
/*
* For MSI-X, we check to see if we have this IRQ. If we do,
* we request the updated mapping info. If that works, we go
* through all the slots that use this IRQ and update them.
*/
if (cfg->msix.msix_alloc > 0) {
for (i = 0; i < cfg->msix.msix_alloc; i++) {
mv = &cfg->msix.msix_vectors[i];
if (mv->mv_irq == irq) {
error = PCIB_MAP_MSI(device_get_parent(bus),
dev, irq, &addr, &data);
if (error)
return (error);
mv->mv_address = addr;
mv->mv_data = data;
for (j = 0; j < cfg->msix.msix_table_len; j++) {
mte = &cfg->msix.msix_table[j];
if (mte->mte_vector != i + 1)
continue;
if (mte->mte_handlers == 0)
continue;
pci_mask_msix(dev, j);
pci_enable_msix(dev, j, addr, data);
pci_unmask_msix(dev, j);
}
}
}
return (ENOENT);
}
return (ENOENT);
}
Add a first pass at a way to blacklist MSI on systems where it doesn't work: - A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table. - A new pci_msi_device_blacklisted() determines if a passed in device matches an MSI quirk in the quirk table. This can be overridden (all quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0. - A global blacklist check is performed in the MI PCI bus code by checking to see if the device at 0:0:0 is blacklisted. Tested by: jdp
2006-12-14 19:57:06 +00:00
/*
* Returns true if the specified device is blacklisted because MSI
* doesn't work.
*/
int
pci_msi_device_blacklisted(device_t dev)
{
if (!pci_honor_msi_blacklist)
return (0);
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI));
- Add a new PCI quirk to whitelist an old chipset that doesn't support PCI-express or PCI-X capabilities if we are running in a virtual machine. - Whitelist the Intel 82440 chipset used by QEMU. Tested by: jfv MFC after: 1 week
2010-10-22 11:42:02 +00:00
}
Add a first pass at a way to blacklist MSI on systems where it doesn't work: - A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table. - A new pci_msi_device_blacklisted() determines if a passed in device matches an MSI quirk in the quirk table. This can be overridden (all quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0. - A global blacklist check is performed in the MI PCI bus code by checking to see if the device at 0:0:0 is blacklisted. Tested by: jdp
2006-12-14 19:57:06 +00:00
/*
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
* Determine if MSI is blacklisted globally on this system. Currently,
Add a first pass at a way to blacklist MSI on systems where it doesn't work: - A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table. - A new pci_msi_device_blacklisted() determines if a passed in device matches an MSI quirk in the quirk table. This can be overridden (all quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0. - A global blacklist check is performed in the MI PCI bus code by checking to see if the device at 0:0:0 is blacklisted. Tested by: jdp
2006-12-14 19:57:06 +00:00
* we just check for blacklisted chipsets as represented by the
* host-PCI bridge at device 0:0:0. In the future, it may become
* necessary to check other system attributes, such as the kenv values
* that give the motherboard manufacturer and model number.
*/
static int
pci_msi_blacklisted(void)
{
device_t dev;
if (!pci_honor_msi_blacklist)
return (0);
Adjust the global MSI blacklisting strategy so we don't have to explicitly blacklist a bunch of old chipsets. If a system contains a PCI-PCI bridge that supports PCI-X, assume the chipset supports PCI-X. If a system contains a PCI-express root port, assume the chipset supports PCI-express. If the chipset doesn't support either PCI-X or PCI-express, then blacklist it by default. We should now only need to explicitly blacklist PCI-X or PCI-express chipsets that don't properly handle MSI.
2007-02-14 22:36:27 +00:00
/* Blacklist all non-PCI-express and non-PCI-X chipsets. */
- Add a new PCI quirk to whitelist an old chipset that doesn't support PCI-express or PCI-X capabilities if we are running in a virtual machine. - Whitelist the Intel 82440 chipset used by QEMU. Tested by: jfv MFC after: 1 week
2010-10-22 11:42:02 +00:00
if (!(pcie_chipset || pcix_chipset)) {
if (vm_guest != VM_GUEST_NO) {
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
/*
* Whitelist older chipsets in virtual
* machines known to support MSI.
*/
- Add a new PCI quirk to whitelist an old chipset that doesn't support PCI-express or PCI-X capabilities if we are running in a virtual machine. - Whitelist the Intel 82440 chipset used by QEMU. Tested by: jfv MFC after: 1 week
2010-10-22 11:42:02 +00:00
dev = pci_find_bsf(0, 0, 0);
if (dev != NULL)
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
return (!pci_has_quirk(pci_get_devid(dev),
PCI_QUIRK_ENABLE_MSI_VM));
- Add a new PCI quirk to whitelist an old chipset that doesn't support PCI-express or PCI-X capabilities if we are running in a virtual machine. - Whitelist the Intel 82440 chipset used by QEMU. Tested by: jfv MFC after: 1 week
2010-10-22 11:42:02 +00:00
}
Adjust the global MSI blacklisting strategy so we don't have to explicitly blacklist a bunch of old chipsets. If a system contains a PCI-PCI bridge that supports PCI-X, assume the chipset supports PCI-X. If a system contains a PCI-express root port, assume the chipset supports PCI-express. If the chipset doesn't support either PCI-X or PCI-express, then blacklist it by default. We should now only need to explicitly blacklist PCI-X or PCI-express chipsets that don't properly handle MSI.
2007-02-14 22:36:27 +00:00
return (1);
- Add a new PCI quirk to whitelist an old chipset that doesn't support PCI-express or PCI-X capabilities if we are running in a virtual machine. - Whitelist the Intel 82440 chipset used by QEMU. Tested by: jfv MFC after: 1 week
2010-10-22 11:42:02 +00:00
}
Adjust the global MSI blacklisting strategy so we don't have to explicitly blacklist a bunch of old chipsets. If a system contains a PCI-PCI bridge that supports PCI-X, assume the chipset supports PCI-X. If a system contains a PCI-express root port, assume the chipset supports PCI-express. If the chipset doesn't support either PCI-X or PCI-express, then blacklist it by default. We should now only need to explicitly blacklist PCI-X or PCI-express chipsets that don't properly handle MSI.
2007-02-14 22:36:27 +00:00
Add a first pass at a way to blacklist MSI on systems where it doesn't work: - A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table. - A new pci_msi_device_blacklisted() determines if a passed in device matches an MSI quirk in the quirk table. This can be overridden (all quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0. - A global blacklist check is performed in the MI PCI bus code by checking to see if the device at 0:0:0 is blacklisted. Tested by: jdp
2006-12-14 19:57:06 +00:00
dev = pci_find_bsf(0, 0, 0);
if (dev != NULL)
return (pci_msi_device_blacklisted(dev));
return (0);
}
- As it turns out, not only MSI-X is broken for devices passed through by VMware up to at least ESXi 5.1. Actually, using INTx in that case instead may still result in interrupt storms, with MSI being the only working option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk which only blacklists MSI-X but not also MSI and use it for the VMware PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't work, MSI-X won't work either - but that's part of the internal logic and not guaranteed as part of the API contract. While at it, add and employ a pci_has_quirk() helper. Reported and tested by: Paul Bucher - Use NULL instead of 0 for pointers. Submitted by: jhb (mostly) Approved by: jhb MFC after: 3 days
2013-07-09 23:12:26 +00:00
/*
* Returns true if the specified device is blacklisted because MSI-X
* doesn't work. Note that this assumes that if MSI doesn't work,
* MSI-X doesn't either.
*/
int
pci_msix_device_blacklisted(device_t dev)
{
if (!pci_honor_msi_blacklist)
return (0);
if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX))
return (1);
return (pci_msi_device_blacklisted(dev));
}
/*
* Determine if MSI-X is blacklisted globally on this system. If MSI
* is blacklisted, assume that MSI-X is as well. Check for additional
* chipsets where MSI works but MSI-X does not.
*/
static int
pci_msix_blacklisted(void)
{
device_t dev;
if (!pci_honor_msi_blacklist)
return (0);
dev = pci_find_bsf(0, 0, 0);
if (dev != NULL && pci_has_quirk(pci_get_devid(dev),
PCI_QUIRK_DISABLE_MSIX))
return (1);
return (pci_msi_blacklisted());
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/*
* Attempt to allocate *count MSI messages. The actual number allocated is
* returned in *count. After this function returns, each message will be
* available to the driver as SYS_RES_IRQ resources starting at a rid 1.
*/
int
pci_alloc_msi_method(device_t dev, device_t child, int *count)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
struct resource_list_entry *rle;
int actual, error, i, irqs[32];
uint16_t ctrl;
/* Don't let count == 0 get us into trouble. */
if (*count == 0)
return (EINVAL);
/* If rid 0 is allocated, then fail. */
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
if (rle != NULL && rle->res != NULL)
return (ENXIO);
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
/* Already have allocated messages? */
if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
return (ENXIO);
Add a first pass at a way to blacklist MSI on systems where it doesn't work: - A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table. - A new pci_msi_device_blacklisted() determines if a passed in device matches an MSI quirk in the quirk table. This can be overridden (all quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0. - A global blacklist check is performed in the MI PCI bus code by checking to see if the device at 0:0:0 is blacklisted. Tested by: jdp
2006-12-14 19:57:06 +00:00
/* If MSI is blacklisted for this system, fail. */
if (pci_msi_blacklisted())
return (ENXIO);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* MSI capability present? */
if (cfg->msi.msi_location == 0 || !pci_do_msi)
return (ENODEV);
Add some bootverbose printf's to detail how many MSI messages are allocated and to which IRQs. Requested by: scottl
2006-12-12 19:29:01 +00:00
if (bootverbose)
device_printf(child,
"attempting to allocate %d MSI vectors (%d supported)\n",
*count, cfg->msi.msi_msgnum);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* Don't ask for more than the device supports. */
actual = min(*count, cfg->msi.msi_msgnum);
/* Don't ask for more than 32 messages. */
actual = min(actual, 32);
/* MSI requires power of 2 number of messages. */
if (!powerof2(actual))
return (EINVAL);
for (;;) {
/* Try to allocate N messages. */
error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
Only align MSI message groups based on the number of messages being allocated, not the maximum number of messages the device supports. The spec only requires the former, and I believe I implemented the latter due to misunderstanding an e-mail. In particular, this fixes an issue where having several devices that all support 16 messages can run out of IDT vectors on x86 even though the driver only uses a single message. Submitted by: Bret Ketchum bcketchum of gmail MFC after: 1 week
2011-04-27 20:08:44 +00:00
actual, irqs);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
if (error == 0)
break;
if (actual == 1)
return (error);
/* Try N / 2. */
actual >>= 1;
}
/*
* We now have N actual messages mapped onto SYS_RES_IRQ
* resources in the irqs[] array, so add new resources
* starting at rid 1.
*/
for (i = 0; i < actual; i++)
resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
irqs[i], irqs[i], 1);
Add some bootverbose printf's to detail how many MSI messages are allocated and to which IRQs. Requested by: scottl
2006-12-12 19:29:01 +00:00
if (bootverbose) {
if (actual == 1)
device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
else {
int run;
/*
* Be fancy and try to print contiguous runs
* of IRQ values as ranges. 'run' is true if
* we are in a range.
*/
device_printf(child, "using IRQs %d", irqs[0]);
run = 0;
for (i = 1; i < actual; i++) {
/* Still in a run? */
if (irqs[i] == irqs[i - 1] + 1) {
run = 1;
continue;
}
/* Finish previous range. */
if (run) {
printf("-%d", irqs[i - 1]);
run = 0;
}
/* Start new range. */
printf(",%d", irqs[i]);
}
/* Unfinished range? */
if (run)
Fix a typo in a bootverbose printf. MFC after: 3 days Submitted by: yongari
2007-05-07 18:29:37 +00:00
printf("-%d", irqs[actual - 1]);
Add some bootverbose printf's to detail how many MSI messages are allocated and to which IRQs. Requested by: scottl
2006-12-12 19:29:01 +00:00
printf(" for MSI\n");
}
}
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
/* Update control register with actual count. */
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
ctrl = cfg->msi.msi_ctrl;
ctrl &= ~PCIM_MSICTRL_MME_MASK;
ctrl |= (ffs(actual) - 1) << 4;
cfg->msi.msi_ctrl = ctrl;
pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
/* Update counts of alloc'd messages. */
cfg->msi.msi_alloc = actual;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
cfg->msi.msi_handlers = 0;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
*count = actual;
return (0);
}
/* Release the MSI messages associated with this device. */
int
pci_release_msi_method(device_t dev, device_t child)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msi *msi = &dinfo->cfg.msi;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
struct resource_list_entry *rle;
int error, i, irqs[32];
/* Try MSI-X first. */
error = pci_release_msix(dev, child);
if (error != ENODEV)
return (error);
/* Do we have any messages to release? */
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
if (msi->msi_alloc == 0)
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
return (ENODEV);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* Make sure none of the resources are allocated. */
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
if (msi->msi_handlers > 0)
return (EBUSY);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
for (i = 0; i < msi->msi_alloc; i++) {
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
KASSERT(rle != NULL, ("missing MSI resource"));
if (rle->res != NULL)
return (EBUSY);
irqs[i] = rle->start;
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/* Update control register with 0 count. */
KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
("%s: MSI still enabled", __func__));
msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
msi->msi_ctrl, 2);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
/* Release the messages. */
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
for (i = 0; i < msi->msi_alloc; i++)
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
/* Update alloc count. */
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
msi->msi_alloc = 0;
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
msi->msi_addr = 0;
msi->msi_data = 0;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
return (0);
}
/*
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
* Return the max supported MSI messages this device supports.
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
* Basically, assuming the MD code can alloc messages, this function
Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support. - First off, device drivers really do need to know if they are allocating MSI or MSI-X messages. MSI requires allocating powerof2() messages for example where MSI-X does not. To address this, split out the MSI-X support from pci_msi_count() and pci_alloc_msi() into new driver-visible functions pci_msix_count() and pci_alloc_msix(). As a result, pci_msi_count() now just returns a count of the max supported MSI messages for the device, and pci_alloc_msi() only tries to allocate MSI messages. To get a count of the max supported MSI-X messages, use pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix(). pci_release_msi() still handles both MSI and MSI-X messages, however. As a result of this change, drivers using the existing API will only use MSI messages and will no longer try to use MSI-X messages. - Because MSI-X allows for each message to have its own data and address values (and thus does not require all of the messages to have their MD vectors allocated as a group), some devices allow for "sparse" use of MSI-X message slots. For example, if a device supports 8 messages but the OS is only able to allocate 2 messages, the device may make the best use of 2 IRQs if it enables the messages at slots 1 and 4 rather than default of using the first N slots (or indicies) at 1 and 2. To support this, add a new pci_remap_msix() function that a driver may call after a successful pci_alloc_msix() (but before allocating any of the SYS_RES_IRQ resources) to allow the allocated IRQ resources to be assigned to different message indices. For example, from the earlier example, after pci_alloc_msix() returned a value of 2, the driver would call pci_remap_msix() passing in array of integers { 1, 4 } as the new message indices to use. The rid's for the SYS_RES_IRQ resources will always match the message indices. Thus, after the call to pci_remap_msix() the driver would be able to access the first message in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based rather than 0-based so that they will always correspond to the rid values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt). To support this API, a new PCIB_REMAP_MSIX() method was added to the pcib interface to change the message index for a single IRQ. Tested by: scottl
2007-01-22 21:48:44 +00:00
* should return the maximum value that pci_alloc_msi() can return.
* Thus, it is subject to the tunables, etc.
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
*/
int
pci_msi_count_method(device_t dev, device_t child)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
struct pcicfg_msi *msi = &dinfo->cfg.msi;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
Use more specific local variable pointers to narrow some expressions. MFC after: 1 week
2007-05-02 16:21:18 +00:00
if (pci_do_msi && msi->msi_location != 0)
return (msi->msi_msgnum);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
return (0);
}
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
/* free pcicfgregs structure and all depending data structures */
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
int
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
pci_freecfg(struct pci_devinfo *dinfo)
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
{
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
struct devlist *devlist_head;
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
struct pci_map *pm, *next;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
int i;
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
devlist_head = &pci_devq;
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
if (dinfo->cfg.vpd.vpd_reg) {
free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
}
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
free(pm, M_DEVBUF);
}
Back out the previous change to the queue(3) interface. It was not discussed and should probably not happen. Requested by: msmith and others
2000-05-26 02:09:24 +00:00
STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
free(dinfo, M_DEVBUF);
/* increment the generation count */
pci_generation++;
/* we're losing one device */
pci_numdevs--;
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* . The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ... This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code. A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality: 1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device. The following features are currently missing, but will be added back, soon: 1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
return (0);
Completely new PCI code: 1) Supports PCI to PCI bridge devices (and tries to initialise them, even if the BIOS is brain dead). 2) Supports shared PCI interrupts. Interrupt handlers now MUST return '0' if they found nothing to do, '1' otherwise. New features tested with i486 systems based on the Intel Saturn and a DEC 4channel Ethernet card only, but expected to work on most systems. The option PCI_REMAP has been removed ! Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
}
Add support for ioctl() accesses to PCI config space registers. Garrett Wollman sent me this code a few weeks ago for review, and I made some significant changes, which he in turn accepted ... In order to make use of these changes, a device entry has to added to /dev. Submitted by: wollman
1996-10-22 20:20:14 +00:00
/*
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
* PCI power manangement
Add support for ioctl() accesses to PCI config space registers. Garrett Wollman sent me this code a few weeks ago for review, and I made some significant changes, which he in turn accepted ... In order to make use of these changes, a device entry has to added to /dev. Submitted by: wollman
1996-10-22 20:20:14 +00:00
*/
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
int
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
pci_set_powerstate_method(device_t dev, device_t child, int state)
Add support for ioctl() accesses to PCI config space registers. Garrett Wollman sent me this code a few weeks ago for review, and I made some significant changes, which he in turn accepted ... In order to make use of these changes, a device entry has to added to /dev. Submitted by: wollman
1996-10-22 20:20:14 +00:00
{
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
struct pci_devinfo *dinfo = device_get_ivars(child);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
pcicfgregs *cfg = &dinfo->cfg;
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint16_t status;
Remove several write-only variables, all reported by the gcc 4.9 buildkernel run. Some of them were write-only under some kernel options, e.g. variables keeping values only used by CTR() macros. It costs nothing to the code readability and correctness to eliminate the warnings in those cases too by removing the local cached values used only for single-access. Review: https://reviews.freebsd.org/D2665 Reviewed by: rodrigc Looked at by: bjk Sponsored by: The FreeBSD Foundation MFC after: 1 week
2015-05-29 13:24:17 +00:00
int oldstate, highest, delay;
Implement mimimum system software delays, per PCI PM 1.1 spec, as suggested by Peter Edwards. This seems to fix my fxp problems and likely will fix his as well. Use DELAY rather than *sleep because we can be called from any context.
2004-12-31 20:43:46 +00:00
if (cfg->pp.pp_cap == 0)
return (EOPNOTSUPP);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
Add system tunable to turn off power state changes. Default to off until we get the resource allocation stuff hammered out. Fix and off by one error that caused unnecessary filtering of valid BARs for only 4 bytes than ICH3 and other PCI IDE controllers have. Andrew Gallatin submitted this, although it doesn't solve the problems ICH3 controllers have with the new code, it does restore the former resource list on the probe line.
2004-04-11 07:02:49 +00:00
/*
Implement mimimum system software delays, per PCI PM 1.1 spec, as suggested by Peter Edwards. This seems to fix my fxp problems and likely will fix his as well. Use DELAY rather than *sleep because we can be called from any context.
2004-12-31 20:43:46 +00:00
* Optimize a no state change request away. While it would be OK to
* write to the hardware in theory, some devices have shown odd
* behavior when going from D3 -> D3.
Add system tunable to turn off power state changes. Default to off until we get the resource allocation stuff hammered out. Fix and off by one error that caused unnecessary filtering of valid BARs for only 4 bytes than ICH3 and other PCI IDE controllers have. Andrew Gallatin submitted this, although it doesn't solve the problems ICH3 controllers have with the new code, it does restore the former resource list on the probe line.
2004-04-11 07:02:49 +00:00
*/
Implement mimimum system software delays, per PCI PM 1.1 spec, as suggested by Peter Edwards. This seems to fix my fxp problems and likely will fix his as well. Use DELAY rather than *sleep because we can be called from any context.
2004-12-31 20:43:46 +00:00
oldstate = pci_get_powerstate(child);
if (oldstate == state)
Add system tunable to turn off power state changes. Default to off until we get the resource allocation stuff hammered out. Fix and off by one error that caused unnecessary filtering of valid BARs for only 4 bytes than ICH3 and other PCI IDE controllers have. Andrew Gallatin submitted this, although it doesn't solve the problems ICH3 controllers have with the new code, it does restore the former resource list on the probe line.
2004-04-11 07:02:49 +00:00
return (0);
Implement mimimum system software delays, per PCI PM 1.1 spec, as suggested by Peter Edwards. This seems to fix my fxp problems and likely will fix his as well. Use DELAY rather than *sleep because we can be called from any context.
2004-12-31 20:43:46 +00:00
/*
* The PCI power management specification states that after a state
* transition between PCI power states, system software must
* guarantee a minimal delay before the function accesses the device.
* Compute the worst case delay that we need to guarantee before we
* access the device. Many devices will be responsive much more
* quickly than this delay, but there are some that don't respond
* instantly to state changes. Transitions to/from D3 state require
* 10ms, while D2 requires 200us, and D0/1 require none. The delay
* is done below with DELAY rather than a sleeper function because
* this function can be called from contexts where we cannot sleep.
*/
highest = (oldstate > state) ? oldstate : state;
Fix last second typos that crept in :-(.
2004-12-31 23:59:24 +00:00
if (highest == PCI_POWERSTATE_D3)
Implement mimimum system software delays, per PCI PM 1.1 spec, as suggested by Peter Edwards. This seems to fix my fxp problems and likely will fix his as well. Use DELAY rather than *sleep because we can be called from any context.
2004-12-31 20:43:46 +00:00
delay = 10000;
Fix last second typos that crept in :-(.
2004-12-31 23:59:24 +00:00
else if (highest == PCI_POWERSTATE_D2)
Implement mimimum system software delays, per PCI PM 1.1 spec, as suggested by Peter Edwards. This seems to fix my fxp problems and likely will fix his as well. Use DELAY rather than *sleep because we can be called from any context.
2004-12-31 20:43:46 +00:00
delay = 200;
else
delay = 0;
status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
& ~PCIM_PSTAT_DMASK;
switch (state) {
case PCI_POWERSTATE_D0:
status |= PCIM_PSTAT_D0;
break;
case PCI_POWERSTATE_D1:
if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
return (EOPNOTSUPP);
status |= PCIM_PSTAT_D1;
break;
case PCI_POWERSTATE_D2:
if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
return (EOPNOTSUPP);
status |= PCIM_PSTAT_D2;
break;
case PCI_POWERSTATE_D3:
status |= PCIM_PSTAT_D3;
break;
default:
return (EINVAL);
On the new Meteor cards, the Philips SAA 7116 is connected to the PCI bus via an IBM PCI-PCI bridge (82351 or 82352 or 82353) The driver must identify if it is on a secondary PCI bus, which is created via the IBM PCI-PCI bridge. If it is, then it must initialise the IBM PCI-PCI bridge correctly. To do this, the following new functions are added. Because they use the pcici_t tag, they are considered 2.2 compatibility APIs pcici_t * pci_get_parent_from_tag(pcici_t tag); int pci_get_bus_from_tag(pcici_t tag); (The _from_tag suffix is used to prevent clashes with similarly named newbus PCI API functions) Submitted by: Anton Berezin <tobez@plab.ku.dk> Reviewed by: Doug Rabson <dfr@nlsystems.com> Reworked by: Me (roger)
1999-05-31 22:13:37 +00:00
}
move the statement about switching power states to just before we do it, so we don't print a false statement if the destination powerstate is unsupported...
2005-04-01 16:22:50 +00:00
if (bootverbose)
Add an internal pci_printf() routine similar to device_printf() except that it prefixes the output with 'pci<domain>:<bus>:<device>:<function>: '.
2009-06-01 20:30:00 +00:00
pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
state);
move the statement about switching power states to just before we do it, so we don't print a false statement if the destination powerstate is unsupported...
2005-04-01 16:22:50 +00:00
Implement mimimum system software delays, per PCI PM 1.1 spec, as suggested by Peter Edwards. This seems to fix my fxp problems and likely will fix his as well. Use DELAY rather than *sleep because we can be called from any context.
2004-12-31 20:43:46 +00:00
PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
if (delay)
DELAY(delay);
return (0);
On the new Meteor cards, the Philips SAA 7116 is connected to the PCI bus via an IBM PCI-PCI bridge (82351 or 82352 or 82353) The driver must identify if it is on a secondary PCI bus, which is created via the IBM PCI-PCI bridge. If it is, then it must initialise the IBM PCI-PCI bridge correctly. To do this, the following new functions are added. Because they use the pcici_t tag, they are considered 2.2 compatibility APIs pcici_t * pci_get_parent_from_tag(pcici_t tag); int pci_get_bus_from_tag(pcici_t tag); (The _from_tag suffix is used to prevent clashes with similarly named newbus PCI API functions) Submitted by: Anton Berezin <tobez@plab.ku.dk> Reviewed by: Doug Rabson <dfr@nlsystems.com> Reworked by: Me (roger)
1999-05-31 22:13:37 +00:00
}
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
int
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
pci_get_powerstate_method(device_t dev, device_t child)
Add support for ioctl() accesses to PCI config space registers. Garrett Wollman sent me this code a few weeks ago for review, and I made some significant changes, which he in turn accepted ... In order to make use of these changes, a device entry has to added to /dev. Submitted by: wollman
1996-10-22 20:20:14 +00:00
{
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
struct pci_devinfo *dinfo = device_get_ivars(child);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
pcicfgregs *cfg = &dinfo->cfg;
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint16_t status;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
int result;
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
if (cfg->pp.pp_cap != 0) {
status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
switch (status & PCIM_PSTAT_DMASK) {
case PCIM_PSTAT_D0:
result = PCI_POWERSTATE_D0;
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
break;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
case PCIM_PSTAT_D1:
result = PCI_POWERSTATE_D1;
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
break;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
case PCIM_PSTAT_D2:
result = PCI_POWERSTATE_D2;
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
break;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
case PCIM_PSTAT_D3:
result = PCI_POWERSTATE_D3;
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
break;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
default:
result = PCI_POWERSTATE_UNKNOWN;
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
break;
}
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
} else {
/* No support, device is always at D0 */
result = PCI_POWERSTATE_D0;
}
Implement mimimum system software delays, per PCI PM 1.1 spec, as suggested by Peter Edwards. This seems to fix my fxp problems and likely will fix his as well. Use DELAY rather than *sleep because we can be called from any context.
2004-12-31 20:43:46 +00:00
return (result);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
}
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
/*
* Some convenience functions for PCI device drivers.
*/
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
static __inline void
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
{
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint16_t command;
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
command |= bit;
PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
}
Revive PCIConf. Submitted by: "Kenneth D. Merry" <ken@plutotech.com>
1998-09-15 08:21:13 +00:00
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
static __inline void
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
{
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint16_t command;
Add support for ioctl() accesses to PCI config space registers. Garrett Wollman sent me this code a few weeks ago for review, and I made some significant changes, which he in turn accepted ... In order to make use of these changes, a device entry has to added to /dev. Submitted by: wollman
1996-10-22 20:20:14 +00:00
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
command &= ~bit;
PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
}
Add PCI LKM support.
1997-01-21 23:23:40 +00:00
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
int
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
pci_enable_busmaster_method(device_t dev, device_t child)
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
{
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
return (0);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
}
Add support for ioctl() accesses to PCI config space registers. Garrett Wollman sent me this code a few weeks ago for review, and I made some significant changes, which he in turn accepted ... In order to make use of these changes, a device entry has to added to /dev. Submitted by: wollman
1996-10-22 20:20:14 +00:00
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
int
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
pci_disable_busmaster_method(device_t dev, device_t child)
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
{
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
return (0);
Add support for ioctl() accesses to PCI config space registers. Garrett Wollman sent me this code a few weeks ago for review, and I made some significant changes, which he in turn accepted ... In order to make use of these changes, a device entry has to added to /dev. Submitted by: wollman
1996-10-22 20:20:14 +00:00
}
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
int
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
pci_enable_io_method(device_t dev, device_t child, int space)
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
{
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint16_t bit;
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
switch(space) {
case SYS_RES_IOPORT:
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
bit = PCIM_CMD_PORTEN;
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
break;
case SYS_RES_MEMORY:
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
bit = PCIM_CMD_MEMEN;
break;
default:
return (EINVAL);
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
}
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
pci_set_command_bit(dev, child, bit);
Don't reread the command register to see if enabling I/O or memory decoding "took". Other OS's that I checked do not do this and it breaks some amdpm(4) devices. Prior to 7.2 we did not honor the error returned when this failed anyway, so this in effect restores previous behavior. PR: kern/137668 Tested by: Aurelien Mere aurelien.mere amc-os.com MFC after: 3 days
2009-09-22 15:43:03 +00:00
return (0);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
}
Add support for ioctl() accesses to PCI config space registers. Garrett Wollman sent me this code a few weeks ago for review, and I made some significant changes, which he in turn accepted ... In order to make use of these changes, a device entry has to added to /dev. Submitted by: wollman
1996-10-22 20:20:14 +00:00
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
int
Slightly reimplement some recently added helper functions as methods, so that drivers are not reaching into the internals of the pci bus. There are no driver changes, the public interface is the same.
2001-02-27 23:13:20 +00:00
pci_disable_io_method(device_t dev, device_t child, int space)
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
{
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint16_t bit;
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
switch(space) {
case SYS_RES_IOPORT:
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
bit = PCIM_CMD_PORTEN;
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
break;
case SYS_RES_MEMORY:
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
bit = PCIM_CMD_MEMEN;
break;
default:
return (EINVAL);
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
}
Return status for PCI methods '{enable,disable}_{io,busmaster}'. Reviewed by: imp
2003-04-16 03:15:08 +00:00
pci_clear_command_bit(dev, child, bit);
return (0);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
}
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
/*
* New style pci driver. Parent device is either a pci-host-bridge or a
* pci-pci-bridge. Both kinds are represented by instances of pcib.
*/
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
void
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
pci_print_verbose(struct pci_devinfo *dinfo)
{
provide routines to access VPD data at the PCI layer... remove sk's own implementation, and use the new calls to get the data... Reviewed by: -arch
2006-10-09 16:15:56 +00:00
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
if (bootverbose) {
pcicfgregs *cfg = &dinfo->cfg;
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
cfg->vendor, cfg->device, cfg->revid);
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
cfg->domain, cfg->bus, cfg->slot, cfg->func);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
cfg->mfdev);
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
if (cfg->intpin > 0)
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
printf("\tintpin=%c, irq=%d\n",
cfg->intpin +'a' -1, cfg->intline);
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
if (cfg->pp.pp_cap) {
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint16_t status;
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
cfg->pp.pp_cap & PCIM_PCAP_SPEC,
cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
status & PCIM_PSTAT_DMASK);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
if (cfg->msi.msi_location) {
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
int ctrl;
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
ctrl = cfg->msi.msi_ctrl;
Teach the PCI code to parse MSI extended capabilities. Re-arrange the pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
printf("\tMSI supports %d message%s%s%s\n",
cfg->msi.msi_msgnum,
(cfg->msi.msi_msgnum == 1) ? "" : "s",
(ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
(ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
}
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
if (cfg->msix.msix_location) {
printf("\tMSI-X supports %d message%s ",
cfg->msix.msix_msgnum,
(cfg->msix.msix_msgnum == 1) ? "" : "s");
if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
printf("in map 0x%x\n",
cfg->msix.msix_table_bar);
else
printf("in maps 0x%x and 0x%x\n",
cfg->msix.msix_table_bar,
cfg->msix.msix_pba_bar);
}
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
}
}
static int
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_porten(device_t dev)
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
{
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
}
static int
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_memen(device_t dev)
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
{
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
}
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
void
pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp,
int *bar64)
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
{
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
struct pci_devinfo *dinfo;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_addr_t map, testval;
int ln2range;
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint16_t cmd;
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
/*
* The device ROM BAR is special. It is always a 32-bit
* memory BAR. Bit 0 is special and should not be set when
* sizing the BAR.
*/
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
dinfo = device_get_ivars(dev);
if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
map = pci_read_config(dev, reg, 4);
pci_write_config(dev, reg, 0xfffffffe, 4);
testval = pci_read_config(dev, reg, 4);
pci_write_config(dev, reg, map, 4);
*mapp = map;
*testvalp = testval;
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
if (bar64 != NULL)
*bar64 = 0;
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
return;
}
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
map = pci_read_config(dev, reg, 4);
Always read/write the full 64-bit value of 64-bit BARs. Specifically, when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
2009-03-05 15:33:04 +00:00
ln2range = pci_maprange(map);
if (ln2range == 64)
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
Disable decoding of BARs by devices before we trash the value in the BAR by writing all 1's to it to determine its length. This fixes issues with MCFG on at least some machines where a trashed BAR claimed subsequent attempts at PCI config transactions because the addresses in the MCFG window fell in the decoding range of the BAR. In general it is a bad idea to leave the BARs enabled while we are frobbing with them in this manner. Sleuthing by: tegge MFC after: 1 week
2009-01-16 22:22:30 +00:00
/*
* Disable decoding via the command register before
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
* determining the BAR's length since we will be placing it in
* a weird state.
Disable decoding of BARs by devices before we trash the value in the BAR by writing all 1's to it to determine its length. This fixes issues with MCFG on at least some machines where a trashed BAR claimed subsequent attempts at PCI config transactions because the addresses in the MCFG window fell in the decoding range of the BAR. In general it is a bad idea to leave the BARs enabled while we are frobbing with them in this manner. Sleuthing by: tegge MFC after: 1 week
2009-01-16 22:22:30 +00:00
*/
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND,
Disable decoding of BARs by devices before we trash the value in the BAR by writing all 1's to it to determine its length. This fixes issues with MCFG on at least some machines where a trashed BAR claimed subsequent attempts at PCI config transactions because the addresses in the MCFG window fell in the decoding range of the BAR. In general it is a bad idea to leave the BARs enabled while we are frobbing with them in this manner. Sleuthing by: tegge MFC after: 1 week
2009-01-16 22:22:30 +00:00
cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
/*
* Determine the BAR's length by writing all 1's. The bottom
* log_2(size) bits of the BAR will stick as 0 when we read
* the value back.
pci: fix write order when sizing BARs According to the PCI Local Specification rev. 3.0 in case of a 64-bit BAR both the low and the high parts of the register should be set to ~0 before attempting to read back the size. So far I have found no single device that has problems with the previous approach, but I think it's better to stay on the safe size. This commit should not introduce any functional change. MFC after: 3 weeks Sponsored by: Citrix Systems R&D Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D11750
2017-08-01 10:47:44 +00:00
*
* NB: according to the PCI Local Bus Specification, rev. 3.0:
* "Software writes 0FFFFFFFFh to both registers, reads them back,
* and combines the result into a 64-bit value." (section 6.2.5.1)
*
* Writes to both registers must be performed before attempting to
* read back the size value.
Disable decoding of BARs by devices before we trash the value in the BAR by writing all 1's to it to determine its length. This fixes issues with MCFG on at least some machines where a trashed BAR claimed subsequent attempts at PCI config transactions because the addresses in the MCFG window fell in the decoding range of the BAR. In general it is a bad idea to leave the BARs enabled while we are frobbing with them in this manner. Sleuthing by: tegge MFC after: 1 week
2009-01-16 22:22:30 +00:00
*/
pci: fix write order when sizing BARs According to the PCI Local Specification rev. 3.0 in case of a 64-bit BAR both the low and the high parts of the register should be set to ~0 before attempting to read back the size. So far I have found no single device that has problems with the previous approach, but I think it's better to stay on the safe size. This commit should not introduce any functional change. MFC after: 3 weeks Sponsored by: Citrix Systems R&D Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D11750
2017-08-01 10:47:44 +00:00
testval = 0;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_write_config(dev, reg, 0xffffffff, 4);
Always read/write the full 64-bit value of 64-bit BARs. Specifically, when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
2009-03-05 15:33:04 +00:00
if (ln2range == 64) {
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_write_config(dev, reg + 4, 0xffffffff, 4);
testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
Always read/write the full 64-bit value of 64-bit BARs. Specifically, when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
2009-03-05 15:33:04 +00:00
}
pci: fix write order when sizing BARs According to the PCI Local Specification rev. 3.0 in case of a 64-bit BAR both the low and the high parts of the register should be set to ~0 before attempting to read back the size. So far I have found no single device that has problems with the previous approach, but I think it's better to stay on the safe size. This commit should not introduce any functional change. MFC after: 3 weeks Sponsored by: Citrix Systems R&D Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D11750
2017-08-01 10:47:44 +00:00
testval |= pci_read_config(dev, reg, 4);
Disable decoding of BARs by devices before we trash the value in the BAR by writing all 1's to it to determine its length. This fixes issues with MCFG on at least some machines where a trashed BAR claimed subsequent attempts at PCI config transactions because the addresses in the MCFG window fell in the decoding range of the BAR. In general it is a bad idea to leave the BARs enabled while we are frobbing with them in this manner. Sleuthing by: tegge MFC after: 1 week
2009-01-16 22:22:30 +00:00
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
/*
* Restore the original value of the BAR. We may have reprogrammed
* the BAR of the low-level console device and when booting verbose,
* we need the console device addressable.
*/
pci_write_config(dev, reg, map, 4);
Always read/write the full 64-bit value of 64-bit BARs. Specifically, when determining the size of a BAR by writing all 1's to the BAR and reading back the result, always operate on the full 64-bit size. Reviewed by: imp MFC after: 1 month
2009-03-05 15:33:04 +00:00
if (ln2range == 64)
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_write_config(dev, reg + 4, map >> 32, 4);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
*mapp = map;
*testvalp = testval;
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
if (bar64 != NULL)
*bar64 = (ln2range == 64);
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
}
static void
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
{
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
struct pci_devinfo *dinfo;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
int ln2range;
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
/* The device ROM BAR is always a 32-bit memory BAR. */
dinfo = device_get_ivars(dev);
if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
ln2range = 32;
else
ln2range = pci_maprange(pm->pm_value);
pci_write_config(dev, pm->pm_reg, base, 4);
if (ln2range == 64)
pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
if (ln2range == 64)
Minor whitespace and style fixes.
2011-06-21 19:31:31 +00:00
pm->pm_value |= (pci_addr_t)pci_read_config(dev,
pm->pm_reg + 4, 4) << 32;
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
}
struct pci_map *
pci_find_bar(device_t dev, int reg)
{
struct pci_devinfo *dinfo;
struct pci_map *pm;
dinfo = device_get_ivars(dev);
STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
if (pm->pm_reg == reg)
return (pm);
}
return (NULL);
}
int
pci_bar_enabled(device_t dev, struct pci_map *pm)
{
struct pci_devinfo *dinfo;
uint16_t cmd;
dinfo = device_get_ivars(dev);
if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
!(pm->pm_value & PCIM_BIOS_ENABLE))
return (0);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
return ((cmd & PCIM_CMD_MEMEN) != 0);
else
return ((cmd & PCIM_CMD_PORTEN) != 0);
}
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
struct pci_map *
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
{
struct pci_devinfo *dinfo;
struct pci_map *pm, *prev;
dinfo = device_get_ivars(dev);
pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
pm->pm_reg = reg;
pm->pm_value = value;
pm->pm_size = size;
STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
reg));
if (STAILQ_NEXT(prev, pm_link) == NULL ||
STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
break;
}
if (prev != NULL)
STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
else
STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
return (pm);
}
static void
pci_restore_bars(device_t dev)
{
struct pci_devinfo *dinfo;
struct pci_map *pm;
int ln2range;
dinfo = device_get_ivars(dev);
STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
ln2range = 32;
else
ln2range = pci_maprange(pm->pm_value);
pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
if (ln2range == 64)
pci_write_config(dev, pm->pm_reg + 4,
pm->pm_value >> 32, 4);
}
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
}
/*
* Add a resource based on a pci map register. Return 1 if the map
* register is a 32bit map register or 2 if it is a 64bit register.
*/
static int
pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
int force, int prefetch)
{
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
struct pci_map *pm;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_addr_t base, map, testval;
pci_addr_t start, end, count;
Properly set the alignment flags when allocating the initial range for a BAR. This only really matters when pci_do_realloc_bars is enabled and the initial allocation of a specific range fails. MFC after: 1 week
2014-02-05 19:24:16 +00:00
int barlen, basezero, flags, maprange, mapsize, type;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
uint16_t cmd;
struct resource *res;
More properly handle Cardbus cards that that store their CIS in a BAR after the recent changes to track BAR state explicitly. The code would now attempt to add the same BAR twice in this case. Instead, change this so that it recognizes this case and only adds it once and do not delete the BAR outright after parsing the CIS. Tested by: bschmidt
2011-06-06 13:21:11 +00:00
/*
* The BAR may already exist if the device is a CardBus card
* whose CIS is stored in this BAR.
*/
pm = pci_find_bar(dev, reg);
if (pm != NULL) {
maprange = pci_maprange(pm->pm_value);
barlen = maprange == 64 ? 2 : 1;
return (barlen);
}
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
pci_read_bar(dev, reg, &map, &testval, NULL);
Honor the prefetchable flag in memory BARs by setting the RF_PREFETCHABLE flag when calling bus_alloc_resource() to allocate resources from a parent PCI bridge. For PCI-PCI bridges this asks the bridge to satisfy the request using the prefetchable memory range rather than the normal memory range. Reviewed by: imp Reported by: scottl MFC after: 1 week
2009-03-05 15:28:46 +00:00
if (PCI_BAR_MEM(map)) {
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
type = SYS_RES_MEMORY;
Honor the prefetchable flag in memory BARs by setting the RF_PREFETCHABLE flag when calling bus_alloc_resource() to allocate resources from a parent PCI bridge. For PCI-PCI bridges this asks the bridge to satisfy the request using the prefetchable memory range rather than the normal memory range. Reviewed by: imp Reported by: scottl MFC after: 1 week
2009-03-05 15:28:46 +00:00
if (map & PCIM_BAR_MEM_PREFETCH)
prefetch = 1;
} else
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
type = SYS_RES_IOPORT;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
mapsize = pci_mapsize(testval);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
base = pci_mapbase(map);
Add a MD __PCI_BAR_ZERO_VALID which denotes that BARs containing 0 actually specify valid bases that should be treated just as normal. The PCI specifications have no indication that 0 would be a magic value indicating a disabled BAR as commonly used on at least amd64 and i386 but not sparc64. It's unclear what to do in pci_delete_resource() instead of writing 0 to a BAR though as there's no (other) way do disable individual BARs so its decoding is left enabled in case of __PCI_BAR_ZERO_VALID for now. Approved by: re (kib), jhb MFC after: 1 week
2009-07-21 19:06:39 +00:00
#ifdef __PCI_BAR_ZERO_VALID
basezero = 0;
#else
basezero = base == 0;
#endif
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
maprange = pci_maprange(map);
barlen = maprange == 64 ? 2 : 1;
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
/*
* For I/O registers, if bottom bit is set, and the next bit up
* isn't clear, we know we have a BAR that doesn't conform to the
* spec, so ignore it. Also, sanity check the size of the data
Add system tunable to turn off power state changes. Default to off until we get the resource allocation stuff hammered out. Fix and off by one error that caused unnecessary filtering of valid BARs for only 4 bytes than ICH3 and other PCI IDE controllers have. Andrew Gallatin submitted this, although it doesn't solve the problems ICH3 controllers have with the new code, it does restore the former resource list on the probe line.
2004-04-11 07:02:49 +00:00
* areas to the type of memory involved. Memory must be at least
The size of I/O ranges can be anything from 16 bytes to 2G bytes. Lower the minimum for memory mapped I/O from 32 bytes to 16 bytes. This fixes bus enumeration on ia64 now that the Diva auxiliary serial port is attached to.
2006-04-27 04:53:18 +00:00
* 16 bytes in size, while I/O ranges must be at least 4.
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
*/
Add constants for the fields in a BAR. Also, add two new macros PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR is for an IO or memory BAR, respectively. Reviewed by: imp
2007-03-31 21:39:02 +00:00
if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
More consistantly return the correct BAR size. Before, we'd only return the correct bar size if we encountered a 64-bit BAR that had its resources already assigned. If the resources weren't yet assigned, we'd bogusly assume it was a 32-bit bar and return 1.
2005-09-03 23:15:46 +00:00
return (barlen);
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
if ((type == SYS_RES_MEMORY && mapsize < 4) ||
(type == SYS_RES_IOPORT && mapsize < 2))
More consistantly return the correct BAR size. Before, we'd only return the correct bar size if we encountered a 64-bit BAR that had its resources already assigned. If the resources weren't yet assigned, we'd bogusly assume it was a 32-bit bar and return 1.
2005-09-03 23:15:46 +00:00
return (barlen);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
/* Save a record of this BAR. */
pm = pci_add_bar(dev, reg, map, mapsize);
Print the PCI resources even if they are disabled. This shows more clearly when the BIOS is forgetful about initialising the USB controllers.
2000-03-18 19:18:36 +00:00
if (bootverbose) {
Add constants for the fields in a BAR. Also, add two new macros PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR is for an IO or memory BAR, respectively. Reviewed by: imp
2007-03-31 21:39:02 +00:00
printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
if (type == SYS_RES_IOPORT && !pci_porten(dev))
Print the PCI resources even if they are disabled. This shows more clearly when the BIOS is forgetful about initialising the USB controllers.
2000-03-18 19:18:36 +00:00
printf(", port disabled\n");
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
else if (type == SYS_RES_MEMORY && !pci_memen(dev))
Print the PCI resources even if they are disabled. This shows more clearly when the BIOS is forgetful about initialising the USB controllers.
2000-03-18 19:18:36 +00:00
printf(", memory disabled\n");
else
printf(", enabled\n");
}
Unconditionally turning on the I/O and memory enable bits in the PCI command register is too aggressive. Revert to the previous behaviour, but leave the new behaviour available as an undocumented option. It's not clear what the Right, Right Thing is to do here, but the more conservative approach is safer.
2000-10-28 23:07:13 +00:00
Don't enable I/O or memory mode in a device's command register if the BAR we are processing has a base address of zero. Note that this will only change behavior for devices where all the BARs of a given type have a base address of 0 since we will enable the appropriate access when we encounter the first BAR with a base that is not 0. Specifically, this allows certain Toshiba laptops to no longer require 'hw.pci.enable_io_modes=0' to avoid hangs during boot. PR: kern/20040 PR: i386/63776 (possibly) PR: i386/68900 (possibly) PR: i386/74532 (possibly) MFC after: 1 week
2005-05-31 21:33:33 +00:00
/*
Add a MD __PCI_BAR_ZERO_VALID which denotes that BARs containing 0 actually specify valid bases that should be treated just as normal. The PCI specifications have no indication that 0 would be a magic value indicating a disabled BAR as commonly used on at least amd64 and i386 but not sparc64. It's unclear what to do in pci_delete_resource() instead of writing 0 to a BAR though as there's no (other) way do disable individual BARs so its decoding is left enabled in case of __PCI_BAR_ZERO_VALID for now. Approved by: re (kib), jhb MFC after: 1 week
2009-07-21 19:06:39 +00:00
* If base is 0, then we have problems if this architecture does
* not allow that. It is best to ignore such entries for the
* moment. These will be allocated later if the driver specifically
"Buses" is the preferred plural of "bus" Replace archaic "busses" with modern form "buses." Intentionally excluded: * Old/random drivers I didn't recognize * Old hardware in general * Use of "busses" in code as identifiers No functional change. http://grammarist.com/spelling/buses-busses/ PR: 216099 Reported by: bltsrc at mail.ru Sponsored by: Dell EMC Isilon
2017-01-15 17:54:01 +00:00
* requests them. However, some removable buses look better when
Add a MD __PCI_BAR_ZERO_VALID which denotes that BARs containing 0 actually specify valid bases that should be treated just as normal. The PCI specifications have no indication that 0 would be a magic value indicating a disabled BAR as commonly used on at least amd64 and i386 but not sparc64. It's unclear what to do in pci_delete_resource() instead of writing 0 to a BAR though as there's no (other) way do disable individual BARs so its decoding is left enabled in case of __PCI_BAR_ZERO_VALID for now. Approved by: re (kib), jhb MFC after: 1 week
2009-07-21 19:06:39 +00:00
* all resources are allocated, so allow '0' to be overriden.
Treat resources that are 0xfffff.... as being 'unassigned'. Reviewed by: jhb Tested by: Mark Kirkwood MFC After: 3 days
2005-09-01 02:42:34 +00:00
*
Typo in comment.
2005-09-01 16:41:42 +00:00
* Similarly treat maps whose values is the same as the test value
Treat resources that are 0xfffff.... as being 'unassigned'. Reviewed by: jhb Tested by: Mark Kirkwood MFC After: 3 days
2005-09-01 02:42:34 +00:00
* read back. These maps have had all f's written to them by the
* BIOS in an attempt to disable the resources.
Don't enable I/O or memory mode in a device's command register if the BAR we are processing has a base address of zero. Note that this will only change behavior for devices where all the BARs of a given type have a base address of 0 since we will enable the appropriate access when we encounter the first BAR with a base that is not 0. Specifically, this allows certain Toshiba laptops to no longer require 'hw.pci.enable_io_modes=0' to avoid hangs during boot. PR: kern/20040 PR: i386/63776 (possibly) PR: i386/68900 (possibly) PR: i386/74532 (possibly) MFC after: 1 week
2005-05-31 21:33:33 +00:00
*/
Add a MD __PCI_BAR_ZERO_VALID which denotes that BARs containing 0 actually specify valid bases that should be treated just as normal. The PCI specifications have no indication that 0 would be a magic value indicating a disabled BAR as commonly used on at least amd64 and i386 but not sparc64. It's unclear what to do in pci_delete_resource() instead of writing 0 to a BAR though as there's no (other) way do disable individual BARs so its decoding is left enabled in case of __PCI_BAR_ZERO_VALID for now. Approved by: re (kib), jhb MFC after: 1 week
2009-07-21 19:06:39 +00:00
if (!force && (basezero || map == testval))
More consistantly return the correct BAR size. Before, we'd only return the correct bar size if we encountered a 64-bit BAR that had its resources already assigned. If the resources weren't yet assigned, we'd bogusly assume it was a 32-bit bar and return 1.
2005-09-03 23:15:46 +00:00
return (barlen);
More fully support 64-bit bars. Prior to this commit, we supported only those bars that had addresses assigned by the BIOS and where the bridges were properly programmed. Now even unprogrammed ones work. This was needed for sun4v. We still only implement up to 2GB memory ranges, even for 64-bit bars. PCI standards at least through 2.2 say that this is the max (or 1GB is, I only know it is < 32bits). o Always define pci_addr_t as uint64_t. A pci address is always 64-bits, but some hosts can't address all of them. o Preserve the upper half of the 64-bit word during resource probing. o Test to make sure that 64-bit values can fit in a u_long (true on some platforms, but not others). Don't use those that can't. o minor pedantry about data sizes. o Better bridge resource reporting in bootverbose case. o Minor formatting changes to cope with different data types on different platforms. Submitted by: jmg, with many changes by me to fully support 64-bit addresses.
2006-10-30 19:18:46 +00:00
if ((u_long)base != base) {
device_printf(bus,
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
"pci%d:%d:%d:%d bar %#x too many address bits",
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
pci_get_function(dev), reg);
More fully support 64-bit bars. Prior to this commit, we supported only those bars that had addresses assigned by the BIOS and where the bridges were properly programmed. Now even unprogrammed ones work. This was needed for sun4v. We still only implement up to 2GB memory ranges, even for 64-bit bars. PCI standards at least through 2.2 say that this is the max (or 1GB is, I only know it is < 32bits). o Always define pci_addr_t as uint64_t. A pci address is always 64-bits, but some hosts can't address all of them. o Preserve the upper half of the 64-bit word during resource probing. o Test to make sure that 64-bit values can fit in a u_long (true on some platforms, but not others). Don't use those that can't. o minor pedantry about data sizes. o Better bridge resource reporting in bootverbose case. o Minor formatting changes to cope with different data types on different platforms. Submitted by: jmg, with many changes by me to fully support 64-bit addresses.
2006-10-30 19:18:46 +00:00
return (barlen);
}
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
Unconditionally turning on the I/O and memory enable bits in the PCI command register is too aggressive. Revert to the previous behaviour, but leave the new behaviour available as an undocumented option. It's not clear what the Right, Right Thing is to do here, but the more conservative approach is safer.
2000-10-28 23:07:13 +00:00
/*
* This code theoretically does the right thing, but has
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
* undesirable side effects in some cases where peripherals
* respond oddly to having these bits enabled. Let the user
* be able to turn them off (since pci_enable_io_modes is 1 by
* default).
Unconditionally turning on the I/O and memory enable bits in the PCI command register is too aggressive. Revert to the previous behaviour, but leave the new behaviour available as an undocumented option. It's not clear what the Right, Right Thing is to do here, but the more conservative approach is safer.
2000-10-28 23:07:13 +00:00
*/
Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
2002-07-26 07:58:16 +00:00
if (pci_enable_io_modes) {
/* Turn on resources that have been left off by a lazy BIOS */
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
2002-07-26 07:58:16 +00:00
cmd |= PCIM_CMD_PORTEN;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
2002-07-26 07:58:16 +00:00
}
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
2002-07-26 07:58:16 +00:00
cmd |= PCIM_CMD_MEMEN;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
Make PCI_ENABLE_IO_MODES a sysctl hw.pci.enable_io_modes. It can also be set at boot time. It defaults to 1 now since it can be set in the boot loader. If this proves unwise, we can reset it to defaulting to 0.
2002-07-26 07:58:16 +00:00
}
} else {
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
if (type == SYS_RES_IOPORT && !pci_porten(dev))
More consistantly return the correct BAR size. Before, we'd only return the correct bar size if we encountered a 64-bit BAR that had its resources already assigned. If the resources weren't yet assigned, we'd bogusly assume it was a 32-bit bar and return 1.
2005-09-03 23:15:46 +00:00
return (barlen);
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
if (type == SYS_RES_MEMORY && !pci_memen(dev))
More consistantly return the correct BAR size. Before, we'd only return the correct bar size if we encountered a 64-bit BAR that had its resources already assigned. If the resources weren't yet assigned, we'd bogusly assume it was a 32-bit bar and return 1.
2005-09-03 23:15:46 +00:00
return (barlen);
If a base address register has been set up by the BIOS, but the relevant enable bit hasn't been set in the command register, set the bit and honour the register. It seems that quite a few lazy BIOS writers aren't bothering to do this, which upsets the existing code and causes us to miss out on properly-configured devices.
2000-09-01 23:09:02 +00:00
}
Do not pre-allocate resources for BAR's on ATA MASTERDEV's thats on the standard ATA primary and secondary addresses. Reintroduce the size 1 ALTIO space so that we can have both ATA and floppies back working.
2004-04-20 20:57:29 +00:00
Properly handle BARs bigger than 4G. The '1' was treated as an int causing the size calculation to be truncated to the size of an int (32-bits on all current architectures). Submitted by: Anish akgupt3 of gmail MFC after: 1 week
2011-02-23 12:58:50 +00:00
count = (pci_addr_t)1 << mapsize;
Properly set the alignment flags when allocating the initial range for a BAR. This only really matters when pci_do_realloc_bars is enabled and the initial allocation of a specific range fails. MFC after: 1 week
2014-02-05 19:24:16 +00:00
flags = RF_ALIGNMENT_LOG2(mapsize);
if (prefetch)
flags |= RF_PREFETCHABLE;
Add two tunables to ignore certain firmware-assigned resources. These are mostly useful for debugging. - hw.pci.clear_bars ignores all firmware-assigned ranges for BARs when set. - hw.pci.clear_pcib ignores all firmware-assigned ranges for PCI-PCI bridge I/O windows when set. MFC after: 1 week
2014-02-05 20:52:12 +00:00
if (basezero || base == pci_mapbase(testval) || pci_clear_bars) {
If the kernel fails to allocate resources for the initial value of a BAR for a PCI device during the boot-time probe of the parent PCI bus, then zero the BAR and clear the resource list entry for that BAR. This forces the PCI bus driver to request a valid resource range from the parent bridge driver when the device driver tries to allocate the BAR. Similarly, if the initial value of a BAR is a valid range but it is > 4GB and the current OS only has 32-bit longs, then do a full teardown of the initial value of the BAR to force a reallocation. Reviewed by: imp MFC after: 1 week
2008-08-05 18:24:41 +00:00
start = 0; /* Let the parent decide. */
Replace all resource occurrences of '0UL/~0UL' with '0/~0'. Summary: The idea behind this is '~0ul' is well-defined, and casting to uintmax_t, on a 32-bit platform, will leave the upper 32 bits as 0. The maximum range of a resource is 0xFFF.... (all bits of the full type set). By dropping the 'ul' suffix, C type promotion rules apply, and the sign extension of ~0 on 32 bit platforms gets it to a type-independent 'unsigned max'. Reviewed By: cem Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5255
2016-03-03 05:07:35 +00:00
end = ~0;
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
} else {
start = base;
Properly handle BARs bigger than 4G. The '1' was treated as an int causing the size calculation to be truncated to the size of an int (32-bits on all current architectures). Submitted by: Anish akgupt3 of gmail MFC after: 1 week
2011-02-23 12:58:50 +00:00
end = base + count - 1;
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
}
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
resource_list_add(rl, type, reg, start, end, count);
* Implement bus_set/get/delete_resource for pci. * Change the hack used on the alpha for mapping devices into DENSE or BWX memory spaces to a simpler one. Its still a hack and should be a seperate api to explicitly map the resource. * Add $FreeBSD$ as necessary.
1999-10-14 21:38:33 +00:00
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
/*
If the kernel fails to allocate resources for the initial value of a BAR for a PCI device during the boot-time probe of the parent PCI bus, then zero the BAR and clear the resource list entry for that BAR. This forces the PCI bus driver to request a valid resource range from the parent bridge driver when the device driver tries to allocate the BAR. Similarly, if the initial value of a BAR is a valid range but it is > 4GB and the current OS only has 32-bit longs, then do a full teardown of the initial value of the BAR to force a reallocation. Reviewed by: imp MFC after: 1 week
2008-08-05 18:24:41 +00:00
* Try to allocate the resource for this BAR from our parent
* so that this resource range is already reserved. The
* driver for this device will later inherit this resource in
* pci_alloc_resource().
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
*/
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
res = resource_list_reserve(rl, bus, dev, type, &reg, start, end, count,
Properly set the alignment flags when allocating the initial range for a BAR. This only really matters when pci_do_realloc_bars is enabled and the initial allocation of a specific range fails. MFC after: 1 week
2014-02-05 19:24:16 +00:00
flags);
Work around BIOS quirks on HPE Proliant MicroServer Gen10 PR: 221350 Submitted by: Bob Bishop Reported by: Rafal Lukawiecki Reviewed by: jhb MFC after: 2 weeks
2018-12-17 07:09:46 +00:00
if ((pci_do_realloc_bars
|| pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR))
&& res == NULL && (start != 0 || end != ~0)) {
Revision 233677 broke certain machines. Specifically, if the firmware/BIOS assigned conflicting ranges to BARs then leaving the BARs alone could result in one device stealing mmio accesses intended to go to a second device. Prior to 233677 the PCI bus driver attempted to handle this case by clearing the BAR to 0 depending on BARs based at 0 not decoding (which is not guaranteed to be true). Now when a conflicting BAR is detected the following steps are taken: 1) If hw.pci.realloc_bars (a new tunable) is enabled (default is enabled), then ignore the current BAR setting from the firmware and attempt to allocate a fresh resource range for the BAR. 2) If 1) failed (or was disabled), disable decoding for the relevant BAR type (e.g. disable mem decoding for a memory BAR) and emit a warning if booting verbose. Tested by: Alex Keda <admin@lissyara.su> MFC after: 1 week
2013-05-09 19:24:50 +00:00
/*
* If the allocation fails, try to allocate a resource for
* this BAR using any available range. The firmware felt
* it was important enough to assign a resource, so don't
* disable decoding if we can help it.
*/
resource_list_delete(rl, type, reg);
Replace all resource occurrences of '0UL/~0UL' with '0/~0'. Summary: The idea behind this is '~0ul' is well-defined, and casting to uintmax_t, on a 32-bit platform, will leave the upper 32 bits as 0. The maximum range of a resource is 0xFFF.... (all bits of the full type set). By dropping the 'ul' suffix, C type promotion rules apply, and the sign extension of ~0 on 32 bit platforms gets it to a type-independent 'unsigned max'. Reviewed By: cem Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5255
2016-03-03 05:07:35 +00:00
resource_list_add(rl, type, reg, 0, ~0, count);
res = resource_list_reserve(rl, bus, dev, type, &reg, 0, ~0,
Properly set the alignment flags when allocating the initial range for a BAR. This only really matters when pci_do_realloc_bars is enabled and the initial allocation of a specific range fails. MFC after: 1 week
2014-02-05 19:24:16 +00:00
count, flags);
Revision 233677 broke certain machines. Specifically, if the firmware/BIOS assigned conflicting ranges to BARs then leaving the BARs alone could result in one device stealing mmio accesses intended to go to a second device. Prior to 233677 the PCI bus driver attempted to handle this case by clearing the BAR to 0 depending on BARs based at 0 not decoding (which is not guaranteed to be true). Now when a conflicting BAR is detected the following steps are taken: 1) If hw.pci.realloc_bars (a new tunable) is enabled (default is enabled), then ignore the current BAR setting from the firmware and attempt to allocate a fresh resource range for the BAR. 2) If 1) failed (or was disabled), disable decoding for the relevant BAR type (e.g. disable mem decoding for a memory BAR) and emit a warning if booting verbose. Tested by: Alex Keda <admin@lissyara.su> MFC after: 1 week
2013-05-09 19:24:50 +00:00
}
If the kernel fails to allocate resources for the initial value of a BAR for a PCI device during the boot-time probe of the parent PCI bus, then zero the BAR and clear the resource list entry for that BAR. This forces the PCI bus driver to request a valid resource range from the parent bridge driver when the device driver tries to allocate the BAR. Similarly, if the initial value of a BAR is a valid range but it is > 4GB and the current OS only has 32-bit longs, then do a full teardown of the initial value of the BAR to force a reallocation. Reviewed by: imp MFC after: 1 week
2008-08-05 18:24:41 +00:00
if (res == NULL) {
/*
Revert r233662 and generalize the hack. Writing zero to BAR actually does not disable it and it is even harmful as hselasky found out. Historically, this code was originated from (OLDCARD) CardBus driver and later leaked into PCI driver when CardBus was newbus'ified and refactored with PCI driver. However, it is not really necessary even for CardBus. Reviewed by: hselasky, imp, jhb
2012-03-29 19:26:39 +00:00
* If the allocation fails, delete the resource list entry
Revision 233677 broke certain machines. Specifically, if the firmware/BIOS assigned conflicting ranges to BARs then leaving the BARs alone could result in one device stealing mmio accesses intended to go to a second device. Prior to 233677 the PCI bus driver attempted to handle this case by clearing the BAR to 0 depending on BARs based at 0 not decoding (which is not guaranteed to be true). Now when a conflicting BAR is detected the following steps are taken: 1) If hw.pci.realloc_bars (a new tunable) is enabled (default is enabled), then ignore the current BAR setting from the firmware and attempt to allocate a fresh resource range for the BAR. 2) If 1) failed (or was disabled), disable decoding for the relevant BAR type (e.g. disable mem decoding for a memory BAR) and emit a warning if booting verbose. Tested by: Alex Keda <admin@lissyara.su> MFC after: 1 week
2013-05-09 19:24:50 +00:00
* and disable decoding for this device.
*
* If the driver requests this resource in the future,
* pci_reserve_map() will try to allocate a fresh
* resource range.
If the kernel fails to allocate resources for the initial value of a BAR for a PCI device during the boot-time probe of the parent PCI bus, then zero the BAR and clear the resource list entry for that BAR. This forces the PCI bus driver to request a valid resource range from the parent bridge driver when the device driver tries to allocate the BAR. Similarly, if the initial value of a BAR is a valid range but it is > 4GB and the current OS only has 32-bit longs, then do a full teardown of the initial value of the BAR to force a reallocation. Reviewed by: imp MFC after: 1 week
2008-08-05 18:24:41 +00:00
*/
resource_list_delete(rl, type, reg);
Revision 233677 broke certain machines. Specifically, if the firmware/BIOS assigned conflicting ranges to BARs then leaving the BARs alone could result in one device stealing mmio accesses intended to go to a second device. Prior to 233677 the PCI bus driver attempted to handle this case by clearing the BAR to 0 depending on BARs based at 0 not decoding (which is not guaranteed to be true). Now when a conflicting BAR is detected the following steps are taken: 1) If hw.pci.realloc_bars (a new tunable) is enabled (default is enabled), then ignore the current BAR setting from the firmware and attempt to allocate a fresh resource range for the BAR. 2) If 1) failed (or was disabled), disable decoding for the relevant BAR type (e.g. disable mem decoding for a memory BAR) and emit a warning if booting verbose. Tested by: Alex Keda <admin@lissyara.su> MFC after: 1 week
2013-05-09 19:24:50 +00:00
pci_disable_io(dev, type);
if (bootverbose)
device_printf(bus,
"pci%d:%d:%d:%d bar %#x failed to allocate\n",
pci_get_domain(dev), pci_get_bus(dev),
pci_get_slot(dev), pci_get_function(dev), reg);
Revert r233662 and generalize the hack. Writing zero to BAR actually does not disable it and it is even harmful as hselasky found out. Historically, this code was originated from (OLDCARD) CardBus driver and later leaked into PCI driver when CardBus was newbus'ified and refactored with PCI driver. However, it is not really necessary even for CardBus. Reviewed by: hselasky, imp, jhb
2012-03-29 19:26:39 +00:00
} else {
If the kernel fails to allocate resources for the initial value of a BAR for a PCI device during the boot-time probe of the parent PCI bus, then zero the BAR and clear the resource list entry for that BAR. This forces the PCI bus driver to request a valid resource range from the parent bridge driver when the device driver tries to allocate the BAR. Similarly, if the initial value of a BAR is a valid range but it is > 4GB and the current OS only has 32-bit longs, then do a full teardown of the initial value of the BAR to force a reallocation. Reviewed by: imp MFC after: 1 week
2008-08-05 18:24:41 +00:00
start = rman_get_start(res);
Revert r233662 and generalize the hack. Writing zero to BAR actually does not disable it and it is even harmful as hselasky found out. Historically, this code was originated from (OLDCARD) CardBus driver and later leaked into PCI driver when CardBus was newbus'ified and refactored with PCI driver. However, it is not really necessary even for CardBus. Reviewed by: hselasky, imp, jhb
2012-03-29 19:26:39 +00:00
pci_write_bar(dev, pm, start);
}
More consistantly return the correct BAR size. Before, we'd only return the correct bar size if we encountered a 64-bit BAR that had its resources already assigned. If the resources weren't yet assigned, we'd bogusly assume it was a 32-bit bar and return 1.
2005-09-03 23:15:46 +00:00
return (barlen);
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
}
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
/*
Update the special handling code for ATA devices to allow usage of PCI native addressing. That means that if the HW says that using "real" addresses instead of the hardwired legacy compat ones is allowed, we will use them.
2004-06-29 20:25:43 +00:00
* For ATA devices we need to decide early what addressing mode to use.
* Legacy demands that the primary and secondary ATA ports sits on the
* same addresses that old ISA hardware did. This dictates that we use
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
* those addresses and ignore the BAR's if we cannot set PCI native
Update the special handling code for ATA devices to allow usage of PCI native addressing. That means that if the HW says that using "real" addresses instead of the hardwired legacy compat ones is allowed, we will use them.
2004-06-29 20:25:43 +00:00
* addressing mode.
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
*/
static void
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
uint32_t prefetchmask)
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
{
Update the special handling code for ATA devices to allow usage of PCI native addressing. That means that if the HW says that using "real" addresses instead of the hardwired legacy compat ones is allowed, we will use them.
2004-06-29 20:25:43 +00:00
int rid, type, progif;
Disable native ata support for now, too much breaks
2004-07-02 13:42:36 +00:00
#if 0
Update the special handling code for ATA devices to allow usage of PCI native addressing. That means that if the HW says that using "real" addresses instead of the hardwired legacy compat ones is allowed, we will use them.
2004-06-29 20:25:43 +00:00
/* if this device supports PCI native addressing use it */
progif = pci_read_config(dev, PCIR_PROGIF, 1);
if ((progif & 0x8a) == 0x8a) {
if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
printf("Trying ATA native PCI addressing mode\n");
pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
}
}
#endif
progif = pci_read_config(dev, PCIR_PROGIF, 1);
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
type = SYS_RES_IOPORT;
Update the special handling code for ATA devices to allow usage of PCI native addressing. That means that if the HW says that using "real" addresses instead of the hardwired legacy compat ones is allowed, we will use them.
2004-06-29 20:25:43 +00:00
if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
prefetchmask & (1 << 0));
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
prefetchmask & (1 << 1));
Minor style(9) nitage.
2005-10-28 05:56:50 +00:00
} else {
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
rid = PCIR_BAR(0);
resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
Remove several write-only variables, all reported by the gcc 4.9 buildkernel run. Some of them were write-only under some kernel options, e.g. variables keeping values only used by CTR() macros. It costs nothing to the code readability and correctness to eliminate the warnings in those cases too by removing the local cached values used only for single-access. Review: https://reviews.freebsd.org/D2665 Reviewed by: rodrigc Looked at by: bjk Sponsored by: The FreeBSD Foundation MFC after: 1 week
2015-05-29 13:24:17 +00:00
(void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
0x1f7, 8, 0);
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
rid = PCIR_BAR(1);
resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
Remove several write-only variables, all reported by the gcc 4.9 buildkernel run. Some of them were write-only under some kernel options, e.g. variables keeping values only used by CTR() macros. It costs nothing to the code readability and correctness to eliminate the warnings in those cases too by removing the local cached values used only for single-access. Review: https://reviews.freebsd.org/D2665 Reviewed by: rodrigc Looked at by: bjk Sponsored by: The FreeBSD Foundation MFC after: 1 week
2015-05-29 13:24:17 +00:00
(void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
0x3f6, 1, 0);
Update the special handling code for ATA devices to allow usage of PCI native addressing. That means that if the HW says that using "real" addresses instead of the hardwired legacy compat ones is allowed, we will use them.
2004-06-29 20:25:43 +00:00
}
if (progif & PCIP_STORAGE_IDE_MODESEC) {
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
prefetchmask & (1 << 2));
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
prefetchmask & (1 << 3));
Minor style(9) nitage.
2005-10-28 05:56:50 +00:00
} else {
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
rid = PCIR_BAR(2);
resource_list_add(rl, type, rid, 0x170, 0x177, 8);
Remove several write-only variables, all reported by the gcc 4.9 buildkernel run. Some of them were write-only under some kernel options, e.g. variables keeping values only used by CTR() macros. It costs nothing to the code readability and correctness to eliminate the warnings in those cases too by removing the local cached values used only for single-access. Review: https://reviews.freebsd.org/D2665 Reviewed by: rodrigc Looked at by: bjk Sponsored by: The FreeBSD Foundation MFC after: 1 week
2015-05-29 13:24:17 +00:00
(void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
0x177, 8, 0);
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
rid = PCIR_BAR(3);
resource_list_add(rl, type, rid, 0x376, 0x376, 1);
Remove several write-only variables, all reported by the gcc 4.9 buildkernel run. Some of them were write-only under some kernel options, e.g. variables keeping values only used by CTR() macros. It costs nothing to the code readability and correctness to eliminate the warnings in those cases too by removing the local cached values used only for single-access. Review: https://reviews.freebsd.org/D2665 Reviewed by: rodrigc Looked at by: bjk Sponsored by: The FreeBSD Foundation MFC after: 1 week
2015-05-29 13:24:17 +00:00
(void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
0x376, 1, 0);
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
}
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
prefetchmask & (1 << 4));
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
prefetchmask & (1 << 5));
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
}
- Consolidate duplicated code for assigning interrupts to PCI devices via routing, etc. in a static pci_assign_interrupt() function. - Add a sledgehammer that allows the user to override the interrupt assignment of any PCI device via a tunable (e.g. "hw.pci0.7.INTB=5" would force any functions on the pci device in slot 7 of bus 0 that use B# to use IRQ 5). This should be used with great caution! Generally, if the interrupt routing in use provides specific tunables (such as hard-wiring the IRQ for a given $PIR or ACPI PCI link device), then those should be used instead. One instance where this tunable might be useful is if a box has an MPTable with duplicate entries for the same PCI device with different IRQs. MFC after: 1 week
2005-09-29 15:04:41 +00:00
static void
pci_assign_interrupt(device_t bus, device_t dev, int force_route)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
pcicfgregs *cfg = &dinfo->cfg;
char tunable_name[64];
int irq;
/* Has to have an intpin to have an interrupt. */
if (cfg->intpin == 0)
return;
/* Let the user override the IRQ with a tunable. */
irq = PCI_INVALID_IRQ;
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
snprintf(tunable_name, sizeof(tunable_name),
"hw.pci%d.%d.%d.INT%c.irq",
cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
- Consolidate duplicated code for assigning interrupts to PCI devices via routing, etc. in a static pci_assign_interrupt() function. - Add a sledgehammer that allows the user to override the interrupt assignment of any PCI device via a tunable (e.g. "hw.pci0.7.INTB=5" would force any functions on the pci device in slot 7 of bus 0 that use B# to use IRQ 5). This should be used with great caution! Generally, if the interrupt routing in use provides specific tunables (such as hard-wiring the IRQ for a given $PIR or ACPI PCI link device), then those should be used instead. One instance where this tunable might be useful is if a box has an MPTable with duplicate entries for the same PCI device with different IRQs. MFC after: 1 week
2005-09-29 15:04:41 +00:00
if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
irq = PCI_INVALID_IRQ;
/*
* If we didn't get an IRQ via the tunable, then we either use the
* IRQ value in the intline register or we ask the bus to route an
* interrupt for us. If force_route is true, then we only use the
* value in the intline register if the bus was unable to assign an
* IRQ.
*/
if (!PCI_INTERRUPT_VALID(irq)) {
if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
irq = PCI_ASSIGN_INTERRUPT(bus, dev);
if (!PCI_INTERRUPT_VALID(irq))
irq = cfg->intline;
}
/* If after all that we don't have an IRQ, just bail. */
if (!PCI_INTERRUPT_VALID(irq))
return;
/* Update the config register if it changed. */
if (irq != cfg->intline) {
cfg->intline = irq;
pci_write_config(dev, PCIR_INTLINE, irq, 1);
}
/* Add this IRQ as rid 0 interrupt resource. */
resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
}
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
/* Perform early OHCI takeover from SMM. */
static void
ohci_early_takeover(device_t self)
{
struct resource *res;
uint32_t ctl;
int rid;
int i;
rid = PCIR_BAR(0);
res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (res == NULL)
return;
ctl = bus_read_4(res, OHCI_CONTROL);
if (ctl & OHCI_IR) {
if (bootverbose)
printf("ohci early: "
"SMM active, request owner change\n");
bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
DELAY(1000);
ctl = bus_read_4(res, OHCI_CONTROL);
}
if (ctl & OHCI_IR) {
if (bootverbose)
printf("ohci early: "
"SMM does not respond, resetting\n");
bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
}
Disable interrupts after doing early takeover of the usb controller in case usb isnt actually compiled in (or kldloaded) as the controller could cause spurious interrupts. Tested by: Florian Smeets
2009-11-25 20:50:43 +00:00
/* Disable interrupts */
bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
}
bus_release_resource(self, SYS_RES_MEMORY, rid, res);
}
/* Perform early UHCI takeover from SMM. */
static void
uhci_early_takeover(device_t self)
{
Disable interrupts after doing early takeover of the usb controller in case usb isnt actually compiled in (or kldloaded) as the controller could cause spurious interrupts. Tested by: Florian Smeets
2009-11-25 20:50:43 +00:00
struct resource *res;
int rid;
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
/*
* Set the PIRQD enable bit and switch off all the others. We don't
* want legacy support to interfere with us XXX Does this also mean
* that the BIOS won't touch the keyboard anymore if it is connected
* to the ports of the root hub?
*/
pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
Disable interrupts after doing early takeover of the usb controller in case usb isnt actually compiled in (or kldloaded) as the controller could cause spurious interrupts. Tested by: Florian Smeets
2009-11-25 20:50:43 +00:00
/* Disable interrupts */
rid = PCI_UHCI_BASE_REG;
res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
if (res != NULL) {
bus_write_2(res, UHCI_INTR, 0);
bus_release_resource(self, SYS_RES_IOPORT, rid, res);
}
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
}
/* Perform early EHCI takeover from SMM. */
static void
ehci_early_takeover(device_t self)
{
struct resource *res;
uint32_t cparams;
uint32_t eec;
uint8_t eecp;
uint8_t bios_sem;
Disable interrupts after doing early takeover of the usb controller in case usb isnt actually compiled in (or kldloaded) as the controller could cause spurious interrupts. Tested by: Florian Smeets
2009-11-25 20:50:43 +00:00
uint8_t offs;
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
int rid;
int i;
rid = PCIR_BAR(0);
res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (res == NULL)
return;
cparams = bus_read_4(res, EHCI_HCCPARAMS);
/* Synchronise with the BIOS if it owns the controller. */
for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
eecp = EHCI_EECP_NEXT(eec)) {
eec = pci_read_config(self, eecp, 4);
if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
continue;
}
bios_sem = pci_read_config(self, eecp +
EHCI_LEGSUP_BIOS_SEM, 1);
if (bios_sem == 0) {
continue;
}
if (bootverbose)
printf("ehci early: "
"SMM active, request owner change\n");
pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
for (i = 0; (i < 100) && (bios_sem != 0); i++) {
DELAY(1000);
bios_sem = pci_read_config(self, eecp +
EHCI_LEGSUP_BIOS_SEM, 1);
}
if (bios_sem != 0) {
if (bootverbose)
printf("ehci early: "
"SMM does not respond\n");
}
Disable interrupts after doing early takeover of the usb controller in case usb isnt actually compiled in (or kldloaded) as the controller could cause spurious interrupts. Tested by: Florian Smeets
2009-11-25 20:50:43 +00:00
/* Disable interrupts */
The EHCI_CAPLENGTH and EHCI_HCIVERSION registers are actually sub-registers within the first 4 bytes of the EHCI memory space. For controllers that use big-endian MMIO, reading them with 1- and 2-byte reads would then return the wrong values. Instead, read the combined register with a 4-byte read and mask out the interesting quantities.
2010-10-25 15:51:43 +00:00
offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
Disable interrupts after doing early takeover of the usb controller in case usb isnt actually compiled in (or kldloaded) as the controller could cause spurious interrupts. Tested by: Florian Smeets
2009-11-25 20:50:43 +00:00
bus_write_4(res, offs + EHCI_USBINTR, 0);
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
}
bus_release_resource(self, SYS_RES_MEMORY, rid, res);
}
Add missing XHCI early takeover code. The XHCI takeover code is supposed to disable the BIOS from using the XHCI controller after bootup. Approved by: re (kib) Reported by: Mike Tancsa MFC after: 1 week
2011-07-22 15:37:23 +00:00
/* Perform early XHCI takeover from SMM. */
static void
xhci_early_takeover(device_t self)
{
struct resource *res;
uint32_t cparams;
uint32_t eec;
uint8_t eecp;
uint8_t bios_sem;
uint8_t offs;
int rid;
int i;
rid = PCIR_BAR(0);
res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (res == NULL)
return;
cparams = bus_read_4(res, XHCI_HCSPARAMS0);
eec = -1;
/* Synchronise with the BIOS if it owns the controller. */
for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
eecp += XHCI_XECP_NEXT(eec) << 2) {
eec = bus_read_4(res, eecp);
if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
continue;
bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
if (bios_sem == 0)
continue;
if (bootverbose)
printf("xhci early: "
"SMM active, request owner change\n");
bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
/* wait a maximum of 5 second */
for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
DELAY(1000);
bios_sem = bus_read_1(res, eecp +
XHCI_XECP_BIOS_SEM);
}
if (bios_sem != 0) {
if (bootverbose)
printf("xhci early: "
"SMM does not respond\n");
}
/* Disable interrupts */
offs = bus_read_1(res, XHCI_CAPLENGTH);
bus_write_4(res, offs + XHCI_USBCMD, 0);
bus_read_4(res, offs + XHCI_USBSTS);
}
bus_release_resource(self, SYS_RES_MEMORY, rid, res);
}
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
static void
pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg,
struct resource_list *rl)
{
struct resource *res;
char *cp;
Convert rman to use rman_res_t instead of u_long Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075
2016-01-27 02:23:54 +00:00
rman_res_t start, end, count;
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus;
switch (cfg->hdrtype & PCIM_HDRTYPE) {
case PCIM_HDRTYPE_BRIDGE:
sec_reg = PCIR_SECBUS_1;
sub_reg = PCIR_SUBBUS_1;
break;
case PCIM_HDRTYPE_CARDBUS:
sec_reg = PCIR_SECBUS_2;
sub_reg = PCIR_SUBBUS_2;
break;
default:
return;
}
/*
* If the existing bus range is valid, attempt to reserve it
* from our parent. If this fails for any reason, clear the
* secbus and subbus registers.
*
* XXX: Should we reset sub_bus to sec_bus if it is < sec_bus?
* This would at least preserve the existing sec_bus if it is
* valid.
*/
sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1);
sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1);
/* Quirk handling. */
switch (pci_get_devid(dev)) {
case 0x12258086: /* Intel 82454KX/GX (Orion) */
sup_bus = pci_read_config(dev, 0x41, 1);
if (sup_bus != 0xff) {
sec_bus = sup_bus + 1;
sub_bus = sup_bus + 1;
PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1);
PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
}
break;
case 0x00dd10de:
/* Compaq R3000 BIOS sets wrong subordinate bus number. */
Follow up to r225617. In order to maximize the re-usability of kernel code in userland rename in-kernel getenv()/setenv() to kern_setenv()/kern_getenv(). This fixes a namespace collision with libc symbols. Submitted by: kmacy Tested by: make universe
2014-10-16 18:04:43 +00:00
if ((cp = kern_getenv("smbios.planar.maker")) == NULL)
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
break;
if (strncmp(cp, "Compal", 6) != 0) {
freeenv(cp);
break;
}
freeenv(cp);
Follow up to r225617. In order to maximize the re-usability of kernel code in userland rename in-kernel getenv()/setenv() to kern_setenv()/kern_getenv(). This fixes a namespace collision with libc symbols. Submitted by: kmacy Tested by: make universe
2014-10-16 18:04:43 +00:00
if ((cp = kern_getenv("smbios.planar.product")) == NULL)
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
break;
if (strncmp(cp, "08A0", 4) != 0) {
freeenv(cp);
break;
}
freeenv(cp);
if (sub_bus < 0xa) {
sub_bus = 0xa;
PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
}
break;
}
if (bootverbose)
printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus);
if (sec_bus > 0 && sub_bus >= sec_bus) {
start = sec_bus;
end = sub_bus;
count = end - start + 1;
Replace all resource occurrences of '0UL/~0UL' with '0/~0'. Summary: The idea behind this is '~0ul' is well-defined, and casting to uintmax_t, on a 32-bit platform, will leave the upper 32 bits as 0. The maximum range of a resource is 0xFFF.... (all bits of the full type set). By dropping the 'ul' suffix, C type promotion rules apply, and the sign extension of ~0 on 32 bit platforms gets it to a type-independent 'unsigned max'. Reviewed By: cem Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5255
2016-03-03 05:07:35 +00:00
resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count);
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
/*
* If requested, clear secondary bus registers in
* bridge devices to force a complete renumbering
* rather than reserving the existing range. However,
* preserve the existing size.
*/
if (pci_clear_buses)
goto clear;
rid = 0;
res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid,
start, end, count, 0);
if (res != NULL)
return;
if (bootverbose)
device_printf(bus,
"pci%d:%d:%d:%d secbus failed to allocate\n",
pci_get_domain(dev), pci_get_bus(dev),
pci_get_slot(dev), pci_get_function(dev));
}
clear:
PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1);
PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1);
}
static struct resource *
Convert rman to use rman_res_t instead of u_long Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075
2016-01-27 02:23:54 +00:00
pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start,
rman_res_t end, rman_res_t count, u_int flags)
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
{
struct pci_devinfo *dinfo;
pcicfgregs *cfg;
struct resource_list *rl;
struct resource *res;
int sec_reg, sub_reg;
dinfo = device_get_ivars(child);
cfg = &dinfo->cfg;
rl = &dinfo->resources;
switch (cfg->hdrtype & PCIM_HDRTYPE) {
case PCIM_HDRTYPE_BRIDGE:
sec_reg = PCIR_SECBUS_1;
sub_reg = PCIR_SUBBUS_1;
break;
case PCIM_HDRTYPE_CARDBUS:
sec_reg = PCIR_SECBUS_2;
sub_reg = PCIR_SUBBUS_2;
break;
default:
return (NULL);
}
if (*rid != 0)
return (NULL);
if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL)
resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count);
if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) {
res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid,
start, end, count, flags & ~RF_ACTIVE);
if (res == NULL) {
resource_list_delete(rl, PCI_RES_BUS, *rid);
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
device_printf(child, "allocating %ju bus%s failed\n",
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
count, count == 1 ? "" : "es");
return (NULL);
}
if (bootverbose)
device_printf(child,
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
"Lazy allocation of %ju bus%s at %ju\n", count,
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
count == 1 ? "" : "es", rman_get_start(res));
PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1);
PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1);
}
return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start,
end, count, flags));
}
#endif
Support for Enhanced Allocation in PCI On some platforms, BAR entries are hardcoded and must not be accessed using standard method. Add functionality to identify this situation and configure the bus based on Enhanced Allocation structure. Obtained from: Semihalf Sponsored by: Cavium Approved by: cognet (mentor) Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D5242
2016-03-02 09:54:58 +00:00
static int
pci_ea_bei_to_rid(device_t dev, int bei)
{
#ifdef PCI_IOV
struct pci_devinfo *dinfo;
int iov_pos;
struct pcicfg_iov *iov;
dinfo = device_get_ivars(dev);
iov = dinfo->cfg.iov;
if (iov != NULL)
iov_pos = iov->iov_pos;
else
iov_pos = 0;
#endif
/* Check if matches BAR */
if ((bei >= PCIM_EA_BEI_BAR_0) &&
(bei <= PCIM_EA_BEI_BAR_5))
return (PCIR_BAR(bei));
/* Check ROM */
if (bei == PCIM_EA_BEI_ROM)
return (PCIR_BIOS);
#ifdef PCI_IOV
/* Check if matches VF_BAR */
if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) &&
(bei <= PCIM_EA_BEI_VF_BAR_5))
return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) +
iov_pos);
#endif
return (-1);
}
int
pci_ea_is_enabled(device_t dev, int rid)
{
struct pci_ea_entry *ea;
struct pci_devinfo *dinfo;
dinfo = device_get_ivars(dev);
STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid)
return ((ea->eae_flags & PCIM_EA_ENABLE) > 0);
}
return (0);
}
void
pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov)
{
struct pci_ea_entry *ea;
struct pci_devinfo *dinfo;
pci_addr_t start, end, count;
struct resource_list *rl;
int type, flags, rid;
struct resource *res;
uint32_t tmp;
#ifdef PCI_IOV
struct pcicfg_iov *iov;
#endif
dinfo = device_get_ivars(dev);
rl = &dinfo->resources;
flags = 0;
#ifdef PCI_IOV
iov = dinfo->cfg.iov;
#endif
if (dinfo->cfg.ea.ea_location == 0)
return;
STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
/*
* TODO: Ignore EA-BAR if is not enabled.
* Currently the EA implementation supports
* only situation, where EA structure contains
* predefined entries. In case they are not enabled
* leave them unallocated and proceed with
* a legacy-BAR mechanism.
*/
if ((ea->eae_flags & PCIM_EA_ENABLE) == 0)
continue;
switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) {
case PCIM_EA_P_MEM_PREFETCH:
case PCIM_EA_P_VF_MEM_PREFETCH:
flags = RF_PREFETCHABLE;
PCI Enhanced Allocation: Annotate an intentional switch fallthrough This is a trivial follow-up to r296308. Annotate the intentional fallthrough to make it clear for future readers and linters. Reported by: Coverity CID: 1352716 Discussed with: jhb Sponsored by: EMC / Isilon Storage Division
2016-04-26 20:06:35 +00:00
/* FALLTHROUGH */
Support for Enhanced Allocation in PCI On some platforms, BAR entries are hardcoded and must not be accessed using standard method. Add functionality to identify this situation and configure the bus based on Enhanced Allocation structure. Obtained from: Semihalf Sponsored by: Cavium Approved by: cognet (mentor) Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D5242
2016-03-02 09:54:58 +00:00
case PCIM_EA_P_VF_MEM:
case PCIM_EA_P_MEM:
type = SYS_RES_MEMORY;
break;
case PCIM_EA_P_IO:
type = SYS_RES_IOPORT;
break;
default:
continue;
}
if (alloc_iov != 0) {
#ifdef PCI_IOV
/* Allocating IOV, confirm BEI matches */
if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) ||
(ea->eae_bei > PCIM_EA_BEI_VF_BAR_5))
continue;
#else
continue;
#endif
} else {
/* Allocating BAR, confirm BEI matches */
if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) ||
(ea->eae_bei > PCIM_EA_BEI_BAR_5)) &&
(ea->eae_bei != PCIM_EA_BEI_ROM))
continue;
}
rid = pci_ea_bei_to_rid(dev, ea->eae_bei);
if (rid < 0)
continue;
/* Skip resources already allocated by EA */
if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) ||
(resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL))
continue;
start = ea->eae_base;
count = ea->eae_max_offset + 1;
#ifdef PCI_IOV
if (iov != NULL)
count = count * iov->iov_num_vfs;
#endif
end = start + count - 1;
if (count == 0)
continue;
resource_list_add(rl, type, rid, start, end, count);
res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count,
flags);
if (res == NULL) {
resource_list_delete(rl, type, rid);
/*
* Failed to allocate using EA, disable entry.
* Another attempt to allocation will be performed
* further, but this time using legacy BAR registers
*/
tmp = pci_read_config(dev, ea->eae_cfg_offset, 4);
tmp &= ~PCIM_EA_ENABLE;
pci_write_config(dev, ea->eae_cfg_offset, tmp, 4);
/*
* Disabling entry might fail in case it is hardwired.
* Read flags again to match current status.
*/
ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4);
continue;
}
/* As per specification, fill BAR with zeros */
pci_write_config(dev, rid, 0, 4);
}
}
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
void
pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
{
Add a PCI quirk to ignore PCI map registers from configuration space. For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base address as a memory BAR for SMBus controller depending on a PM register configuration. Before r231161 (and r232086, subsequent MFC to stable/9), it was not fatal but hpet(4) just failed to attach. Since we probe and attach HPET earlier than PCI devices now, it caused unfortunate hard lockup. With this patch, it does not hang any more and HPET works at the same time. Clean up some style nits while I am in the neighborhood. PR: kern/165647 Reviewed by: jhb MFC after: 3 days
2012-03-14 23:25:46 +00:00
struct pci_devinfo *dinfo;
pcicfgregs *cfg;
struct resource_list *rl;
- As it turns out, MSI-X is broken for at least LSI SAS1068E when passed through by VMware so blacklist their PCI-PCI bridge for MSI/MSI-X here. Note that besides currently there not being a quirk type that disables MSI-X only and there's no evidence that MSI doesn't work with the VMware pass-through, it's really questionable whether MSI generally works in that setup as VMware only mention three know working devices [1, p. 4]. Also not that this quirk entry currently doesn't affect the devices emulated by VMware in any way as these don't claim support MSI/MSI-X to begin with. [2] While at it, make the PCI quirk table const and static. - Remove some duplicated empty lines. - Use DEVMETHOD_END. PR: 163812, http://forums.freebsd.org/showthread.php?t=27899 [2] Reviewed by: jhb MFC after: 3 days
2012-02-14 00:18:35 +00:00
const struct pci_quirk *q;
Add a PCI quirk to ignore PCI map registers from configuration space. For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base address as a memory BAR for SMBus controller depending on a PM register configuration. Before r231161 (and r232086, subsequent MFC to stable/9), it was not fatal but hpet(4) just failed to attach. Since we probe and attach HPET earlier than PCI devices now, it caused unfortunate hard lockup. With this patch, it does not hang any more and HPET works at the same time. Clean up some style nits while I am in the neighborhood. PR: kern/165647 Reviewed by: jhb MFC after: 3 days
2012-03-14 23:25:46 +00:00
uint32_t devid;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
int i;
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
Add a PCI quirk to ignore PCI map registers from configuration space. For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base address as a memory BAR for SMBus controller depending on a PM register configuration. Before r231161 (and r232086, subsequent MFC to stable/9), it was not fatal but hpet(4) just failed to attach. Since we probe and attach HPET earlier than PCI devices now, it caused unfortunate hard lockup. With this patch, it does not hang any more and HPET works at the same time. Clean up some style nits while I am in the neighborhood. PR: kern/165647 Reviewed by: jhb MFC after: 3 days
2012-03-14 23:25:46 +00:00
dinfo = device_get_ivars(dev);
cfg = &dinfo->cfg;
rl = &dinfo->resources;
devid = (cfg->device << 16) | cfg->vendor;
Support for Enhanced Allocation in PCI On some platforms, BAR entries are hardcoded and must not be accessed using standard method. Add functionality to identify this situation and configure the bus based on Enhanced Allocation structure. Obtained from: Semihalf Sponsored by: Cavium Approved by: cognet (mentor) Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D5242
2016-03-02 09:54:58 +00:00
/* Allocate resources using Enhanced Allocation */
pci_add_resources_ea(bus, dev, 0);
Update the special handling code for ATA devices to allow usage of PCI native addressing. That means that if the HW says that using "real" addresses instead of the hardwired legacy compat ones is allowed, we will use them.
2004-06-29 20:25:43 +00:00
/* ATA devices needs special map treatment */
if ((pci_get_class(dev) == PCIC_STORAGE) &&
(pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
Add support for chipsets that has NULL'd BAR's for legacy ports. This allows DMA to be used on a fine little geode system I got here and most like on lots of older systems like that. HW donated by: Paul Ghering
2007-02-17 16:56:39 +00:00
((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
(!pci_read_config(dev, PCIR_BAR(0), 4) &&
!pci_read_config(dev, PCIR_BAR(2), 4))) )
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_ata_maps(bus, dev, rl, force, prefetchmask);
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
else
Add a PCI quirk to ignore PCI map registers from configuration space. For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base address as a memory BAR for SMBus controller depending on a PM register configuration. Before r231161 (and r232086, subsequent MFC to stable/9), it was not fatal but hpet(4) just failed to attach. Since we probe and attach HPET earlier than PCI devices now, it caused unfortunate hard lockup. With this patch, it does not hang any more and HPET works at the same time. Clean up some style nits while I am in the neighborhood. PR: kern/165647 Reviewed by: jhb MFC after: 3 days
2012-03-14 23:25:46 +00:00
for (i = 0; i < cfg->nummaps;) {
Support for Enhanced Allocation in PCI On some platforms, BAR entries are hardcoded and must not be accessed using standard method. Add functionality to identify this situation and configure the bus based on Enhanced Allocation structure. Obtained from: Semihalf Sponsored by: Cavium Approved by: cognet (mentor) Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D5242
2016-03-02 09:54:58 +00:00
/* Skip resources already managed by EA */
if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) ||
(resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) ||
pci_ea_is_enabled(dev, PCIR_BAR(i))) {
i++;
continue;
}
Add a PCI quirk to ignore PCI map registers from configuration space. For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base address as a memory BAR for SMBus controller depending on a PM register configuration. Before r231161 (and r232086, subsequent MFC to stable/9), it was not fatal but hpet(4) just failed to attach. Since we probe and attach HPET earlier than PCI devices now, it caused unfortunate hard lockup. With this patch, it does not hang any more and HPET works at the same time. Clean up some style nits while I am in the neighborhood. PR: kern/165647 Reviewed by: jhb MFC after: 3 days
2012-03-14 23:25:46 +00:00
/*
* Skip quirked resources.
*/
for (q = &pci_quirks[0]; q->devid != 0; q++)
if (q->devid == devid &&
q->type == PCI_QUIRK_UNMAP_REG &&
q->arg1 == PCIR_BAR(i))
break;
if (q->devid != 0) {
i++;
continue;
}
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
prefetchmask & (1 << i));
Add a PCI quirk to ignore PCI map registers from configuration space. For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base address as a memory BAR for SMBus controller depending on a PM register configuration. Before r231161 (and r232086, subsequent MFC to stable/9), it was not fatal but hpet(4) just failed to attach. Since we probe and attach HPET earlier than PCI devices now, it caused unfortunate hard lockup. With this patch, it does not hang any more and HPET works at the same time. Clean up some style nits while I am in the neighborhood. PR: kern/165647 Reviewed by: jhb MFC after: 3 days
2012-03-14 23:25:46 +00:00
}
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
Expose pci_add_resources to the outside world, add a 'force' flag to force allocation of unallocated BARs (cardbus uses this to preallocate everything). Add a prefetchmask to allow for busses that get prefetch hints to set them. Addjust pci_add_map and pci_ata_maps to take a new force flag which pci_add_resources will pass in. Implement 'force' in pci_add_map. Write new value of allocated resource into the bar, if the allocation succeeded (we should have done this before, but with the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
/*
* Add additional, quirked resources.
*/
Add a PCI quirk to ignore PCI map registers from configuration space. For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base address as a memory BAR for SMBus controller depending on a PM register configuration. Before r231161 (and r232086, subsequent MFC to stable/9), it was not fatal but hpet(4) just failed to attach. Since we probe and attach HPET earlier than PCI devices now, it caused unfortunate hard lockup. With this patch, it does not hang any more and HPET works at the same time. Clean up some style nits while I am in the neighborhood. PR: kern/165647 Reviewed by: jhb MFC after: 3 days
2012-03-14 23:25:46 +00:00
for (q = &pci_quirks[0]; q->devid != 0; q++)
if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
pci_add_map(bus, dev, q->arg1, rl, force, 0);
Fix some resource allocation peculiarities of the intpm device.
1999-10-28 08:06:59 +00:00
Use PCI_INTERRUPT_VALI in stead of hard coded 255
2002-06-01 05:48:58 +00:00
if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
Use __HAVE_ACPI and __PCI_REROUTE_INTERRUPT as appropriate rather than the complicated #ifdefs.
2006-01-01 21:04:31 +00:00
#ifdef __PCI_REROUTE_INTERRUPT
Re-route interrupts on ia64 so that we can get the I/O SAPIC interrupt numbers (the BIOS leaves legacy PIC interrupt numbers in the intline registers).
2001-10-05 10:33:42 +00:00
/*
- Adjust the comment about re-routing PCI interrupts to be less ia64-specific. - When trying to re-route interrupts, don't change cfg->intline if the re-route fails by returning an invalid vector. This fixes machines without any way of routing interrupts such as older PC's without a $PIR table. We do not currently write the new intline value back to the hardware, but we should. That will likely be added in a later commit.
2003-06-07 15:00:19 +00:00
* Try to re-route interrupts. Sometimes the BIOS or
* firmware may leave bogus values in these registers.
* If the re-route fails, then just stick with what we
* have.
Re-route interrupts on ia64 so that we can get the I/O SAPIC interrupt numbers (the BIOS leaves legacy PIC interrupt numbers in the intline registers).
2001-10-05 10:33:42 +00:00
*/
- Consolidate duplicated code for assigning interrupts to PCI devices via routing, etc. in a static pci_assign_interrupt() function. - Add a sledgehammer that allows the user to override the interrupt assignment of any PCI device via a tunable (e.g. "hw.pci0.7.INTB=5" would force any functions on the pci device in slot 7 of bus 0 that use B# to use IRQ 5). This should be used with great caution! Generally, if the interrupt routing in use provides specific tunables (such as hard-wiring the IRQ for a given $PIR or ACPI PCI link device), then those should be used instead. One instance where this tunable might be useful is if a box has an MPTable with duplicate entries for the same PCI device with different IRQs. MFC after: 1 week
2005-09-29 15:04:41 +00:00
pci_assign_interrupt(bus, dev, 1);
#else
pci_assign_interrupt(bus, dev, 0);
Re-route interrupts on ia64 so that we can get the I/O SAPIC interrupt numbers (the BIOS leaves legacy PIC interrupt numbers in the intline registers).
2001-10-05 10:33:42 +00:00
#endif
}
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
Add missing XHCI early takeover code. The XHCI takeover code is supposed to disable the BIOS from using the XHCI controller after bootup. Approved by: re (kib) Reported by: Mike Tancsa MFC after: 1 week
2011-07-22 15:37:23 +00:00
if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
xhci_early_takeover(dev);
else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
2009-10-15 20:07:08 +00:00
ehci_early_takeover(dev);
else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
ohci_early_takeover(dev);
else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
uhci_early_takeover(dev);
}
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
/*
* Reserve resources for secondary bus ranges behind bridge
* devices.
*/
pci_reserve_secbus(bus, dev, cfg, rl);
#endif
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Add support for PCIe ARI PCIe Alternate RID Interpretation (ARI) is an optional feature that allows devices to have up to 256 different functions. It is implemented by always setting the PCI slot number to 0 and re-purposing the 5 bits used to encode the slot number to instead contain the function number. Combined with the original 3 bits allocated for the function number, this allows for 256 functions. This is enabled by default, but it's expected to be a no-op on currently supported hardware. It's a prerequisite for supporting PCI SR-IOV, and I want the ARI support to go in early to help shake out any bugs in it. ARI can be disabled by setting the tunable hw.pci.enable_ari=0. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 16:02:02 +00:00
static struct pci_devinfo *
pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
int slot, int func)
Add support for PCIe ARI PCIe Alternate RID Interpretation (ARI) is an optional feature that allows devices to have up to 256 different functions. It is implemented by always setting the PCI slot number to 0 and re-purposing the 5 bits used to encode the slot number to instead contain the function number. Combined with the original 3 bits allocated for the function number, this allows for 256 functions. This is enabled by default, but it's expected to be a no-op on currently supported hardware. It's a prerequisite for supporting PCI SR-IOV, and I want the ARI support to go in early to help shake out any bugs in it. ARI can be disabled by setting the tunable hw.pci.enable_ari=0. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 16:02:02 +00:00
{
struct pci_devinfo *dinfo;
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
dinfo = pci_read_device(pcib, dev, domain, busno, slot, func);
Add support for PCIe ARI PCIe Alternate RID Interpretation (ARI) is an optional feature that allows devices to have up to 256 different functions. It is implemented by always setting the PCI slot number to 0 and re-purposing the 5 bits used to encode the slot number to instead contain the function number. Combined with the original 3 bits allocated for the function number, this allows for 256 functions. This is enabled by default, but it's expected to be a no-op on currently supported hardware. It's a prerequisite for supporting PCI SR-IOV, and I want the ARI support to go in early to help shake out any bugs in it. ARI can be disabled by setting the tunable hw.pci.enable_ari=0. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 16:02:02 +00:00
if (dinfo != NULL)
pci_add_child(dev, dinfo);
return (dinfo);
}
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
void
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
pci_add_children(device_t dev, int domain, int busno)
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
{
Replace #define<space> with #define<tab> so the code is consistent with style(9) and avoids mixing the two formats.
2006-12-14 16:53:48 +00:00
#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
device_t pcib = device_get_parent(dev);
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
struct pci_devinfo *dinfo;
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
int maxslots;
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
int s, f, pcifunchigh;
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint8_t hdrtype;
Add support for PCIe ARI PCIe Alternate RID Interpretation (ARI) is an optional feature that allows devices to have up to 256 different functions. It is implemented by always setting the PCI slot number to 0 and re-purposing the 5 bits used to encode the slot number to instead contain the function number. Combined with the original 3 bits allocated for the function number, this allows for 256 functions. This is enabled by default, but it's expected to be a no-op on currently supported hardware. It's a prerequisite for supporting PCI SR-IOV, and I want the ARI support to go in early to help shake out any bugs in it. ARI can be disabled by setting the tunable hw.pci.enable_ari=0. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 16:02:02 +00:00
int first_func;
/*
* Try to detect a device at slot 0, function 0. If it exists, try to
* enable ARI. We must enable ARI before detecting the rest of the
* functions on this bus as ARI changes the set of slots and functions
* that are legal on this bus.
*/
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0);
Add support for PCIe ARI PCIe Alternate RID Interpretation (ARI) is an optional feature that allows devices to have up to 256 different functions. It is implemented by always setting the PCI slot number to 0 and re-purposing the 5 bits used to encode the slot number to instead contain the function number. Combined with the original 3 bits allocated for the function number, this allows for 256 functions. This is enabled by default, but it's expected to be a no-op on currently supported hardware. It's a prerequisite for supporting PCI SR-IOV, and I want the ARI support to go in early to help shake out any bugs in it. ARI can be disabled by setting the tunable hw.pci.enable_ari=0. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 16:02:02 +00:00
if (dinfo != NULL && pci_enable_ari)
PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
/*
* Start looking for new devices on slot 0 at function 1 because we
* just identified the device at slot 0, function 0.
*/
first_func = 1;
Add support for multiple PCI "hoses" used on various alpha platforms. The specific intent of this commit is to pave the way for importing Compaq XP1000 support. These changes should not affect the i386 port. Reviewed by: Doug Rabson <dfr@nlsystems.com> (actually, he walked me through most of it & deserves more than reviewd-by credit )
1999-05-20 15:33:33 +00:00
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
maxslots = PCIB_MAXSLOTS(pcib);
Correct a PCI enumeration bug introduced in r264011 Ensure that first_func is set to 0 on every iteration of the PCI slot enumeration loop after the first. There is a continue statement that would cause first_func to stay at 1 any PCI device where slot 0 has no functions until we find a slot that does have a function. This would cause us to not enumerate the first PCI function on the device. Credit to markj@ for spotting the bug. X-MFC-With: r264011
2014-04-03 22:32:12 +00:00
for (s = 0; s <= maxslots; s++, first_func = 0) {
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
pcifunchigh = 0;
use a REG macro that was already defined. Reorder how the pci probing in handled. before adding devices, check to see if the slot is a multi-function device to see if we should probe all the functions. Original idea by: imp
2003-06-22 02:26:17 +00:00
f = 0;
Add a 1 microsecond delay in pci_add_children(), right before the read of the PCIR_HDRTYPE register. It's the value returned from this read access that determines whether or not we decide a device is present at the current slot index. For some reason that I can't adequately explain, this read fails on my machine when probing the USB controller on my machine (which happens a multifunction device at slot index 3 hung off the PCI-PCI bridge on the AMD8111 (bus index 1)). The read will return 0xFF even though it should return 0x80 to indicate the presence of a multifunction device. As near as I can tell, there's some timing issue involved with reading the 'dead' slot indexes 0 through 2 that causes the read of the actual device at slot 3 to fail. I tried a couple of different tricks to correct the problem (the patch to amd64/pci/pci_cfgreg.c fixes it for the amd64 arch), but adding this delay is the only thing that always allows the USB controllers to be correctly probed 100% of the time. Whatever the problem is, it's likely confined to the AMD8111 chipset. However, a simple 1us delay is fairly harmless and should have no side effects for other hardware. I consider this to be voodoo, but it's fairly benign voodoo and it makes my USB keyboard and mouse work again. Note that this is the second time that I've had to resort to a 1us delay to fix a PCI-related problem with this AMD8111/Opteron system (the first being a fix I made a while back to the NDISulator). It's possible the delay really belongs in the cfgreg code itself, or that pci_cfgreg needs some custom hackery for an errata in the 8111. (I checked but couldn't find any documented errata on AMD's site that could account for these problems.)
2005-10-25 06:53:45 +00:00
DELAY(1);
- Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long. - Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds the header type. - Replace several magic numbers with appropriate constants for the header type register and a couple of PCI_FUNCMAX. - Merge to amd64 the fix to the i386 bridge code to skip devices with unknown header types. Requested by: imp (1, 2)
2003-08-28 21:22:25 +00:00
hdrtype = REG(PCIR_HDRTYPE, 1);
if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
use a REG macro that was already defined. Reorder how the pci probing in handled. before adding devices, check to see if the slot is a multi-function device to see if we should probe all the functions. Original idea by: imp
2003-06-22 02:26:17 +00:00
continue;
if (hdrtype & PCIM_MFDEV)
Add support for PCIe ARI PCIe Alternate RID Interpretation (ARI) is an optional feature that allows devices to have up to 256 different functions. It is implemented by always setting the PCI slot number to 0 and re-purposing the 5 bits used to encode the slot number to instead contain the function number. Combined with the original 3 bits allocated for the function number, this allows for 256 functions. This is enabled by default, but it's expected to be a no-op on currently supported hardware. It's a prerequisite for supporting PCI SR-IOV, and I want the ARI support to go in early to help shake out any bugs in it. ARI can be disabled by setting the tunable hw.pci.enable_ari=0. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 16:02:02 +00:00
pcifunchigh = PCIB_MAXFUNCS(pcib);
for (f = first_func; f <= pcifunchigh; f++)
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
pci_identify_function(pcib, dev, domain, busno, s, f);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
use a REG macro that was already defined. Reorder how the pci probing in handled. before adding devices, check to see if the slot is a multi-function device to see if we should probe all the functions. Original idea by: imp
2003-06-22 02:26:17 +00:00
#undef REG
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Implement a PCI bus rescan method. Rescanning a PCI bus uses the following steps: - Fetch the current set of child devices and save it in the 'devlist' array. - Allocate a parallel array 'unchanged' initalized with NULL pointers. - Scan the bus checking each slot (and each function on slots with a multifunction device). - If a valid function is found, look for a matching device in the 'devlist' array. If a device is found, save the pointer in the 'unchanged' array. If a device is not found, add a new device. - After the scan has finished, walk the 'devlist' array deleting any devices that do not have a matching pointer in the 'unchanged' array. - Finally, fetch an updated set of child devices and explicitly attach any devices that are not present in the 'unchanged' array. This builds on the previous changes to move subclass data management into pci_alloc_devinfo(), pci_child_added(), and bus_child_deleted(). Subclasses of the PCI bus use custom rescan logic explicitly override the rescan method to disable rescans. Differential Revision: https://reviews.freebsd.org/D6018
2016-04-27 16:31:12 +00:00
int
pci_rescan_method(device_t dev)
{
#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
device_t pcib = device_get_parent(dev);
device_t child, *devlist, *unchanged;
int devcount, error, i, j, maxslots, oldcount;
int busno, domain, s, f, pcifunchigh;
uint8_t hdrtype;
/* No need to check for ARI on a rescan. */
error = device_get_children(dev, &devlist, &devcount);
if (error)
return (error);
if (devcount != 0) {
unchanged = malloc(devcount * sizeof(device_t), M_TEMP,
M_NOWAIT | M_ZERO);
if (unchanged == NULL) {
free(devlist, M_TEMP);
return (ENOMEM);
}
} else
unchanged = NULL;
domain = pcib_get_domain(dev);
busno = pcib_get_bus(dev);
maxslots = PCIB_MAXSLOTS(pcib);
for (s = 0; s <= maxslots; s++) {
/* If function 0 is not present, skip to the next slot. */
f = 0;
if (REG(PCIR_VENDOR, 2) == 0xffff)
continue;
pcifunchigh = 0;
hdrtype = REG(PCIR_HDRTYPE, 1);
if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
continue;
if (hdrtype & PCIM_MFDEV)
pcifunchigh = PCIB_MAXFUNCS(pcib);
for (f = 0; f <= pcifunchigh; f++) {
Fix invalid vendor ID constant (typo). During a bus rescan the check for an invalid vendor ID of a subfunction used the wrong constant. Submitted by: Dexuan Cui <decui@microsoft.com> MFC after: 3 days
2016-09-21 16:51:56 +00:00
if (REG(PCIR_VENDOR, 2) == 0xffff)
Implement a PCI bus rescan method. Rescanning a PCI bus uses the following steps: - Fetch the current set of child devices and save it in the 'devlist' array. - Allocate a parallel array 'unchanged' initalized with NULL pointers. - Scan the bus checking each slot (and each function on slots with a multifunction device). - If a valid function is found, look for a matching device in the 'devlist' array. If a device is found, save the pointer in the 'unchanged' array. If a device is not found, add a new device. - After the scan has finished, walk the 'devlist' array deleting any devices that do not have a matching pointer in the 'unchanged' array. - Finally, fetch an updated set of child devices and explicitly attach any devices that are not present in the 'unchanged' array. This builds on the previous changes to move subclass data management into pci_alloc_devinfo(), pci_child_added(), and bus_child_deleted(). Subclasses of the PCI bus use custom rescan logic explicitly override the rescan method to disable rescans. Differential Revision: https://reviews.freebsd.org/D6018
2016-04-27 16:31:12 +00:00
continue;
/*
* Found a valid function. Check if a
* device_t for this device already exists.
*/
for (i = 0; i < devcount; i++) {
child = devlist[i];
if (child == NULL)
continue;
if (pci_get_slot(child) == s &&
pci_get_function(child) == f) {
unchanged[i] = child;
goto next_func;
}
}
pci_identify_function(pcib, dev, domain, busno, s, f);
next_func:;
}
}
/* Remove devices that are no longer present. */
for (i = 0; i < devcount; i++) {
if (unchanged[i] != NULL)
continue;
device_delete_child(dev, devlist[i]);
}
free(devlist, M_TEMP);
oldcount = devcount;
/* Try to attach the devices just added. */
error = device_get_children(dev, &devlist, &devcount);
if (error) {
free(unchanged, M_TEMP);
return (error);
}
for (i = 0; i < devcount; i++) {
for (j = 0; j < oldcount; j++) {
if (devlist[i] == unchanged[j])
goto next_device;
}
device_probe_and_attach(devlist[i]);
next_device:;
}
free(unchanged, M_TEMP);
free(devlist, M_TEMP);
return (0);
#undef REG
}
Implement interface to create SR-IOV Virtual Functions Implement the interace to create SR-IOV Virtual Functions (VFs). When a driver registers that they support SR-IOV by calling pci_setup_iov(), the SR-IOV code creates a new node in /dev/iov for that device. An ioctl can be invoked on that device to create VFs and have the driver initialize them. At this point, allocating memory I/O windows (BARs) is not supported. Differential Revision: https://reviews.freebsd.org/D76 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:09 +00:00
#ifdef PCI_IOV
device_t
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid,
uint16_t did)
Implement interface to create SR-IOV Virtual Functions Implement the interace to create SR-IOV Virtual Functions (VFs). When a driver registers that they support SR-IOV by calling pci_setup_iov(), the SR-IOV code creates a new node in /dev/iov for that device. An ioctl can be invoked on that device to create VFs and have the driver initialize them. At this point, allocating memory I/O windows (BARs) is not supported. Differential Revision: https://reviews.freebsd.org/D76 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:09 +00:00
{
Do pass removing some write-only variables from the kernel. This reduces noise when kernel is compiled by newer GCC versions, such as one used by external toolchain ports. Reviewed by: kib, andrew(sys/arm and sys/arm64), emaste(partial), erj(partial) Reviewed by: jhb (sys/dev/pci/* sys/kern/vfs_aio.c and sys/kern/kern_synch.c) Differential Revision: https://reviews.freebsd.org/D10385
2017-12-25 04:48:39 +00:00
struct pci_devinfo *vf_dinfo;
Implement interface to create SR-IOV Virtual Functions Implement the interace to create SR-IOV Virtual Functions (VFs). When a driver registers that they support SR-IOV by calling pci_setup_iov(), the SR-IOV code creates a new node in /dev/iov for that device. An ioctl can be invoked on that device to create VFs and have the driver initialize them. At this point, allocating memory I/O windows (BARs) is not supported. Differential Revision: https://reviews.freebsd.org/D76 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:09 +00:00
device_t pcib;
int busno, slot, func;
pcib = device_get_parent(bus);
PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func);
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno,
slot, func, vid, did);
Implement interface to create SR-IOV Virtual Functions Implement the interace to create SR-IOV Virtual Functions (VFs). When a driver registers that they support SR-IOV by calling pci_setup_iov(), the SR-IOV code creates a new node in /dev/iov for that device. An ioctl can be invoked on that device to create VFs and have the driver initialize them. At this point, allocating memory I/O windows (BARs) is not supported. Differential Revision: https://reviews.freebsd.org/D76 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:09 +00:00
vf_dinfo->cfg.flags |= PCICFG_VF;
pci_add_child(bus, vf_dinfo);
return (vf_dinfo->cfg.dev);
}
device_t
pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid,
uint16_t vid, uint16_t did)
{
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
return (pci_add_iov_child(bus, pf, rid, vid, did));
Implement interface to create SR-IOV Virtual Functions Implement the interace to create SR-IOV Virtual Functions (VFs). When a driver registers that they support SR-IOV by calling pci_setup_iov(), the SR-IOV code creates a new node in /dev/iov for that device. An ioctl can be invoked on that device to create VFs and have the driver initialize them. At this point, allocating memory I/O windows (BARs) is not supported. Differential Revision: https://reviews.freebsd.org/D76 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:09 +00:00
}
#endif
Rudimentary AER reading code for ddb(4). This is very primitive code to inspect the PCI error state and AER error state, dump the log and clear errors, from ddb. pci_print_faulted_dev() is made external to allow calling it from other places. It was called from NMI handler but this chunk is not included. Also there is a tunable-controlled code to clear AER on device attach, disabled by default. All this code was useful to me when I debugged ACPI_DMAR failures (not faults) long time ago. Reviewed by: cem, imp (previous version) Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D7813
2018-08-18 20:35:19 +00:00
static void
pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo)
{
int aer;
uint32_t r;
uint16_t r2;
if (dinfo->cfg.pcie.pcie_location != 0 &&
dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) {
r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
PCIER_ROOT_CTL, 2);
r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR |
PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL);
pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
PCIER_ROOT_CTL, r2, 2);
}
if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
if (r != 0 && bootverbose) {
pci_printf(&dinfo->cfg,
"clearing AER UC 0x%08x -> 0x%08x\n",
r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS,
4));
}
r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4);
r &= ~(PCIM_AER_UC_TRAINING_ERROR |
PCIM_AER_UC_DL_PROTOCOL_ERROR |
PCIM_AER_UC_SURPRISE_LINK_DOWN |
PCIM_AER_UC_POISONED_TLP |
PCIM_AER_UC_FC_PROTOCOL_ERROR |
PCIM_AER_UC_COMPLETION_TIMEOUT |
PCIM_AER_UC_COMPLETER_ABORT |
PCIM_AER_UC_UNEXPECTED_COMPLETION |
PCIM_AER_UC_RECEIVER_OVERFLOW |
PCIM_AER_UC_MALFORMED_TLP |
PCIM_AER_UC_ECRC_ERROR |
PCIM_AER_UC_UNSUPPORTED_REQUEST |
PCIM_AER_UC_ACS_VIOLATION |
PCIM_AER_UC_INTERNAL_ERROR |
PCIM_AER_UC_MC_BLOCKED_TLP |
PCIM_AER_UC_ATOMIC_EGRESS_BLK |
PCIM_AER_UC_TLP_PREFIX_BLOCKED);
pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4);
r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
if (r != 0 && bootverbose) {
pci_printf(&dinfo->cfg,
"clearing AER COR 0x%08x -> 0x%08x\n",
r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS,
4));
}
r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4);
r &= ~(PCIM_AER_COR_RECEIVER_ERROR |
PCIM_AER_COR_BAD_TLP |
PCIM_AER_COR_BAD_DLLP |
PCIM_AER_COR_REPLAY_ROLLOVER |
PCIM_AER_COR_REPLAY_TIMEOUT |
PCIM_AER_COR_ADVISORY_NF_ERROR |
PCIM_AER_COR_INTERNAL_ERROR |
PCIM_AER_COR_HEADER_LOG_OVFLOW);
pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4);
r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
PCIER_DEVICE_CTL, 2);
r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE |
PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE;
pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
PCIER_DEVICE_CTL, r, 2);
}
}
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
void
pci_add_child(device_t bus, struct pci_devinfo *dinfo)
{
Rudimentary AER reading code for ddb(4). This is very primitive code to inspect the PCI error state and AER error state, dump the log and clear errors, from ddb. pci_print_faulted_dev() is made external to allow calling it from other places. It was called from NMI handler but this chunk is not included. Also there is a tunable-controlled code to clear AER on device attach, disabled by default. All this code was useful to me when I debugged ACPI_DMAR failures (not faults) long time ago. Reviewed by: cem, imp (previous version) Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D7813
2018-08-18 20:35:19 +00:00
device_t dev;
dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1);
device_set_ivars(dev, dinfo);
Use STAILQ in preference to SLIST for the resources. Insert new resources last in the list rather than first. This makes the resouces print in the 4.x order rather than the 5.x order (eg fdc0 at 0x3f0-0x3f5,0x3f7 is 4.x, but 0x3f7,0x3f0-0x3f5 is 5.x). This also means that the pci code will once again print the resources in BAR ascending order.
2005-03-18 05:19:50 +00:00
resource_list_init(&dinfo->resources);
Rudimentary AER reading code for ddb(4). This is very primitive code to inspect the PCI error state and AER error state, dump the log and clear errors, from ddb. pci_print_faulted_dev() is made external to allow calling it from other places. It was called from NMI handler but this chunk is not included. Also there is a tunable-controlled code to clear AER on device attach, disabled by default. All this code was useful to me when I debugged ACPI_DMAR failures (not faults) long time ago. Reviewed by: cem, imp (previous version) Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D7813
2018-08-18 20:35:19 +00:00
pci_cfg_save(dev, dinfo, 0);
pci_cfg_restore(dev, dinfo);
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
pci_print_verbose(dinfo);
Rudimentary AER reading code for ddb(4). This is very primitive code to inspect the PCI error state and AER error state, dump the log and clear errors, from ddb. pci_print_faulted_dev() is made external to allow calling it from other places. It was called from NMI handler but this chunk is not included. Also there is a tunable-controlled code to clear AER on device attach, disabled by default. All this code was useful to me when I debugged ACPI_DMAR failures (not faults) long time ago. Reviewed by: cem, imp (previous version) Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D7813
2018-08-18 20:35:19 +00:00
pci_add_resources(bus, dev, 0, 0);
pci: add a new pci_child_added newbus method. This is needed so when running under Xen the calls to pci_child_added can be intercepted and a custom Xen method can be used to register those devices with Xen. This should not include any functional change, since the Xen implementation will be added in a following patch and the native implementation is a noop. Sponsored by: Citrix Systems R&D Reviewed by: jhb dev/pci/pci.c: dev/pci/pci_if.m: dev/pci/pci_private.h: dev/pci/pcivar.h: - Add the pci_child_added newbus method.
2014-08-22 15:05:51 +00:00
pci_child_added(dinfo->cfg.dev);
Rudimentary AER reading code for ddb(4). This is very primitive code to inspect the PCI error state and AER error state, dump the log and clear errors, from ddb. pci_print_faulted_dev() is made external to allow calling it from other places. It was called from NMI handler but this chunk is not included. Also there is a tunable-controlled code to clear AER on device attach, disabled by default. All this code was useful to me when I debugged ACPI_DMAR failures (not faults) long time ago. Reviewed by: cem, imp (previous version) Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D7813
2018-08-18 20:35:19 +00:00
if (pci_clear_aer_on_attach)
pci_add_child_clear_aer(dev, dinfo);
Update the I/O MMU in bhyve when PCI devices are added and removed. When the I/O MMU is active in bhyve, all PCI devices need valid entries in the DMAR context tables. The I/O MMU code does a single enumeration of the available PCI devices during initialization to add all existing devices to a domain representing the host. The ppt(4) driver then moves pass through devices in and out of domains for virtual machines as needed. However, when new PCI devices were added at runtime either via SR-IOV or HotPlug, the I/O MMU tables were not updated. This change adds a new set of EVENTHANDLERS that are invoked when PCI devices are added and deleted. The I/O MMU driver in bhyve installs handlers for these events which it uses to add and remove devices to the "host" domain. Reviewed by: imp Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D7667
2016-09-06 20:17:54 +00:00
EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev);
pci: add a new pci_child_added newbus method. This is needed so when running under Xen the calls to pci_child_added can be intercepted and a custom Xen method can be used to register those devices with Xen. This should not include any functional change, since the Xen implementation will be added in a following patch and the native implementation is a noop. Sponsored by: Citrix Systems R&D Reviewed by: jhb dev/pci/pci.c: dev/pci/pci_if.m: dev/pci/pci_private.h: dev/pci/pcivar.h: - Add the pci_child_added newbus method.
2014-08-22 15:05:51 +00:00
}
void
pci_child_added_method(device_t dev, device_t child)
{
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
}
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
static int
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
pci_probe(device_t dev)
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
{
Convert DEVFS hooks in (most) drivers to make_dev(). Diskslice/label code not yet handled. Vinum, i4b, alpha, pc98 not dealt with (left to respective Maintainers) Add the correct hook for devfs to kern_conf.c The net result of this excercise is that a lot less files depends on DEVFS, and devtoname() gets more sensible output in many cases. A few drivers had minor additional cleanups performed relating to cdevsw registration. A few drivers don't register a cdevsw{} anymore, but only use make_dev().
1999-08-23 20:59:21 +00:00
device_set_desc(dev, "PCI bus");
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
/* Allow other subclasses to override this driver. */
Change the probe priority for PCI and I2C generic bus modules from numerical constants to BUS_PROBE_GENERIC. Suggested by: jhb
2009-01-20 00:05:43 +00:00
return (BUS_PROBE_GENERIC);
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
}
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
int
pci_attach_common(device_t dev)
{
struct pci_softc *sc;
Simplify the PCI bus dma tag code a bit. First, don't create a tag at all for platforms that only have 32-bit bus addresses. Second, remove the 'tag_valid' flag from the softc. Instead, if we don't create a tag in pci_attach_common(), just cache the value of our parent's tag so that we always have a valid tag to return.
2012-03-07 18:50:33 +00:00
int busno, domain;
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
#ifdef PCI_RES_BUS
int rid;
#endif
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
sc = device_get_softc(dev);
domain = pcib_get_domain(dev);
busno = pcib_get_bus(dev);
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
#ifdef PCI_RES_BUS
rid = 0;
sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno,
1, 0);
if (sc->sc_bus == NULL) {
device_printf(dev, "failed to allocate bus number\n");
return (ENXIO);
}
#endif
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
if (bootverbose)
device_printf(dev, "domain=%d, physical bus=%d\n",
domain, busno);
remove the 4GB boundary requirement on PCI DMA segments Reviewed by: kib Discussed with: jhb Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D19867
2019-04-19 13:43:33 +00:00
sc->sc_dma_tag = bus_get_dma_tag(dev);
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
return (0);
}
Export pci_attach() and pci_detach(). Reviewed by: imp MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D21948
2019-10-15 18:58:01 +00:00
int
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
pci_attach(device_t dev)
{
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
int busno, domain, error;
error = pci_attach_common(dev);
if (error)
return (error);
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
/*
sys/dev: minor spelling fixes. Most affect comments, very few have user-visible effects.
2016-05-03 03:41:25 +00:00
* Since there can be multiple independently numbered PCI
"Buses" is the preferred plural of "bus" Replace archaic "busses" with modern form "buses." Intentionally excluded: * Old/random drivers I didn't recognize * Old hardware in general * Use of "busses" in code as identifiers No functional change. http://grammarist.com/spelling/buses-busses/ PR: 216099 Reported by: bltsrc at mail.ru Sponsored by: Dell EMC Isilon
2017-01-15 17:54:01 +00:00
* buses on systems with multiple PCI domains, we can't use
Fixup some comments to allow for the fact that PCI domains are not specific to Alpha hoses.
2006-05-11 22:13:21 +00:00
* the unit number to decide which bus we are probing. We ask
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
* the parent pcib what our domain and bus numbers are.
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
*/
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
domain = pcib_get_domain(dev);
Validate the PCI bus number that we fetch from our parent, since there's no guarantee that everything attached to *it* is a PCI bus.
2000-10-09 00:43:45 +00:00
busno = pcib_get_bus(dev);
Add a new PCI bus interface method to alloc the ivars (dinfo) for a device. The ACPI and OFW PCI bus drivers as well as CardBus override this to allocate the larger ivars to hold additional info beyond the stock PCI ivars. This removes the need to pass the size to functions like pci_add_iov_child() and pci_read_device() simplifying IOV and bus rescanning implementations. As a result of this and earlier changes, the ACPI PCI bus driver no longer needs its own device_attach and pci_create_iov_child methods but can use the methods in the stock PCI bus driver instead. Differential Revision: https://reviews.freebsd.org/D5891
2016-04-15 03:42:12 +00:00
pci_add_children(dev, domain, busno);
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
return (bus_generic_attach(dev));
}
Export pci_attach() and pci_detach(). Reviewed by: imp MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D21948
2019-10-15 18:58:01 +00:00
int
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
pci_detach(device_t dev)
{
Fix PCI bus detach to delete child devices. Differential Revision: https://reviews.freebsd.org/D6020
2016-04-27 16:34:29 +00:00
#ifdef PCI_RES_BUS
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
struct pci_softc *sc;
Fix PCI bus detach to delete child devices. Differential Revision: https://reviews.freebsd.org/D6020
2016-04-27 16:34:29 +00:00
#endif
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
int error;
error = bus_generic_detach(dev);
if (error)
return (error);
Fix PCI bus detach to delete child devices. Differential Revision: https://reviews.freebsd.org/D6020
2016-04-27 16:34:29 +00:00
#ifdef PCI_RES_BUS
Fix build for systems without PCI_RES_BUS. Submitted by: vangyzen
2016-04-27 19:54:56 +00:00
sc = device_get_softc(dev);
Fix PCI bus detach to delete child devices. Differential Revision: https://reviews.freebsd.org/D6020
2016-04-27 16:34:29 +00:00
error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus);
if (error)
return (error);
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
#endif
Fix PCI bus detach to delete child devices. Differential Revision: https://reviews.freebsd.org/D6020
2016-04-27 16:34:29 +00:00
return (device_delete_children(dev));
}
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
Add device location wiring to the pci bus. This allows one to specify, for example, that if there's an igb card in bus 12, slot 0, function 0, it should be assigned igb5. If there isn't, or there's one in a different slot, normal numbering rules apply (hinted units are skipped). Adding 'hint.igb.5.at="pci12:0:0"' or 'hint.igb.5.at="pci0:12:0:0"' to /boot/device.hints will accomplish this. The double quotes are important. The kernel only accepts the strings (in shell notation): pci$d:$b:$s:$f and pci$b:$s:$f where $d is the pci domain, $b is the pci bus number, $s is the slot number and $f is the function number. A string compare is done with the current device to avoid another string parser in the kernel. All numbers are unsigned decimal without leading zeros. Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D13546
2017-12-20 19:14:05 +00:00
static void
pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp)
{
int line, unit;
const char *at;
char me1[24], me2[32];
uint8_t b, s, f;
uint32_t d;
d = pci_get_domain(child);
b = pci_get_bus(child);
s = pci_get_slot(child);
f = pci_get_function(child);
snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f);
snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f);
line = 0;
while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) {
resource_string_value(name, unit, "at", &at);
if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0)
continue; /* No match, try next candidate */
*unitp = unit;
return;
}
}
Move setting power state for children into a separate function as they were essentially the same. This also restores hw.pci.do_power_resume tunable, which was broken since r211430. Reviewed by: jhb
2010-10-15 21:39:51 +00:00
static void
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
pci_set_power_child(device_t dev, device_t child, int state)
Move setting power state for children into a separate function as they were essentially the same. This also restores hw.pci.do_power_resume tunable, which was broken since r211430. Reviewed by: jhb
2010-10-15 21:39:51 +00:00
{
Revert r274635 as it's completely wrong. The parent of a pci dev device is a pciX device which do not implement the PCIB_POWER_FOR_SLEEP method from pcib_if.m.
2014-11-19 11:05:45 +00:00
device_t pcib;
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
int dstate;
Move setting power state for children into a separate function as they were essentially the same. This also restores hw.pci.do_power_resume tunable, which was broken since r211430. Reviewed by: jhb
2010-10-15 21:39:51 +00:00
/*
* Set the device to the given state. If the firmware suggests
* a different power state, use it instead. If power management
* is not present, the firmware is responsible for managing
* device power. Skip children who aren't attached since they
Remove PCI header type 0 restriction from power state changes. PCI config. registers for bridges are saved and restored since r200341. OK'ed by: imp, jhb
2010-10-19 17:15:22 +00:00
* are handled separately.
Move setting power state for children into a separate function as they were essentially the same. This also restores hw.pci.do_power_resume tunable, which was broken since r211430. Reviewed by: jhb
2010-10-15 21:39:51 +00:00
*/
Revert r274635 as it's completely wrong. The parent of a pci dev device is a pciX device which do not implement the PCIB_POWER_FOR_SLEEP method from pcib_if.m.
2014-11-19 11:05:45 +00:00
pcib = device_get_parent(dev);
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
dstate = state;
if (device_is_attached(child) &&
Revert r274635 as it's completely wrong. The parent of a pci dev device is a pciX device which do not implement the PCIB_POWER_FOR_SLEEP method from pcib_if.m.
2014-11-19 11:05:45 +00:00
PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0)
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
pci_set_powerstate(child, dstate);
Move setting power state for children into a separate function as they were essentially the same. This also restores hw.pci.do_power_resume tunable, which was broken since r211430. Reviewed by: jhb
2010-10-15 21:39:51 +00:00
}
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
int
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
pci_suspend_child(device_t dev, device_t child)
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
{
struct pci_devinfo *dinfo;
add support for marking interrupt handlers as suspended The goal of this change is to fix a problem with PCI shared interrupts during suspend and resume. I have observed a couple of variations of the following scenario. Devices A and B are on the same PCI bus and share the same interrupt. Device A's driver is suspended first and the device is powered down. Device B generates an interrupt. Interrupt handlers of both drivers are called. Device A's interrupt handler accesses registers of the powered down device and gets back bogus values (I assume all 0xff). That data is interpreted as interrupt status bits, etc. So, the interrupt handler gets confused and may produce some noise or enter an infinite loop, etc. This change affects only PCI devices. The pci(4) bus driver marks a child's interrupt handler as suspended after the child's suspend method is called and before the device is powered down. This is done only for traditional PCI interrupts, because only they can be shared. At the moment the change is only for x86. Notable changes in core subsystems / interfaces: - BUS_SUSPEND_INTR and BUS_RESUME_INTR methods are added to bus interface along with convenience functions bus_suspend_intr and bus_resume_intr; - rman_set_irq_cookie and rman_get_irq_cookie functions are added to provide a way to associate an interrupt resource with an interrupt cookie; - intr_event_suspend_handler and intr_event_resume_handler functions are added to the MI interrupt handler interface. I added two new interrupt handler flags, IH_SUSP and IH_CHANGED, to implement the new intr_event functions. IH_SUSP marks a suspended interrupt handler. IH_CHANGED is used to implement a barrier that ensures that a change to the interrupt handler's state is visible to future interrupts. While there, I fixed some whitespace issues in comments and changed a couple of logically boolean variables to be bool. MFC after: 1 month (maybe) Differential Revision: https://reviews.freebsd.org/D15755
2018-12-17 17:11:00 +00:00
struct resource_list_entry *rle;
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
int error;
dinfo = device_get_ivars(child);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
/*
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
* Save the PCI configuration space for the child and set the
Turn ACPI and PCI devices off or to a lower power state in suspend and back on again in resume. Override the default of D3 with the value the BIOS specifies in _SxD, if present. Skip serial devices (PNP05xx) since they seem to hang when set to D3 and may require special driver support. Also, skip non-type 0 PCI devices (i.e., bridges) since our we don't yet save/restore their config space and that seems to be necessary. If this gives you trouble with suspend/resume, you can disable the new ACPI and PCI power behavior separately with these tunables & sysctls: debug.acpi.do_powerstate hw.pci.do_powerstate Approved by: imp (pci) Tested by: acpi@ (numerous)
2004-12-02 08:07:12 +00:00
* device in the appropriate power state for this sleep state.
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
*/
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
pci_cfg_save(child, dinfo, 0);
Turn ACPI and PCI devices off or to a lower power state in suspend and back on again in resume. Override the default of D3 with the value the BIOS specifies in _SxD, if present. Skip serial devices (PNP05xx) since they seem to hang when set to D3 and may require special driver support. Also, skip non-type 0 PCI devices (i.e., bridges) since our we don't yet save/restore their config space and that seems to be necessary. If this gives you trouble with suspend/resume, you can disable the new ACPI and PCI power behavior separately with these tunables & sysctls: debug.acpi.do_powerstate hw.pci.do_powerstate Approved by: imp (pci) Tested by: acpi@ (numerous)
2004-12-02 08:07:12 +00:00
/* Suspend devices before potentially powering them down. */
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
error = bus_generic_suspend_child(dev, child);
if (error)
Turn ACPI and PCI devices off or to a lower power state in suspend and back on again in resume. Override the default of D3 with the value the BIOS specifies in _SxD, if present. Skip serial devices (PNP05xx) since they seem to hang when set to D3 and may require special driver support. Also, skip non-type 0 PCI devices (i.e., bridges) since our we don't yet save/restore their config space and that seems to be necessary. If this gives you trouble with suspend/resume, you can disable the new ACPI and PCI power behavior separately with these tunables & sysctls: debug.acpi.do_powerstate hw.pci.do_powerstate Approved by: imp (pci) Tested by: acpi@ (numerous)
2004-12-02 08:07:12 +00:00
return (error);
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
add support for marking interrupt handlers as suspended The goal of this change is to fix a problem with PCI shared interrupts during suspend and resume. I have observed a couple of variations of the following scenario. Devices A and B are on the same PCI bus and share the same interrupt. Device A's driver is suspended first and the device is powered down. Device B generates an interrupt. Interrupt handlers of both drivers are called. Device A's interrupt handler accesses registers of the powered down device and gets back bogus values (I assume all 0xff). That data is interpreted as interrupt status bits, etc. So, the interrupt handler gets confused and may produce some noise or enter an infinite loop, etc. This change affects only PCI devices. The pci(4) bus driver marks a child's interrupt handler as suspended after the child's suspend method is called and before the device is powered down. This is done only for traditional PCI interrupts, because only they can be shared. At the moment the change is only for x86. Notable changes in core subsystems / interfaces: - BUS_SUSPEND_INTR and BUS_RESUME_INTR methods are added to bus interface along with convenience functions bus_suspend_intr and bus_resume_intr; - rman_set_irq_cookie and rman_get_irq_cookie functions are added to provide a way to associate an interrupt resource with an interrupt cookie; - intr_event_suspend_handler and intr_event_resume_handler functions are added to the MI interrupt handler interface. I added two new interrupt handler flags, IH_SUSP and IH_CHANGED, to implement the new intr_event functions. IH_SUSP marks a suspended interrupt handler. IH_CHANGED is used to implement a barrier that ensures that a change to the interrupt handler's state is visible to future interrupts. While there, I fixed some whitespace issues in comments and changed a couple of logically boolean variables to be bool. MFC after: 1 month (maybe) Differential Revision: https://reviews.freebsd.org/D15755
2018-12-17 17:11:00 +00:00
if (pci_do_power_suspend) {
/*
* Make sure this device's interrupt handler is not invoked
* in the case the device uses a shared interrupt that can
* be raised by some other device.
* This is applicable only to regular (legacy) PCI interrupts
* as MSI/MSI-X interrupts are never shared.
*/
rle = resource_list_find(&dinfo->resources,
SYS_RES_IRQ, 0);
if (rle != NULL && rle->res != NULL)
(void)bus_suspend_intr(child, rle->res);
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
pci_set_power_child(dev, child, PCI_POWERSTATE_D3);
add support for marking interrupt handlers as suspended The goal of this change is to fix a problem with PCI shared interrupts during suspend and resume. I have observed a couple of variations of the following scenario. Devices A and B are on the same PCI bus and share the same interrupt. Device A's driver is suspended first and the device is powered down. Device B generates an interrupt. Interrupt handlers of both drivers are called. Device A's interrupt handler accesses registers of the powered down device and gets back bogus values (I assume all 0xff). That data is interpreted as interrupt status bits, etc. So, the interrupt handler gets confused and may produce some noise or enter an infinite loop, etc. This change affects only PCI devices. The pci(4) bus driver marks a child's interrupt handler as suspended after the child's suspend method is called and before the device is powered down. This is done only for traditional PCI interrupts, because only they can be shared. At the moment the change is only for x86. Notable changes in core subsystems / interfaces: - BUS_SUSPEND_INTR and BUS_RESUME_INTR methods are added to bus interface along with convenience functions bus_suspend_intr and bus_resume_intr; - rman_set_irq_cookie and rman_get_irq_cookie functions are added to provide a way to associate an interrupt resource with an interrupt cookie; - intr_event_suspend_handler and intr_event_resume_handler functions are added to the MI interrupt handler interface. I added two new interrupt handler flags, IH_SUSP and IH_CHANGED, to implement the new intr_event functions. IH_SUSP marks a suspended interrupt handler. IH_CHANGED is used to implement a barrier that ensures that a change to the interrupt handler's state is visible to future interrupts. While there, I fixed some whitespace issues in comments and changed a couple of logically boolean variables to be bool. MFC after: 1 month (maybe) Differential Revision: https://reviews.freebsd.org/D15755
2018-12-17 17:11:00 +00:00
}
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
return (0);
}
int
pci_resume_child(device_t dev, device_t child)
{
struct pci_devinfo *dinfo;
add support for marking interrupt handlers as suspended The goal of this change is to fix a problem with PCI shared interrupts during suspend and resume. I have observed a couple of variations of the following scenario. Devices A and B are on the same PCI bus and share the same interrupt. Device A's driver is suspended first and the device is powered down. Device B generates an interrupt. Interrupt handlers of both drivers are called. Device A's interrupt handler accesses registers of the powered down device and gets back bogus values (I assume all 0xff). That data is interpreted as interrupt status bits, etc. So, the interrupt handler gets confused and may produce some noise or enter an infinite loop, etc. This change affects only PCI devices. The pci(4) bus driver marks a child's interrupt handler as suspended after the child's suspend method is called and before the device is powered down. This is done only for traditional PCI interrupts, because only they can be shared. At the moment the change is only for x86. Notable changes in core subsystems / interfaces: - BUS_SUSPEND_INTR and BUS_RESUME_INTR methods are added to bus interface along with convenience functions bus_suspend_intr and bus_resume_intr; - rman_set_irq_cookie and rman_get_irq_cookie functions are added to provide a way to associate an interrupt resource with an interrupt cookie; - intr_event_suspend_handler and intr_event_resume_handler functions are added to the MI interrupt handler interface. I added two new interrupt handler flags, IH_SUSP and IH_CHANGED, to implement the new intr_event functions. IH_SUSP marks a suspended interrupt handler. IH_CHANGED is used to implement a barrier that ensures that a change to the interrupt handler's state is visible to future interrupts. While there, I fixed some whitespace issues in comments and changed a couple of logically boolean variables to be bool. MFC after: 1 month (maybe) Differential Revision: https://reviews.freebsd.org/D15755
2018-12-17 17:11:00 +00:00
struct resource_list_entry *rle;
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
if (pci_do_power_resume)
pci_set_power_child(dev, child, PCI_POWERSTATE_D0);
dinfo = device_get_ivars(child);
pci_cfg_restore(child, dinfo);
if (!device_is_attached(child))
pci_cfg_save(child, dinfo, 1);
bus_generic_resume_child(dev, child);
add support for marking interrupt handlers as suspended The goal of this change is to fix a problem with PCI shared interrupts during suspend and resume. I have observed a couple of variations of the following scenario. Devices A and B are on the same PCI bus and share the same interrupt. Device A's driver is suspended first and the device is powered down. Device B generates an interrupt. Interrupt handlers of both drivers are called. Device A's interrupt handler accesses registers of the powered down device and gets back bogus values (I assume all 0xff). That data is interpreted as interrupt status bits, etc. So, the interrupt handler gets confused and may produce some noise or enter an infinite loop, etc. This change affects only PCI devices. The pci(4) bus driver marks a child's interrupt handler as suspended after the child's suspend method is called and before the device is powered down. This is done only for traditional PCI interrupts, because only they can be shared. At the moment the change is only for x86. Notable changes in core subsystems / interfaces: - BUS_SUSPEND_INTR and BUS_RESUME_INTR methods are added to bus interface along with convenience functions bus_suspend_intr and bus_resume_intr; - rman_set_irq_cookie and rman_get_irq_cookie functions are added to provide a way to associate an interrupt resource with an interrupt cookie; - intr_event_suspend_handler and intr_event_resume_handler functions are added to the MI interrupt handler interface. I added two new interrupt handler flags, IH_SUSP and IH_CHANGED, to implement the new intr_event functions. IH_SUSP marks a suspended interrupt handler. IH_CHANGED is used to implement a barrier that ensures that a change to the interrupt handler's state is visible to future interrupts. While there, I fixed some whitespace issues in comments and changed a couple of logically boolean variables to be bool. MFC after: 1 month (maybe) Differential Revision: https://reviews.freebsd.org/D15755
2018-12-17 17:11:00 +00:00
/*
* Allow interrupts only after fully resuming the driver and hardware.
*/
if (pci_do_power_suspend) {
/* See pci_suspend_child for details. */
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
if (rle != NULL && rle->res != NULL)
(void)bus_resume_intr(child, rle->res);
}
Turn ACPI and PCI devices off or to a lower power state in suspend and back on again in resume. Override the default of D3 with the value the BIOS specifies in _SxD, if present. Skip serial devices (PNP05xx) since they seem to hang when set to D3 and may require special driver support. Also, skip non-type 0 PCI devices (i.e., bridges) since our we don't yet save/restore their config space and that seems to be necessary. If this gives you trouble with suspend/resume, you can disable the new ACPI and PCI power behavior separately with these tunables & sysctls: debug.acpi.do_powerstate hw.pci.do_powerstate Approved by: imp (pci) Tested by: acpi@ (numerous)
2004-12-02 08:07:12 +00:00
return (0);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
}
int
pci_resume(device_t dev)
{
Move setting power state for children into a separate function as they were essentially the same. This also restores hw.pci.do_power_resume tunable, which was broken since r211430. Reviewed by: jhb
2010-10-15 21:39:51 +00:00
device_t child, *devlist;
int error, i, numdevs;
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
Cope with errors from device_get_children(). These errors can happen only in low memory situations, so the error fork of these fixes is lightly tested, but they should do the least-wrong thing... Submitted by: Hans Petter Selasky
2008-08-23 07:23:52 +00:00
if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
return (error);
Resume critical PCI devices (and their children) first, then everything else later. This give us better chance to catch device driver problems.
2010-11-22 21:58:00 +00:00
/*
* Resume critical devices first, then everything else later.
*/
for (i = 0; i < numdevs; i++) {
child = devlist[i];
switch (pci_get_class(child)) {
case PCIC_DISPLAY:
case PCIC_MEMORY:
case PCIC_BRIDGE:
case PCIC_BASEPERIPH:
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
BUS_RESUME_CHILD(dev, child);
Resume critical PCI devices (and their children) first, then everything else later. This give us better chance to catch device driver problems.
2010-11-22 21:58:00 +00:00
break;
}
}
for (i = 0; i < numdevs; i++) {
child = devlist[i];
switch (pci_get_class(child)) {
case PCIC_DISPLAY:
case PCIC_MEMORY:
case PCIC_BRIDGE:
case PCIC_BASEPERIPH:
break;
default:
Stage one of multipass suspend/resume Summary: Add the beginnings of multipass suspend/resume, by introducing BUS_SUSPEND_CHILD/BUS_RESUME_CHILD, and move the PCI driver to this. Reviewers: jhb Reviewed By: jhb Differential Revision: https://reviews.freebsd.org/D590
2014-09-23 02:56:40 +00:00
BUS_RESUME_CHILD(dev, child);
Resume critical PCI devices (and their children) first, then everything else later. This give us better chance to catch device driver problems.
2010-11-22 21:58:00 +00:00
}
}
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
free(devlist, M_TEMP);
Resume critical PCI devices (and their children) first, then everything else later. This give us better chance to catch device driver problems.
2010-11-22 21:58:00 +00:00
return (0);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
}
- Make pci_load_vendor_data() static and do it during MOD_LOAD instead of when the first PCI bus attaches. - Create /dev/pci during MOD_LOAD as well. - Destroy /dev/pci during MOD_UNLOAD (not that you can kldunload pci, but might as well get the code right)
2002-09-04 03:13:16 +00:00
static void
Various changes to make it easier to subclass the PCI bus device. - Make the pci devclass a global variable. - Add child devices in pci_attach() instead of pci_probe(). Change pci_probe() to just check for a valid bus number from the associated bridge and return -1000 if successful. This allows subclasses of the PCI bus driver to override the generic driver. - Move the code to load the vendor data into its own public function. Really though, doing this at attach is just plain wrong. This should really be done in the module load routine instead. As a side effect, the 'busno' variable in pci_attach() is now no longer static (minor bug that was harmless so far.) - Change pci_add_children() to take an extra argument that is the size of the device info structure passed to pci_read_device() and make it public so subclasses of the PCI bus can call it in their attach routines. - Move the bits to attach a probed PCI child to a PCI bus into a global pci_add_child() function. This will allow subclasses that can detect a PCI device not found in the normal PCI probe to add those devices in their own attach routine. (I have seen this in the ACPI tree on my laptop for example.) As a side effect, change the static function pci_add_resources() to get the busno, slot, and func from the passed in dinfo structure instead of requiring them as function arguments. Tested on: i386, alpha, ia64, sparc64
2002-08-26 15:23:52 +00:00
pci_load_vendor_data(void)
{
Use the preload_fetch_addr() and preload_fetch_size() convenience functions to obtain the address and size of the PCI vendor data. Sponsored by: Juniper Networks.
2011-02-13 19:26:51 +00:00
caddr_t data;
void *ptr;
size_t sz;
data = preload_search_by_type("pci_vendor_data");
if (data != NULL) {
ptr = preload_fetch_addr(data);
sz = preload_fetch_size(data);
if (ptr != NULL && sz != 0) {
pci_vendordata = ptr;
pci_vendordata_size = sz;
/* terminate the database */
pci_vendordata[pci_vendordata_size] = '\n';
}
Convert DEVFS hooks in (most) drivers to make_dev(). Diskslice/label code not yet handled. Vinum, i4b, alpha, pc98 not dealt with (left to respective Maintainers) Add the correct hook for devfs to kern_conf.c The net result of this excercise is that a lot less files depends on DEVFS, and devtoname() gets more sensible output in many cases. A few drivers had minor additional cleanups performed relating to cdevsw registration. A few drivers don't register a cdevsw{} anymore, but only use make_dev().
1999-08-23 20:59:21 +00:00
}
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
void
pci_driver_added(device_t dev, driver_t *driver)
{
int numdevs;
device_t *devlist;
device_t child;
struct pci_devinfo *dinfo;
int i;
make the pci power state and resource code a lot less chatty. The chattiness was left in for debugging, but now that nearly all of the problems relating to the changes have been fixed, it is only annoying. It is still available via bootverbose. Prodded by: jhb
2004-05-21 06:03:26 +00:00
if (bootverbose)
device_printf(dev, "driver added\n");
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
DEVICE_IDENTIFY(driver, dev);
Cope with errors from device_get_children(). These errors can happen only in low memory situations, so the error fork of these fixes is lightly tested, but they should do the least-wrong thing... Submitted by: Hans Petter Selasky
2008-08-23 07:23:52 +00:00
if (device_get_children(dev, &devlist, &numdevs) != 0)
return;
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
for (i = 0; i < numdevs; i++) {
child = devlist[i];
if (device_get_state(child) != DS_NOTPRESENT)
continue;
dinfo = device_get_ivars(child);
pci_print_verbose(dinfo);
make the pci power state and resource code a lot less chatty. The chattiness was left in for debugging, but now that nearly all of the problems relating to the changes have been fixed, it is only annoying. It is still available via bootverbose. Prodded by: jhb
2004-05-21 06:03:26 +00:00
if (bootverbose)
Add an internal pci_printf() routine similar to device_printf() except that it prefixes the output with 'pci<domain>:<bus>:<device>:<function>: '.
2009-06-01 20:30:00 +00:00
pci_printf(&dinfo->cfg, "reprobing on driver added\n");
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
pci_cfg_restore(child, dinfo);
if (device_probe_and_attach(child) != 0)
Make detaching drivers from PCI devices more robust. While here, fix a bug where a PCI device would be powered down if it failed to probe, but not when its driver was detached (e.g. via kldunload). - Add a new helper method resource_list_release_active() which forcefully releases any active resources of a specified type from a resource list. - Add a bus_child_detached method for the PCI bus driver which forces any active resources to be released (and whines to the console if it finds any) and then powers the device down. - Call pci_child_detached() if we fail to probe a device when a driver is kldloaded. This isn't perfect but can avoid leaking resources from a probe() routine in the kldload case. Reviewed by: imp, brooks MFC after: 1 month
2013-06-27 20:21:54 +00:00
pci_child_detached(dev, child);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
}
free(devlist, M_TEMP);
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
int
pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
{
struct pci_devinfo *dinfo;
struct msix_table_entry *mte;
struct msix_vector *mv;
uint64_t addr;
uint32_t data;
void *cookie;
int error, rid;
error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
arg, &cookie);
if (error)
return (error);
Extend the management of PCIM_CMD_INTxDIS. We now explicitly enable INTx during bus_setup_intr() if it is needed. Several of the ata drivers were managing this bit internally. This is better handled in pci and it should work for all drivers now. We also mask INTx during bus_teardown_intr() by setting this bit. Reviewed by: jhb MFC after: 3 days
2009-03-04 18:23:48 +00:00
/* If this is not a direct child, just bail out. */
if (device_get_parent(child) != dev) {
*cookiep = cookie;
return(0);
}
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
rid = rman_get_rid(irq);
Extend the management of PCIM_CMD_INTxDIS. We now explicitly enable INTx during bus_setup_intr() if it is needed. Several of the ata drivers were managing this bit internally. This is better handled in pci and it should work for all drivers now. We also mask INTx during bus_teardown_intr() by setting this bit. Reviewed by: jhb MFC after: 3 days
2009-03-04 18:23:48 +00:00
if (rid == 0) {
/* Make sure that INTx is enabled */
pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
} else {
/*
* Check to see if the interrupt is MSI or MSI-X.
* Ask our parent to map the MSI and give
* us the address and data register values.
* If we fail for some reason, teardown the
* interrupt handler.
*/
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
dinfo = device_get_ivars(child);
if (dinfo->cfg.msi.msi_alloc > 0) {
if (dinfo->cfg.msi.msi_addr == 0) {
KASSERT(dinfo->cfg.msi.msi_handlers == 0,
("MSI has handlers, but vectors not mapped"));
error = PCIB_MAP_MSI(device_get_parent(dev),
child, rman_get_start(irq), &addr, &data);
if (error)
goto bad;
dinfo->cfg.msi.msi_addr = addr;
dinfo->cfg.msi.msi_data = data;
}
Enable MSI in the MSI capability registers any time that the first message in an MSI group is enabled, not just if the address/data pair are not initialized. Reported by: rnoland MFC after: 1 week
2009-06-22 20:08:06 +00:00
if (dinfo->cfg.msi.msi_handlers == 0)
pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
dinfo->cfg.msi.msi_data);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
dinfo->cfg.msi.msi_handlers++;
} else {
KASSERT(dinfo->cfg.msix.msix_alloc > 0,
("No MSI or MSI-X interrupts allocated"));
KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
("MSI-X index too high"));
mte = &dinfo->cfg.msix.msix_table[rid - 1];
KASSERT(mte->mte_vector != 0, ("no message vector"));
mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
KASSERT(mv->mv_irq == rman_get_start(irq),
("IRQ mismatch"));
if (mv->mv_address == 0) {
KASSERT(mte->mte_handlers == 0,
("MSI-X table entry has handlers, but vector not mapped"));
error = PCIB_MAP_MSI(device_get_parent(dev),
child, rman_get_start(irq), &addr, &data);
if (error)
goto bad;
mv->mv_address = addr;
mv->mv_data = data;
}
Add MSIX rewrite table quirk for use with VMs. This patch solves IRQ generation problems using the mlx5en(4) driver with xenserver v6.5.0 in SRIOV and PCI-passthrough modes. Until further the hw.pci.msix_rewrite_table quirk must be set manually in /boot/loader.conf . Reviewed by: jhb @ Sponsored by: Mellanox Technologies MFC after: 2 weeks
2016-12-30 08:37:30 +00:00
/*
* The MSIX table entry must be made valid by
* incrementing the mte_handlers before
* calling pci_enable_msix() and
* pci_resume_msix(). Else the MSIX rewrite
* table quirk will not work as expected.
*/
mte->mte_handlers++;
if (mte->mte_handlers == 1) {
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
pci_enable_msix(child, rid - 1, mv->mv_address,
mv->mv_data);
pci_unmask_msix(child, rid - 1);
}
}
Extend the management of PCIM_CMD_INTxDIS. We now explicitly enable INTx during bus_setup_intr() if it is needed. Several of the ata drivers were managing this bit internally. This is better handled in pci and it should work for all drivers now. We also mask INTx during bus_teardown_intr() by setting this bit. Reviewed by: jhb MFC after: 3 days
2009-03-04 18:23:48 +00:00
- Make PCI_QUIRK_MSI_INTX_BUG work by using the ID of the actual PCI device for the lookup. - For devices affected by PCI_QUIRK_MSI_INTX_BUG, ensure PCIM_CMD_INTxDIS is cleared when using MSI/MSI-X. - Employ PCI_QUIRK_MSI_INTX_BUG for BCM5714(S)/BCM5715(S)/BCM5780(S) rather than clearing PCIM_CMD_INTxDIS unconditionally for all devices in bge(4). MFC after: 3 days
2014-12-27 14:26:18 +00:00
/*
* Make sure that INTx is disabled if we are using MSI/MSI-X,
* unless the device is affected by PCI_QUIRK_MSI_INTX_BUG,
* in which case we "enable" INTx so MSI/MSI-X actually works.
*/
if (!pci_has_quirk(pci_get_devid(child),
PCI_QUIRK_MSI_INTX_BUG))
Add new quirk PCI_QUIRK_MSI_INTX_BUG to pci(4). QAC AR816x/E2200 controller has a silicon bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of command register is set. Reviewed by: jhb
2014-10-08 05:34:39 +00:00
pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
- Make PCI_QUIRK_MSI_INTX_BUG work by using the ID of the actual PCI device for the lookup. - For devices affected by PCI_QUIRK_MSI_INTX_BUG, ensure PCIM_CMD_INTxDIS is cleared when using MSI/MSI-X. - Employ PCI_QUIRK_MSI_INTX_BUG for BCM5714(S)/BCM5715(S)/BCM5780(S) rather than clearing PCIM_CMD_INTxDIS unconditionally for all devices in bge(4). MFC after: 3 days
2014-12-27 14:26:18 +00:00
else
pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
bad:
if (error) {
(void)bus_generic_teardown_intr(dev, child, irq,
cookie);
return (error);
}
}
*cookiep = cookie;
return (0);
}
int
pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
void *cookie)
{
struct msix_table_entry *mte;
struct resource_list_entry *rle;
struct pci_devinfo *dinfo;
int error, rid;
if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
return (EINVAL);
Extend the management of PCIM_CMD_INTxDIS. We now explicitly enable INTx during bus_setup_intr() if it is needed. Several of the ata drivers were managing this bit internally. This is better handled in pci and it should work for all drivers now. We also mask INTx during bus_teardown_intr() by setting this bit. Reviewed by: jhb MFC after: 3 days
2009-03-04 18:23:48 +00:00
/* If this isn't a direct child, just bail out */
if (device_get_parent(child) != dev)
return(bus_generic_teardown_intr(dev, child, irq, cookie));
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
rid = rman_get_rid(irq);
Invert the logic error for the MSI/MSIX vs INTx case. Pointyhat to: me MFC after: 3 days
2009-03-06 11:24:42 +00:00
if (rid == 0) {
Extend the management of PCIM_CMD_INTxDIS. We now explicitly enable INTx during bus_setup_intr() if it is needed. Several of the ata drivers were managing this bit internally. This is better handled in pci and it should work for all drivers now. We also mask INTx during bus_teardown_intr() by setting this bit. Reviewed by: jhb MFC after: 3 days
2009-03-04 18:23:48 +00:00
/* Mask INTx */
pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
} else {
/*
* Check to see if the interrupt is MSI or MSI-X. If so,
* decrement the appropriate handlers count and mask the
* MSI-X message, or disable MSI messages if the count
* drops to 0.
*/
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
dinfo = device_get_ivars(child);
rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
if (rle->res != irq)
return (EINVAL);
if (dinfo->cfg.msi.msi_alloc > 0) {
KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
("MSI-X index too high"));
if (dinfo->cfg.msi.msi_handlers == 0)
return (EINVAL);
dinfo->cfg.msi.msi_handlers--;
if (dinfo->cfg.msi.msi_handlers == 0)
pci_disable_msi(child);
} else {
KASSERT(dinfo->cfg.msix.msix_alloc > 0,
("No MSI or MSI-X interrupts allocated"));
KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
("MSI-X index too high"));
mte = &dinfo->cfg.msix.msix_table[rid - 1];
if (mte->mte_handlers == 0)
return (EINVAL);
mte->mte_handlers--;
if (mte->mte_handlers == 0)
pci_mask_msix(child, rid - 1);
}
}
error = bus_generic_teardown_intr(dev, child, irq, cookie);
Extend the management of PCIM_CMD_INTxDIS. We now explicitly enable INTx during bus_setup_intr() if it is needed. Several of the ata drivers were managing this bit internally. This is better handled in pci and it should work for all drivers now. We also mask INTx during bus_teardown_intr() by setting this bit. Reviewed by: jhb MFC after: 3 days
2009-03-04 18:23:48 +00:00
if (rid > 0)
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
KASSERT(error == 0,
("%s: generic teardown failed for MSI/MSI-X", __func__));
return (error);
}
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
int
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
pci_print_child(device_t dev, device_t child)
{
Print 'irq nn' on the device attach line like the old pci code did. However, we are not printing 'int a/b/c/d' yet, is it worth it on non-SMP systems? (It's useful when tracing PCI->IO-APIC routing on SMP systems)
1999-05-08 20:28:01 +00:00
struct pci_devinfo *dinfo;
Show the port/mem/irq of pci devices too.
2000-01-08 10:12:21 +00:00
struct resource_list *rl;
Alter the behavior of sys/kern/subr_bus.c:device_print_child() - device_print_child() either lets the BUS_PRINT_CHILD method produce the entire device announcement message or it prints "foo0: not found\n" Alter sys/kern/subr_bus.c:bus_generic_print_child() to take on the previous behavior of device_print_child() (printing the "foo0: <FooDevice 1.1>" bit of the announce message.) Provide bus_print_child_header() and bus_print_child_footer() to actually print the output for bus_generic_print_child(). These functions should be used whenever possible (unless you can just use bus_generic_print_child()) The BUS_PRINT_CHILD method now returns int instead of void. Modify everything else that defines or uses a BUS_PRINT_CHILD method to comply with the above changes. - Devices are 'on' a bus, not 'at' it. - If a custom BUS_PRINT_CHILD method does the same thing as bus_generic_print_child(), use bus_generic_print_child() - Use device_get_nameunit() instead of both device_get_name() and device_get_unit() - All BUS_PRINT_CHILD methods return the number of characters output. Reviewed by: dfr, peter
1999-07-29 01:03:04 +00:00
int retval = 0;
Print 'irq nn' on the device attach line like the old pci code did. However, we are not printing 'int a/b/c/d' yet, is it worth it on non-SMP systems? (It's useful when tracing PCI->IO-APIC routing on SMP systems)
1999-05-08 20:28:01 +00:00
dinfo = device_get_ivars(child);
Show the port/mem/irq of pci devices too.
2000-01-08 10:12:21 +00:00
rl = &dinfo->resources;
Alter the behavior of sys/kern/subr_bus.c:device_print_child() - device_print_child() either lets the BUS_PRINT_CHILD method produce the entire device announcement message or it prints "foo0: not found\n" Alter sys/kern/subr_bus.c:bus_generic_print_child() to take on the previous behavior of device_print_child() (printing the "foo0: <FooDevice 1.1>" bit of the announce message.) Provide bus_print_child_header() and bus_print_child_footer() to actually print the output for bus_generic_print_child(). These functions should be used whenever possible (unless you can just use bus_generic_print_child()) The BUS_PRINT_CHILD method now returns int instead of void. Modify everything else that defines or uses a BUS_PRINT_CHILD method to comply with the above changes. - Devices are 'on' a bus, not 'at' it. - If a custom BUS_PRINT_CHILD method does the same thing as bus_generic_print_child(), use bus_generic_print_child() - Use device_get_nameunit() instead of both device_get_name() and device_get_unit() - All BUS_PRINT_CHILD methods return the number of characters output. Reviewed by: dfr, peter
1999-07-29 01:03:04 +00:00
retval += bus_print_child_header(dev, child);
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx");
retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
Show the port/mem/irq of pci devices too.
2000-01-08 10:12:21 +00:00
if (device_get_flags(dev))
retval += printf(" flags %#x", device_get_flags(dev));
Alter the behavior of sys/kern/subr_bus.c:device_print_child() - device_print_child() either lets the BUS_PRINT_CHILD method produce the entire device announcement message or it prints "foo0: not found\n" Alter sys/kern/subr_bus.c:bus_generic_print_child() to take on the previous behavior of device_print_child() (printing the "foo0: <FooDevice 1.1>" bit of the announce message.) Provide bus_print_child_header() and bus_print_child_footer() to actually print the output for bus_generic_print_child(). These functions should be used whenever possible (unless you can just use bus_generic_print_child()) The BUS_PRINT_CHILD method now returns int instead of void. Modify everything else that defines or uses a BUS_PRINT_CHILD method to comply with the above changes. - Devices are 'on' a bus, not 'at' it. - If a custom BUS_PRINT_CHILD method does the same thing as bus_generic_print_child(), use bus_generic_print_child() - Use device_get_nameunit() instead of both device_get_name() and device_get_unit() - All BUS_PRINT_CHILD methods return the number of characters output. Reviewed by: dfr, peter
1999-07-29 01:03:04 +00:00
retval += printf(" at device %d.%d", pci_get_slot(child),
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
pci_get_function(child));
Alter the behavior of sys/kern/subr_bus.c:device_print_child() - device_print_child() either lets the BUS_PRINT_CHILD method produce the entire device announcement message or it prints "foo0: not found\n" Alter sys/kern/subr_bus.c:bus_generic_print_child() to take on the previous behavior of device_print_child() (printing the "foo0: <FooDevice 1.1>" bit of the announce message.) Provide bus_print_child_header() and bus_print_child_footer() to actually print the output for bus_generic_print_child(). These functions should be used whenever possible (unless you can just use bus_generic_print_child()) The BUS_PRINT_CHILD method now returns int instead of void. Modify everything else that defines or uses a BUS_PRINT_CHILD method to comply with the above changes. - Devices are 'on' a bus, not 'at' it. - If a custom BUS_PRINT_CHILD method does the same thing as bus_generic_print_child(), use bus_generic_print_child() - Use device_get_nameunit() instead of both device_get_name() and device_get_unit() - All BUS_PRINT_CHILD methods return the number of characters output. Reviewed by: dfr, peter
1999-07-29 01:03:04 +00:00
Add a bus method to fetch the VM domain for the given device/bus. * Add a bus_if.m method - get_domain() - returning the VM domain or ENOENT if the device isn't in a VM domain; * Add bus methods to print out the domain of the device if appropriate; * Add code in srat.c to save the PXM -> VM domain mapping that's done and expose a function to translate VM domain -> PXM; * Add ACPI and ACPI PCI methods to check if the bus has a _PXM attribute and if so map it to the VM domain; * (.. yes, this works recursively.) * Have the pci bus glue print out the device VM domain if present. Note: this is just the plumbing to start enumerating information - it doesn't at all modify behaviour. Differential Revision: D906 Reviewed by: jhb Sponsored by: Norse Corp
2014-10-09 05:33:25 +00:00
retval += bus_print_child_domain(dev, child);
Alter the behavior of sys/kern/subr_bus.c:device_print_child() - device_print_child() either lets the BUS_PRINT_CHILD method produce the entire device announcement message or it prints "foo0: not found\n" Alter sys/kern/subr_bus.c:bus_generic_print_child() to take on the previous behavior of device_print_child() (printing the "foo0: <FooDevice 1.1>" bit of the announce message.) Provide bus_print_child_header() and bus_print_child_footer() to actually print the output for bus_generic_print_child(). These functions should be used whenever possible (unless you can just use bus_generic_print_child()) The BUS_PRINT_CHILD method now returns int instead of void. Modify everything else that defines or uses a BUS_PRINT_CHILD method to comply with the above changes. - Devices are 'on' a bus, not 'at' it. - If a custom BUS_PRINT_CHILD method does the same thing as bus_generic_print_child(), use bus_generic_print_child() - Use device_get_nameunit() instead of both device_get_name() and device_get_unit() - All BUS_PRINT_CHILD methods return the number of characters output. Reviewed by: dfr, peter
1999-07-29 01:03:04 +00:00
retval += bus_print_child_footer(dev, child);
return (retval);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
- Complete r231621 by also blacklisting the bridge used by VMware for PCIe devices. While at it, update the comment now that we know that MSI-X doesn't work with ESXi 5.1 for Intel 82576 either and the underlying issue is a bug in the MSI-X allocation code of the hypervisor. Reported by: Harald Schmalzbauer - Make the nomatch table const. MFC after: 1 week
2013-03-02 15:54:02 +00:00
static const struct
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
{
- Complete r231621 by also blacklisting the bridge used by VMware for PCIe devices. While at it, update the comment now that we know that MSI-X doesn't work with ESXi 5.1 for Intel 82576 either and the underlying issue is a bug in the MSI-X allocation code of the hypervisor. Reported by: Harald Schmalzbauer - Make the nomatch table const. MFC after: 1 week
2013-03-02 15:54:02 +00:00
int class;
int subclass;
Make uninteresting PCI devices with no attached drivers only print out on a verbose boot MFC after: 2 weeks
2014-04-30 16:42:12 +00:00
int report; /* 0 = bootverbose, 1 = always */
- Complete r231621 by also blacklisting the bridge used by VMware for PCIe devices. While at it, update the comment now that we know that MSI-X doesn't work with ESXi 5.1 for Intel 82576 either and the underlying issue is a bug in the MSI-X allocation code of the hypervisor. Reported by: Harald Schmalzbauer - Make the nomatch table const. MFC after: 1 week
2013-03-02 15:54:02 +00:00
const char *desc;
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
} pci_nomatch_tab[] = {
Make uninteresting PCI devices with no attached drivers only print out on a verbose boot MFC after: 2 weeks
2014-04-30 16:42:12 +00:00
{PCIC_OLD, -1, 1, "old"},
{PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
{PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
{PCIC_STORAGE, -1, 1, "mass storage"},
{PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"},
{PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"},
{PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"},
{PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"},
{PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"},
{PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"},
{PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"},
{PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"},
{PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"},
{PCIC_NETWORK, -1, 1, "network"},
{PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"},
{PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"},
{PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"},
{PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"},
{PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"},
{PCIC_DISPLAY, -1, 1, "display"},
{PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"},
{PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"},
{PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"},
{PCIC_MULTIMEDIA, -1, 1, "multimedia"},
{PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"},
{PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"},
{PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"},
{PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"},
{PCIC_MEMORY, -1, 1, "memory"},
{PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"},
{PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"},
{PCIC_BRIDGE, -1, 1, "bridge"},
{PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
{PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
{PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
{PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
{PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
{PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
{PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
{PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
{PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
{PCIC_SIMPLECOMM, -1, 1, "simple comms"},
{PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */
{PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"},
{PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"},
{PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"},
{PCIC_BASEPERIPH, -1, 0, "base peripheral"},
{PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"},
{PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"},
{PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"},
{PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"},
{PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
{PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"},
Add IOMMU PCI subclass, found on Tyan S8236 motherboard. Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com> MFC after: 2 weeks
2014-05-20 14:39:22 +00:00
{PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"},
Make uninteresting PCI devices with no attached drivers only print out on a verbose boot MFC after: 2 weeks
2014-04-30 16:42:12 +00:00
{PCIC_INPUTDEV, -1, 1, "input device"},
{PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"},
{PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"},
{PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"},
{PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"},
{PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"},
{PCIC_DOCKING, -1, 1, "docking station"},
{PCIC_PROCESSOR, -1, 1, "processor"},
{PCIC_SERIALBUS, -1, 1, "serial bus"},
{PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"},
{PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"},
{PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"},
{PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"},
{PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"},
{PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"},
{PCIC_WIRELESS, -1, 1, "wireless controller"},
{PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"},
{PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"},
{PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"},
{PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
{PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"},
{PCIC_SATCOM, -1, 1, "satellite communication"},
{PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"},
{PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"},
{PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"},
{PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"},
{PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
{PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"},
{PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"},
{PCIC_DASP, -1, 0, "dasp"},
{PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"},
Add names for some DASP devices. Submitted by: Dmitry Luhtionov <dmitryluhtionov@gmail.com> MFC after: 1 week
2016-10-21 15:23:54 +00:00
{PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"},
{PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"},
{PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"},
Make uninteresting PCI devices with no attached drivers only print out on a verbose boot MFC after: 2 weeks
2014-04-30 16:42:12 +00:00
{0, 0, 0, NULL}
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
};
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
void
Implement the BUS_PROBE_NOMATCH method for the PCI bus. This function is called for each device for which no driver was found. Output is similar to the eisa_probe_nomatch() function but with the added benefit of displaying the assigned IRQ (since PCI gives us this information up front.) Output is like so: pci0: unknown card CPQ0508 (vendor=0x0e11, dev=0x0508) at 11.0 irq 9 pci0: unknown card DFZ0508 (vendor=0x10da, dev=0x0508) at 11.0 irq 9 pci0: unknown card DBL0508 (vendor=0x104c, dev=0x0508) at 11.0 irq 9 pci0: unknown card DDM0011 (vendor=0x108d, dev=0x0011) at 11.0 irq 9 I'm not happy with the 3 lines of macro cruft that got added but I consider it a temporary annoyance as those bits will be moved to some place where PCI, EISA and ISAPNP code will be able to use them. (Not surprisingly, this message is longer than the code in question.) Reviewed by: peter, dfr
1999-07-27 04:28:14 +00:00
pci_probe_nomatch(device_t dev, device_t child)
{
Make uninteresting PCI devices with no attached drivers only print out on a verbose boot MFC after: 2 weeks
2014-04-30 16:42:12 +00:00
int i, report;
- Complete r231621 by also blacklisting the bridge used by VMware for PCIe devices. While at it, update the comment now that we know that MSI-X doesn't work with ESXi 5.1 for Intel 82576 either and the underlying issue is a bug in the MSI-X allocation code of the hypervisor. Reported by: Harald Schmalzbauer - Make the nomatch table const. MFC after: 1 week
2013-03-02 15:54:02 +00:00
const char *cp, *scp;
char *device;
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
/*
* Look for a listing for this device in a loaded device database.
*/
Make uninteresting PCI devices with no attached drivers only print out on a verbose boot MFC after: 2 weeks
2014-04-30 16:42:12 +00:00
report = 1;
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
if ((device = pci_describe_device(child)) != NULL) {
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
device_printf(dev, "<%s>", device);
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
free(device, M_DEVBUF);
} else {
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
/*
* Scan the class/subclass descriptions for a general
* description.
*/
cp = "unknown";
scp = NULL;
for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
if (pci_nomatch_tab[i].class == pci_get_class(child)) {
if (pci_nomatch_tab[i].subclass == -1) {
cp = pci_nomatch_tab[i].desc;
Make uninteresting PCI devices with no attached drivers only print out on a verbose boot MFC after: 2 weeks
2014-04-30 16:42:12 +00:00
report = pci_nomatch_tab[i].report;
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
} else if (pci_nomatch_tab[i].subclass ==
pci_get_subclass(child)) {
scp = pci_nomatch_tab[i].desc;
Make uninteresting PCI devices with no attached drivers only print out on a verbose boot MFC after: 2 weeks
2014-04-30 16:42:12 +00:00
report = pci_nomatch_tab[i].report;
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
}
}
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
}
Make uninteresting PCI devices with no attached drivers only print out on a verbose boot MFC after: 2 weeks
2014-04-30 16:42:12 +00:00
if (report || bootverbose) {
device_printf(dev, "<%s%s%s>",
cp ? cp : "",
((cp != NULL) && (scp != NULL)) ? ", " : "",
scp ? scp : "");
}
}
if (report || bootverbose) {
printf(" at device %d.%d (no driver attached)\n",
pci_get_slot(child), pci_get_function(child));
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
}
Remove unnecessary castings and fix couple of style(9) nits.
2010-10-15 21:41:59 +00:00
pci_cfg_save(child, device_get_ivars(child), 1);
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
}
Move the pretty printing of the description for USB controllers to pci_probe_nomatch, so it won't be in the way when loading USB as a module. The reason for them being there in the first place is that every motherboard comes with USB kit and this way it looks more pretty (peter). The real solution will be to define some method of detaching a driver after it has attached.
1999-11-22 03:34:43 +00:00
Make detaching drivers from PCI devices more robust. While here, fix a bug where a PCI device would be powered down if it failed to probe, but not when its driver was detached (e.g. via kldunload). - Add a new helper method resource_list_release_active() which forcefully releases any active resources of a specified type from a resource list. - Add a bus_child_detached method for the PCI bus driver which forces any active resources to be released (and whines to the console if it finds any) and then powers the device down. - Call pci_child_detached() if we fail to probe a device when a driver is kldloaded. This isn't perfect but can avoid leaking resources from a probe() routine in the kldload case. Reviewed by: imp, brooks MFC after: 1 month
2013-06-27 20:21:54 +00:00
void
pci_child_detached(device_t dev, device_t child)
{
struct pci_devinfo *dinfo;
struct resource_list *rl;
dinfo = device_get_ivars(child);
rl = &dinfo->resources;
/*
* Have to deallocate IRQs before releasing any MSI messages and
* have to release MSI messages before deallocating any memory
* BARs.
*/
if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
(void)pci_release_msi(child);
}
if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
#ifdef PCI_RES_BUS
if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0)
pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n");
#endif
Make detaching drivers from PCI devices more robust. While here, fix a bug where a PCI device would be powered down if it failed to probe, but not when its driver was detached (e.g. via kldunload). - Add a new helper method resource_list_release_active() which forcefully releases any active resources of a specified type from a resource list. - Add a bus_child_detached method for the PCI bus driver which forces any active resources to be released (and whines to the console if it finds any) and then powers the device down. - Call pci_child_detached() if we fail to probe a device when a driver is kldloaded. This isn't perfect but can avoid leaking resources from a probe() routine in the kldload case. Reviewed by: imp, brooks MFC after: 1 month
2013-06-27 20:21:54 +00:00
pci_cfg_save(child, dinfo, 1);
}
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
/*
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
* Parse the PCI device database, if loaded, and return a pointer to a
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
* description of the device.
*
* The database is flat text formatted as follows:
*
* Any line not in a valid format is ignored.
* Lines are terminated with newline '\n' characters.
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
*
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
* A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
* the vendor name.
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
*
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
* A DEVICE line is entered immediately below the corresponding VENDOR ID.
* - devices cannot be listed without a corresponding VENDOR line.
* A DEVICE line consists of a TAB, the 4 digit (hex) device code,
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
* another TAB, then the device name.
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
*/
/*
* Assuming (ptr) points to the beginning of a line in the database,
* return the vendor or device and description of the next entry.
* The value of (vendor) or (device) inappropriate for the entry type
* is set to -1. Returns nonzero at the end of the database.
*
* Note that this is slightly unrobust in the face of corrupt data;
* we attempt to safeguard against this by spamming the end of the
* database with a newline when we initialise.
*/
static int
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
{
char *cp = *ptr;
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
int left;
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
*device = -1;
*vendor = -1;
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
**desc = '\0';
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
for (;;) {
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
left = pci_vendordata_size - (cp - pci_vendordata);
if (left <= 0) {
*ptr = cp;
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
return(1);
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
}
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
/* vendor entry? */
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
if (*cp != '\t' &&
sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
break;
/* device entry? */
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
if (*cp == '\t' &&
sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
break;
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
/* skip to next line */
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
while (*cp != '\n' && left > 0) {
cp++;
left--;
}
if (*cp == '\n') {
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
cp++;
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
left--;
}
}
/* skip to next line */
while (*cp != '\n' && left > 0) {
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
cp++;
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
left--;
o No need to print the vendor/device ID for things that matched succesfully. o ``<device name>'' versus ``device name'' for things that fall under nomatch. Reviewed by: dfr (in principle) Approved by: Baron von Hubbard
2000-02-22 21:44:39 +00:00
}
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
if (*cp == '\n' && left > 0)
cp++;
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
*ptr = cp;
return(0);
}
static char *
pci_describe_device(device_t dev)
{
int vendor, device;
char *desc, *vp, *dp, *line;
desc = vp = dp = NULL;
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
/*
* If we have no vendor data, we can't do anything.
*/
if (pci_vendordata == NULL)
goto out;
/*
* Scan the vendor data looking for this device
*/
line = pci_vendordata;
if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
goto out;
for (;;) {
if (pci_describe_parse_line(&line, &vendor, &device, &vp))
goto out;
if (vendor == pci_get_vendor(dev))
break;
o No need to print the vendor/device ID for things that matched succesfully. o ``<device name>'' versus ``device name'' for things that fall under nomatch. Reviewed by: dfr (in principle) Approved by: Baron von Hubbard
2000-02-22 21:44:39 +00:00
}
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
goto out;
for (;;) {
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
*dp = 0;
break;
}
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
if (vendor != -1) {
*dp = 0;
break;
}
if (device == pci_get_device(dev))
break;
Implement the BUS_PROBE_NOMATCH method for the PCI bus. This function is called for each device for which no driver was found. Output is similar to the eisa_probe_nomatch() function but with the added benefit of displaying the assigned IRQ (since PCI gives us this information up front.) Output is like so: pci0: unknown card CPQ0508 (vendor=0x0e11, dev=0x0508) at 11.0 irq 9 pci0: unknown card DFZ0508 (vendor=0x10da, dev=0x0508) at 11.0 irq 9 pci0: unknown card DBL0508 (vendor=0x104c, dev=0x0508) at 11.0 irq 9 pci0: unknown card DDM0011 (vendor=0x108d, dev=0x0011) at 11.0 irq 9 I'm not happy with the 3 lines of macro cruft that got added but I consider it a temporary annoyance as those bits will be moved to some place where PCI, EISA and ISAPNP code will be able to use them. (Not surprisingly, this message is longer than the code in question.) Reviewed by: peter, dfr
1999-07-27 04:28:14 +00:00
}
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
if (dp[0] == '\0')
snprintf(dp, 80, "0x%x", pci_get_device(dev));
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
NULL)
- Fix the device database parsing code so that it actually works. - Improve the formatting for devices identified by the database. - Fix the pcib_route_interrupt method definition, as an old version snuck in here somehow 8( - Remove a couple of the vendor/device IDs for PCI:ISA bridges which correctly identify themselves. Submitted by: peter
2000-12-09 09:15:38 +00:00
sprintf(desc, "%s, %s", vp, dp);
Fix couple of style nits.
2012-03-29 19:29:24 +00:00
out:
Next phase in the PCI subsystem cleanup. - Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
if (vp != NULL)
free(vp, M_DEVBUF);
if (dp != NULL)
free(dp, M_DEVBUF);
return(desc);
Implement the BUS_PROBE_NOMATCH method for the PCI bus. This function is called for each device for which no driver was found. Output is similar to the eisa_probe_nomatch() function but with the added benefit of displaying the assigned IRQ (since PCI gives us this information up front.) Output is like so: pci0: unknown card CPQ0508 (vendor=0x0e11, dev=0x0508) at 11.0 irq 9 pci0: unknown card DFZ0508 (vendor=0x10da, dev=0x0508) at 11.0 irq 9 pci0: unknown card DBL0508 (vendor=0x104c, dev=0x0508) at 11.0 irq 9 pci0: unknown card DDM0011 (vendor=0x108d, dev=0x0011) at 11.0 irq 9 I'm not happy with the 3 lines of macro cruft that got added but I consider it a temporary annoyance as those bits will be moved to some place where PCI, EISA and ISAPNP code will be able to use them. (Not surprisingly, this message is longer than the code in question.) Reviewed by: peter, dfr
1999-07-27 04:28:14 +00:00
}
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
int
Fixed the type of some ivar access functions. Ivars have type uintptr_t, not u_long. On i386's with 64-bit longs, returning u_longs indirectly in (more than) the space reserved for uintptr_t's tended to corrupt the previous frame pointer in the stack frame, so it was not easy to debug. The type mismatches are hidden by the bogus cast in DEVMETHOD().
2000-04-30 10:01:56 +00:00
pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
{
struct pci_devinfo *dinfo;
pcicfgregs *cfg;
dinfo = device_get_ivars(child);
cfg = &dinfo->cfg;
switch (which) {
Add a new cardbus specific ivar: PCI_IVAR_ETHADDR. Some pci-like buses support querying the MAC address in a standard-for-that-bus way. The base pci bus returns NULL for this IVAR always. Submitted by: sam Approved by: re (blanket for NEWCARD)
2002-11-27 06:41:28 +00:00
case PCI_IVAR_ETHADDR:
/*
* The generic accessor doesn't deal with failure, so
* we set the return value, then return an error.
*/
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
*((uint8_t **) result) = NULL;
Add a new cardbus specific ivar: PCI_IVAR_ETHADDR. Some pci-like buses support querying the MAC address in a standard-for-that-bus way. The base pci bus returns NULL for this IVAR always. Submitted by: sam Approved by: re (blanket for NEWCARD)
2002-11-27 06:41:28 +00:00
return (EINVAL);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
case PCI_IVAR_SUBVENDOR:
*result = cfg->subvendor;
break;
case PCI_IVAR_SUBDEVICE:
*result = cfg->subdevice;
break;
case PCI_IVAR_VENDOR:
*result = cfg->vendor;
break;
case PCI_IVAR_DEVICE:
*result = cfg->device;
break;
case PCI_IVAR_DEVID:
*result = (cfg->device << 16) | cfg->vendor;
break;
case PCI_IVAR_CLASS:
*result = cfg->baseclass;
break;
case PCI_IVAR_SUBCLASS:
*result = cfg->subclass;
break;
case PCI_IVAR_PROGIF:
*result = cfg->progif;
break;
case PCI_IVAR_REVID:
*result = cfg->revid;
break;
case PCI_IVAR_INTPIN:
*result = cfg->intpin;
break;
case PCI_IVAR_IRQ:
*result = cfg->intline;
break;
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
case PCI_IVAR_DOMAIN:
*result = cfg->domain;
break;
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
case PCI_IVAR_BUS:
*result = cfg->bus;
break;
case PCI_IVAR_SLOT:
*result = cfg->slot;
break;
case PCI_IVAR_FUNCTION:
*result = cfg->func;
break;
Allow one to access the cached values for CMDREG, CACHELNSZ, MINGNT, MAXLAT and LATTIMER. Improve error message when a bogus RID type is requested for a bar.
2005-09-11 03:22:03 +00:00
case PCI_IVAR_CMDREG:
*result = cfg->cmdreg;
break;
case PCI_IVAR_CACHELNSZ:
*result = cfg->cachelnsz;
break;
case PCI_IVAR_MINGNT:
The minimim grant and maximum latency PCI config registers are only valid for type 0 devices, not type 1 or 2 bridges. Don't read them for bridge devices during bus scans and return an error when attempting to read them as ivars for bridge devices.
2015-04-22 21:41:59 +00:00
if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
*result = -1;
return (EINVAL);
}
Allow one to access the cached values for CMDREG, CACHELNSZ, MINGNT, MAXLAT and LATTIMER. Improve error message when a bogus RID type is requested for a bar.
2005-09-11 03:22:03 +00:00
*result = cfg->mingnt;
break;
case PCI_IVAR_MAXLAT:
The minimim grant and maximum latency PCI config registers are only valid for type 0 devices, not type 1 or 2 bridges. Don't read them for bridge devices during bus scans and return an error when attempting to read them as ivars for bridge devices.
2015-04-22 21:41:59 +00:00
if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
*result = -1;
return (EINVAL);
}
Allow one to access the cached values for CMDREG, CACHELNSZ, MINGNT, MAXLAT and LATTIMER. Improve error message when a bogus RID type is requested for a bar.
2005-09-11 03:22:03 +00:00
*result = cfg->maxlat;
break;
case PCI_IVAR_LATTIMER:
*result = cfg->lattimer;
break;
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
default:
More style(9) nits
2002-06-01 05:44:45 +00:00
return (ENOENT);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
More style(9) nits
2002-06-01 05:44:45 +00:00
return (0);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
int
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
{
struct pci_devinfo *dinfo;
dinfo = device_get_ivars(child);
switch (which) {
Allow to write the intpin ivar using the pci_set_intpin() accessor. There are some Sun PCI devices around which bogusly set intpin to 0, although they use the intline mechanism; this allows the device driver to correct that. Reviewed by: imp
2003-07-01 13:54:10 +00:00
case PCI_IVAR_INTPIN:
dinfo->cfg.intpin = value;
return (0);
Add a new cardbus specific ivar: PCI_IVAR_ETHADDR. Some pci-like buses support querying the MAC address in a standard-for-that-bus way. The base pci bus returns NULL for this IVAR always. Submitted by: sam Approved by: re (blanket for NEWCARD)
2002-11-27 06:41:28 +00:00
case PCI_IVAR_ETHADDR:
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
case PCI_IVAR_SUBVENDOR:
case PCI_IVAR_SUBDEVICE:
case PCI_IVAR_VENDOR:
case PCI_IVAR_DEVICE:
case PCI_IVAR_DEVID:
case PCI_IVAR_CLASS:
case PCI_IVAR_SUBCLASS:
case PCI_IVAR_PROGIF:
case PCI_IVAR_REVID:
case PCI_IVAR_IRQ:
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
case PCI_IVAR_DOMAIN:
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
case PCI_IVAR_BUS:
case PCI_IVAR_SLOT:
case PCI_IVAR_FUNCTION:
More style(9) nits
2002-06-01 05:44:45 +00:00
return (EINVAL); /* disallow for now */
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
default:
More style(9) nits
2002-06-01 05:44:45 +00:00
return (ENOENT);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
}
Add a new command: show pciregs, equivalent to pciconf -l Reviewed by: Doug Rabson (quite some time ago) MFC after: 1 week
2002-08-28 10:02:59 +00:00
#include "opt_ddb.h"
#ifdef DDB
#include <ddb/ddb.h>
#include <sys/cons.h>
/*
* List resources based on pci map registers, used for within ddb
*/
DB_SHOW_COMMAND(pciregs, db_pci_dump)
{
struct pci_devinfo *dinfo;
struct devlist *devlist_head;
struct pci_conf *p;
const char *name;
Simplify the pager support in DDB. Allowing different db commands to install custom pager functions didn't actually happen in practice (they all just used the simple pager and passed in a local quit pointer). So, just hardcode the simple pager as the only pager and make it set a global db_pager_quit flag that db commands can check when the user hits 'q' (or a suitable variant) at the pager prompt. Also, now that it's easy to do so, enable paging by default for all ddb commands. Any command that wishes to honor the quit flag can do so by checking db_pager_quit. Note that the pager can also be effectively disabled by setting $lines to 0. Other fixes: - 'show idt' on i386 and pc98 now actually checks the quit flag and terminates early. - 'show intr' now actually checks the quit flag and terminates early.
2006-07-12 21:22:44 +00:00
int i, error, none_count;
Add a new command: show pciregs, equivalent to pciconf -l Reviewed by: Doug Rabson (quite some time ago) MFC after: 1 week
2002-08-28 10:02:59 +00:00
none_count = 0;
/* get the head of the device queue */
devlist_head = &pci_devq;
/*
* Go through the list of devices and print out devices
*/
Simplify the pager support in DDB. Allowing different db commands to install custom pager functions didn't actually happen in practice (they all just used the simple pager and passed in a local quit pointer). So, just hardcode the simple pager as the only pager and make it set a global db_pager_quit flag that db commands can check when the user hits 'q' (or a suitable variant) at the pager prompt. Also, now that it's easy to do so, enable paging by default for all ddb commands. Any command that wishes to honor the quit flag can do so by checking db_pager_quit. Note that the pager can also be effectively disabled by setting $lines to 0. Other fixes: - 'show idt' on i386 and pc98 now actually checks the quit flag and terminates early. - 'show intr' now actually checks the quit flag and terminates early.
2006-07-12 21:22:44 +00:00
for (error = 0, i = 0,
Add a new command: show pciregs, equivalent to pciconf -l Reviewed by: Doug Rabson (quite some time ago) MFC after: 1 week
2002-08-28 10:02:59 +00:00
dinfo = STAILQ_FIRST(devlist_head);
Simplify the pager support in DDB. Allowing different db commands to install custom pager functions didn't actually happen in practice (they all just used the simple pager and passed in a local quit pointer). So, just hardcode the simple pager as the only pager and make it set a global db_pager_quit flag that db commands can check when the user hits 'q' (or a suitable variant) at the pager prompt. Also, now that it's easy to do so, enable paging by default for all ddb commands. Any command that wishes to honor the quit flag can do so by checking db_pager_quit. Note that the pager can also be effectively disabled by setting $lines to 0. Other fixes: - 'show idt' on i386 and pc98 now actually checks the quit flag and terminates early. - 'show intr' now actually checks the quit flag and terminates early.
2006-07-12 21:22:44 +00:00
(dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
Add a new command: show pciregs, equivalent to pciconf -l Reviewed by: Doug Rabson (quite some time ago) MFC after: 1 week
2002-08-28 10:02:59 +00:00
dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
/* Populate pd_name and pd_unit */
name = NULL;
if (dinfo->cfg.dev)
name = device_get_name(dinfo->cfg.dev);
p = &dinfo->conf;
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
Add a new command: show pciregs, equivalent to pciconf -l Reviewed by: Doug Rabson (quite some time ago) MFC after: 1 week
2002-08-28 10:02:59 +00:00
"chip=0x%08x rev=0x%02x hdr=0x%02x\n",
(name && *name) ? name : "none",
(name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
none_count++,
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
Add a new command: show pciregs, equivalent to pciconf -l Reviewed by: Doug Rabson (quite some time ago) MFC after: 1 week
2002-08-28 10:02:59 +00:00
p->pc_sel.pc_func, (p->pc_class << 16) |
(p->pc_subclass << 8) | p->pc_progif,
(p->pc_subdevice << 16) | p->pc_subvendor,
(p->pc_device << 16) | p->pc_vendor,
p->pc_revid, p->pc_hdr);
}
}
#endif /* DDB */
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
static struct resource *
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
pci_reserve_map(device_t dev, device_t child, int type, int *rid,
Convert rman to use rman_res_t instead of u_long Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075
2016-01-27 02:23:54 +00:00
rman_res_t start, rman_res_t end, rman_res_t count, u_int num,
u_int flags)
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
{
struct pci_devinfo *dinfo = device_get_ivars(child);
struct resource_list *rl = &dinfo->resources;
struct resource *res;
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
struct pci_map *pm;
pci: Clear the MEM/PORT_EN bit when updating PCI BAR It's unsafe to update the BAR when the related EN bit is set. Submitted by: Dexuan Cui <decui microsoft com> Reviewed by: jhb MFC after: 1 week Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D7914
2016-09-27 06:00:10 +00:00
uint16_t cmd;
More fully support 64-bit bars. Prior to this commit, we supported only those bars that had addresses assigned by the BIOS and where the bridges were properly programmed. Now even unprogrammed ones work. This was needed for sun4v. We still only implement up to 2GB memory ranges, even for 64-bit bars. PCI standards at least through 2.2 say that this is the max (or 1GB is, I only know it is < 32bits). o Always define pci_addr_t as uint64_t. A pci address is always 64-bits, but some hosts can't address all of them. o Preserve the upper half of the 64-bit word during resource probing. o Test to make sure that 64-bit values can fit in a u_long (true on some platforms, but not others). Don't use those that can't. o minor pedantry about data sizes. o Better bridge resource reporting in bootverbose case. o Minor formatting changes to cope with different data types on different platforms. Submitted by: jmg, with many changes by me to fully support 64-bit addresses.
2006-10-30 19:18:46 +00:00
pci_addr_t map, testval;
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
int mapsize;
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
Some devices have what appear to be invalid BARs. They are invalid in the sense that any write to them reads back as a 0. This presents a problem to our resource allocation scheme. If we encounter such vars, the code now treats them as special, allowing any allocation against them to succeed. I've not seen anything in the standard to clearify what host software should do when it encounters these sorts of BARs. Also cleaned up some output while I'm here and add commmented out bootverbose lines until I'm ready to reduce the verbosity of boot messages. This gets a number of south bridges and ata controllers made mostly by VIA, AMD and nVidia working again. Thanks to Soren Schmidt for his help in coming up with this patch.
2004-04-13 19:31:57 +00:00
res = NULL;
Support for Enhanced Allocation in PCI On some platforms, BAR entries are hardcoded and must not be accessed using standard method. Add functionality to identify this situation and configure the bus based on Enhanced Allocation structure. Obtained from: Semihalf Sponsored by: Cavium Approved by: cognet (mentor) Reviewed by: jhb Differential revision: https://reviews.freebsd.org/D5242
2016-03-02 09:54:58 +00:00
/* If rid is managed by EA, ignore it */
if (pci_ea_is_enabled(child, *rid))
goto out;
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
pm = pci_find_bar(child, *rid);
if (pm != NULL) {
/* This is a BAR that we failed to allocate earlier. */
mapsize = pm->pm_size;
map = pm->pm_value;
} else {
/*
* Weed out the bogons, and figure out how large the
* BAR/map is. BARs that read back 0 here are bogus
* and unimplemented. Note: atapci in legacy mode are
* special and handled elsewhere in the code. If you
* have a atapci device in legacy mode and it fails
* here, that other code is broken.
*/
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
pci_read_bar(child, *rid, &map, &testval, NULL);
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
/*
* Determine the size of the BAR and ignore BARs with a size
* of 0. Device ROM BARs use a different mask value.
*/
if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
mapsize = pci_romsize(testval);
else
mapsize = pci_mapsize(testval);
if (mapsize == 0)
goto out;
pm = pci_add_bar(child, *rid, map, mapsize);
}
In pci_alloc_map(), restore the original value of the BAR for the duration of the function. The device we would otherwise have left in an useless state may just as well be the low-level console. When booting verbose, we do need it addressable if we want to avoid a MCA. Approved by: re (kensmith)
2007-07-29 02:44:41 +00:00
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
if (type != SYS_RES_MEMORY) {
It isn't a whinable offence to want memory when the bar says ioport. Put that behind bootverbose to make the ata driver less chatty on advanced hardware. Requested by: sos
2005-04-11 02:08:05 +00:00
if (bootverbose)
Allow one to access the cached values for CMDREG, CACHELNSZ, MINGNT, MAXLAT and LATTIMER. Improve error message when a bogus RID type is requested for a bar.
2005-09-11 03:22:03 +00:00
device_printf(dev,
"child %s requested type %d for rid %#x,"
" but the BAR says it is an memio\n",
device_get_nameunit(child), type, *rid);
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
goto out;
Some devices have what appear to be invalid BARs. They are invalid in the sense that any write to them reads back as a 0. This presents a problem to our resource allocation scheme. If we encounter such vars, the code now treats them as special, allowing any allocation against them to succeed. I've not seen anything in the standard to clearify what host software should do when it encounters these sorts of BARs. Also cleaned up some output while I'm here and add commmented out bootverbose lines until I'm ready to reduce the verbosity of boot messages. This gets a number of south bridges and ata controllers made mostly by VIA, AMD and nVidia working again. Thanks to Soren Schmidt for his help in coming up with this patch.
2004-04-13 19:31:57 +00:00
}
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
} else {
if (type != SYS_RES_IOPORT) {
It isn't a whinable offence to want memory when the bar says ioport. Put that behind bootverbose to make the ata driver less chatty on advanced hardware. Requested by: sos
2005-04-11 02:08:05 +00:00
if (bootverbose)
Allow one to access the cached values for CMDREG, CACHELNSZ, MINGNT, MAXLAT and LATTIMER. Improve error message when a bogus RID type is requested for a bar.
2005-09-11 03:22:03 +00:00
device_printf(dev,
"child %s requested type %d for rid %#x,"
" but the BAR says it is an ioport\n",
device_get_nameunit(child), type, *rid);
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
goto out;
}
Some devices have what appear to be invalid BARs. They are invalid in the sense that any write to them reads back as a 0. This presents a problem to our resource allocation scheme. If we encounter such vars, the code now treats them as special, allowing any allocation against them to succeed. I've not seen anything in the standard to clearify what host software should do when it encounters these sorts of BARs. Also cleaned up some output while I'm here and add commmented out bootverbose lines until I'm ready to reduce the verbosity of boot messages. This gets a number of south bridges and ata controllers made mostly by VIA, AMD and nVidia working again. Thanks to Soren Schmidt for his help in coming up with this patch.
2004-04-13 19:31:57 +00:00
}
- Consolidate duplicated code for reading and sizing BARs and writing base addresses to BARs into new pci_read_bar() and pci_write_bar() routines. pci_add_map(), pci_alloc_map(), and pci_delete_resource() now use these routines to work with BARs. - Just pass the device_t for the new PCI device to various routines instead of passing the device, bus, slot, and function. Reviewed by: imp
2009-04-14 18:32:37 +00:00
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
/*
* For real BARs, we need to override the size that
* the driver requests, because that's what the BAR
* actually uses and we would otherwise have a
* situation where we might allocate the excess to
* another driver, which won't work.
*/
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
count = ((pci_addr_t)1 << mapsize) * num;
ata devices in legacy are special, and we must treat them as such. While I would have prefered to have a solution that didn't move knowledge of this into the pci layer. However, this is literally the only exception that's listed in the PCI standard to the usual way of decoding BARs. atapci devices in legacy mode now ignore the first 4 bars and hard code the values to the legacy ide values (well, for each of the controllers that are in legacy mode). The 5th bar is handled normally. Remove the zero bar handling. zero bars should be ignored at all other times, and since we handle that specially, we don't need the older workaround.
2004-04-21 20:19:56 +00:00
if (RF_ALIGNMENT(flags) < mapsize)
flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
Honor the prefetchable flag in memory BARs by setting the RF_PREFETCHABLE flag when calling bus_alloc_resource() to allocate resources from a parent PCI bridge. For PCI-PCI bridges this asks the bridge to satisfy the request using the prefetchable memory range rather than the normal memory range. Reviewed by: imp Reported by: scottl MFC after: 1 week
2009-03-05 15:28:46 +00:00
flags |= RF_PREFETCHABLE;
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
/*
* Allocate enough resource, and then write back the
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
* appropriate BAR for that resource.
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
*/
Simplify pci_reserve_map() by calling resource_list_reserve() to allocate the resource after creating a resource list entry rather than reimplementing it by hand. MFC after: 1 week
2014-02-05 20:47:49 +00:00
resource_list_add(rl, type, *rid, start, end, count);
res = resource_list_reserve(rl, dev, child, type, rid, start, end,
count, flags & ~RF_ACTIVE);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
if (res == NULL) {
Simplify pci_reserve_map() by calling resource_list_reserve() to allocate the resource after creating a resource list entry rather than reimplementing it by hand. MFC after: 1 week
2014-02-05 20:47:49 +00:00
resource_list_delete(rl, type, *rid);
Improve diagnostic message.
2005-11-09 03:37:52 +00:00
device_printf(child,
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
"%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n",
Improve diagnostic message.
2005-11-09 03:37:52 +00:00
count, *rid, type, start, end);
Some devices have what appear to be invalid BARs. They are invalid in the sense that any write to them reads back as a 0. This presents a problem to our resource allocation scheme. If we encounter such vars, the code now treats them as special, allowing any allocation against them to succeed. I've not seen anything in the standard to clearify what host software should do when it encounters these sorts of BARs. Also cleaned up some output while I'm here and add commmented out bootverbose lines until I'm ready to reduce the verbosity of boot messages. This gets a number of south bridges and ata controllers made mostly by VIA, AMD and nVidia working again. Thanks to Soren Schmidt for his help in coming up with this patch.
2004-04-13 19:31:57 +00:00
goto out;
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
}
make the pci power state and resource code a lot less chatty. The chattiness was left in for debugging, but now that nearly all of the problems relating to the changes have been fixed, it is only annoying. It is still available via bootverbose. Prodded by: jhb
2004-05-21 06:03:26 +00:00
if (bootverbose)
device_printf(child,
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
"Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n",
make the pci power state and resource code a lot less chatty. The chattiness was left in for debugging, but now that nearly all of the problems relating to the changes have been fixed, it is only annoying. It is still available via bootverbose. Prodded by: jhb
2004-05-21 06:03:26 +00:00
count, *rid, type, rman_get_start(res));
pci: Clear the MEM/PORT_EN bit when updating PCI BAR It's unsafe to update the BAR when the related EN bit is set. Submitted by: Dexuan Cui <decui microsoft com> Reviewed by: jhb MFC after: 1 week Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D7914
2016-09-27 06:00:10 +00:00
/* Disable decoding via the CMD register before updating the BAR */
cmd = pci_read_config(child, PCIR_COMMAND, 2);
pci_write_config(child, PCIR_COMMAND,
cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
Some devices have what appear to be invalid BARs. They are invalid in the sense that any write to them reads back as a 0. This presents a problem to our resource allocation scheme. If we encounter such vars, the code now treats them as special, allowing any allocation against them to succeed. I've not seen anything in the standard to clearify what host software should do when it encounters these sorts of BARs. Also cleaned up some output while I'm here and add commmented out bootverbose lines until I'm ready to reduce the verbosity of boot messages. This gets a number of south bridges and ata controllers made mostly by VIA, AMD and nVidia working again. Thanks to Soren Schmidt for his help in coming up with this patch.
2004-04-13 19:31:57 +00:00
map = rman_get_start(res);
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
pci_write_bar(child, pm, map);
pci: Clear the MEM/PORT_EN bit when updating PCI BAR It's unsafe to update the BAR when the related EN bit is set. Submitted by: Dexuan Cui <decui microsoft com> Reviewed by: jhb MFC after: 1 week Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D7914
2016-09-27 06:00:10 +00:00
/* Restore the original value of the CMD register */
pci_write_config(child, PCIR_COMMAND, cmd, 2);
Fix couple of style nits.
2012-03-29 19:29:24 +00:00
out:
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
return (res);
}
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
struct resource *
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid,
Convert rman to use rman_res_t instead of u_long Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075
2016-01-27 02:23:54 +00:00
rman_res_t start, rman_res_t end, rman_res_t count, u_long num,
u_int flags)
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
{
Properly handle I/O windows in bridges with the ISA enable bit set. These beasts still exist unfortunately. More details can be found in other references, but the short version is that bridges with this bit set ignore I/O port ranges that alias to valid ISA I/O port ranges. In the driver this requires not allocating these alias regions from the parent device (so they are free to be acquired by ISA devices), and ensuring no child devices use resources from these alias regions. - Change the pcib_window structure to allow for an array of backing resources rather than a single resource and update the existing code to cope with this. Some of the coping requires using the saved base and limit values in pcib_window instead of using rman operations on the backing resource. - Add special handling for allocating and adjusting the I/O port window of an ISA-enabled bridge to only allocate the non-alias ranges and add those to the associated resource manager. - Reject I/O port allocations for a fixed request that conflicts with an ISA alias range. - Remove the "no prefected decode" verbose printf during boot. The absence of a "prefetched decode" line is sufficient. - Replace the "subtractively decoded bridge" verbose printf with a single printf that lists all the "special" decoding modes of a bridge: ISA, subtractive, and VGA. - Add a custom bus_release_resource() method to the PCI bus driver so that it can properly free resources for I/O windows of PCI-PCI bridges. (These resources are not stored in the bridge device's resource list.) PR: misc/179033 MFC after: 2 weeks
2013-07-18 15:17:11 +00:00
struct pci_devinfo *dinfo;
struct resource_list *rl;
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
struct resource_list_entry *rle;
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
struct resource *res;
Properly handle I/O windows in bridges with the ISA enable bit set. These beasts still exist unfortunately. More details can be found in other references, but the short version is that bridges with this bit set ignore I/O port ranges that alias to valid ISA I/O port ranges. In the driver this requires not allocating these alias regions from the parent device (so they are free to be acquired by ISA devices), and ensuring no child devices use resources from these alias regions. - Change the pcib_window structure to allow for an array of backing resources rather than a single resource and update the existing code to cope with this. Some of the coping requires using the saved base and limit values in pcib_window instead of using rman operations on the backing resource. - Add special handling for allocating and adjusting the I/O port window of an ISA-enabled bridge to only allocate the non-alias ranges and add those to the associated resource manager. - Reject I/O port allocations for a fixed request that conflicts with an ISA alias range. - Remove the "no prefected decode" verbose printf during boot. The absence of a "prefetched decode" line is sufficient. - Replace the "subtractively decoded bridge" verbose printf with a single printf that lists all the "special" decoding modes of a bridge: ISA, subtractive, and VGA. - Add a custom bus_release_resource() method to the PCI bus driver so that it can properly free resources for I/O windows of PCI-PCI bridges. (These resources are not stored in the bridge device's resource list.) PR: misc/179033 MFC after: 2 weeks
2013-07-18 15:17:11 +00:00
pcicfgregs *cfg;
When a pci device hasn't had an interrupt routed to it (signified by the intline of 255) go ahead and route the interrupt when we allocate an interrupt. Submitted by: msmith
2000-10-16 07:24:00 +00:00
/*
* Perform lazy resource allocation
*/
Properly handle I/O windows in bridges with the ISA enable bit set. These beasts still exist unfortunately. More details can be found in other references, but the short version is that bridges with this bit set ignore I/O port ranges that alias to valid ISA I/O port ranges. In the driver this requires not allocating these alias regions from the parent device (so they are free to be acquired by ISA devices), and ensuring no child devices use resources from these alias regions. - Change the pcib_window structure to allow for an array of backing resources rather than a single resource and update the existing code to cope with this. Some of the coping requires using the saved base and limit values in pcib_window instead of using rman operations on the backing resource. - Add special handling for allocating and adjusting the I/O port window of an ISA-enabled bridge to only allocate the non-alias ranges and add those to the associated resource manager. - Reject I/O port allocations for a fixed request that conflicts with an ISA alias range. - Remove the "no prefected decode" verbose printf during boot. The absence of a "prefetched decode" line is sufficient. - Replace the "subtractively decoded bridge" verbose printf with a single printf that lists all the "special" decoding modes of a bridge: ISA, subtractive, and VGA. - Add a custom bus_release_resource() method to the PCI bus driver so that it can properly free resources for I/O windows of PCI-PCI bridges. (These resources are not stored in the bridge device's resource list.) PR: misc/179033 MFC after: 2 weeks
2013-07-18 15:17:11 +00:00
dinfo = device_get_ivars(child);
rl = &dinfo->resources;
cfg = &dinfo->cfg;
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
switch (type) {
Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
2014-02-12 04:30:37 +00:00
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
case PCI_RES_BUS:
return (pci_alloc_secbus(dev, child, rid, start, end, count,
flags));
#endif
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
case SYS_RES_IRQ:
/*
* Can't alloc legacy interrupt once MSI messages have
* been allocated.
*/
if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
cfg->msix.msix_alloc > 0))
return (NULL);
/*
* If the child device doesn't have an interrupt
* routed and is deserving of an interrupt, try to
* assign it one.
*/
if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
(cfg->intpin != 0))
pci_assign_interrupt(dev, child, 0);
break;
case SYS_RES_IOPORT:
case SYS_RES_MEMORY:
Reimplement how PCI-PCI bridges manage their I/O windows. Previously the driver would verify that requests for child devices were confined to any existing I/O windows, but the driver relied on the firmware to initialize the windows and would never grow the windows for new requests. Now the driver actively manages the I/O windows. This is implemented by allocating a bus resource for each I/O window from the parent PCI bus and suballocating that resource to child devices. The suballocations are managed by creating an rman for each I/O window. The suballocated resources are mapped by passing the bus_activate_resource() call up to the parent PCI bus. Windows are grown when needed by using bus_adjust_resource() to adjust the resource allocated from the parent PCI bus. If the adjust request succeeds, the window is adjusted and the suballocation request for the child device is retried. When growing a window, the rman_first_free_region() and rman_last_free_region() routines are used to determine if the front or end of the existing I/O window is free. From using that, the smallest ranges that need to be added to either the front or back of the window are computed. The driver will first try to grow the window in whichever direction requires the smallest growth first followed by the other direction if that fails. Subtractive bridges will first attempt to satisfy requests for child resources from I/O windows (including attempts to grow the windows). If that fails, the request is passed up to the parent PCI bus directly however. The PCI-PCI bridge driver will try to use firmware-assigned ranges for child BARs first and only allocate a "fresh" range if that specific range cannot be accommodated in the I/O window. This allows systems where the firmware assigns resources during boot but later wipes the I/O windows (some ACPI BIOSen are known to do this) to "rediscover" the original I/O window ranges. The ACPI Host-PCI bridge driver has been adjusted to correctly honor hw.acpi.host_mem_start and the I/O port equivalent when a PCI-PCI bridge makes a wildcard request for an I/O window range. The new PCI-PCI bridge driver is only enabled if the NEW_PCIB kernel option is enabled. This is a transition aide to allow platforms that do not yet support bus_activate_resource() and bus_adjust_resource() in their Host-PCI bridge drivers (and possibly other drivers as needed) to use the old driver for now. Once all platforms support the new driver, the kernel option and old driver will be removed. PR: kern/143874 kern/149306 Tested by: mav
2011-05-03 17:37:24 +00:00
#ifdef NEW_PCIB
/*
* PCI-PCI bridge I/O window resources are not BARs.
* For those allocations just pass the request up the
* tree.
*/
if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
switch (*rid) {
case PCIR_IOBASEL_1:
case PCIR_MEMBASE_1:
case PCIR_PMBASEL_1:
/*
* XXX: Should we bother creating a resource
* list entry?
*/
return (bus_generic_alloc_resource(dev, child,
type, rid, start, end, count, flags));
}
}
#endif
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
/* Reserve resources for this BAR if needed. */
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
rle = resource_list_find(rl, type, *rid);
if (rle == NULL) {
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
res = pci_reserve_map(dev, child, type, rid, start, end,
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
count, num, flags);
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
if (res == NULL)
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
return (NULL);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
}
When a pci device hasn't had an interrupt routed to it (signified by the intline of 255) go ahead and route the interrupt when we allocate an interrupt. Submitted by: msmith
2000-10-16 07:24:00 +00:00
}
More style(9) nits
2002-06-01 05:44:45 +00:00
return (resource_list_alloc(rl, dev, child, type, rid,
start, end, count, flags));
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
struct resource *
pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
Convert rman to use rman_res_t instead of u_long Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075
2016-01-27 02:23:54 +00:00
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
{
Allocate PCI I/O memory spaces for VFs When creating VFs, we must size each SR-IOV BAR on the PF and allocate a configuous I/O memory window large enough for every VF. However, the window only needs to be aligned to a boundary equal to the size of the window for a single VF. When a VF attempts to allocate an I/O memory resource, we must intercept the request in the pci driver and pass it off to the SR-IOV code, which will allocate the correct window from the pre-allocated memory space for the PF. Inform the pci driver about the size and address of the BARs on the VF when the VF is created. This is required by pciconf -b and bhyve. Differential Revision: https://reviews.freebsd.org/D78 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:26 +00:00
#ifdef PCI_IOV
struct pci_devinfo *dinfo;
#endif
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
if (device_get_parent(child) != dev)
return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
type, rid, start, end, count, flags));
Allocate PCI I/O memory spaces for VFs When creating VFs, we must size each SR-IOV BAR on the PF and allocate a configuous I/O memory window large enough for every VF. However, the window only needs to be aligned to a boundary equal to the size of the window for a single VF. When a VF attempts to allocate an I/O memory resource, we must intercept the request in the pci driver and pass it off to the SR-IOV code, which will allocate the correct window from the pre-allocated memory space for the PF. Inform the pci driver about the size and address of the BARs on the VF when the VF is created. This is required by pciconf -b and bhyve. Differential Revision: https://reviews.freebsd.org/D78 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:26 +00:00
#ifdef PCI_IOV
dinfo = device_get_ivars(child);
if (dinfo->cfg.flags & PCICFG_VF) {
switch (type) {
/* VFs can't have I/O BARs. */
case SYS_RES_IOPORT:
return (NULL);
case SYS_RES_MEMORY:
return (pci_vf_alloc_mem_resource(dev, child, rid,
start, end, count, flags));
}
/* Fall through for other types of resource allocations. */
}
#endif
Refactor PCI resource allocation Refactor PCI resource allocation code to allow a request for a memory-mapped I/O window that is a multiple of a requested size. This is needed by the SR-IOV code because the VF BARs are all allocated contiguously. We can't just allocate a resource that is a multiple of a single VF BAR because the size of an allocation implies its alignment requirement. Differential Revision: https://reviews.freebsd.org/D71 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:39:33 +00:00
return (pci_alloc_multi_resource(dev, child, type, rid, start, end,
count, 1, flags));
}
Properly handle I/O windows in bridges with the ISA enable bit set. These beasts still exist unfortunately. More details can be found in other references, but the short version is that bridges with this bit set ignore I/O port ranges that alias to valid ISA I/O port ranges. In the driver this requires not allocating these alias regions from the parent device (so they are free to be acquired by ISA devices), and ensuring no child devices use resources from these alias regions. - Change the pcib_window structure to allow for an array of backing resources rather than a single resource and update the existing code to cope with this. Some of the coping requires using the saved base and limit values in pcib_window instead of using rman operations on the backing resource. - Add special handling for allocating and adjusting the I/O port window of an ISA-enabled bridge to only allocate the non-alias ranges and add those to the associated resource manager. - Reject I/O port allocations for a fixed request that conflicts with an ISA alias range. - Remove the "no prefected decode" verbose printf during boot. The absence of a "prefetched decode" line is sufficient. - Replace the "subtractively decoded bridge" verbose printf with a single printf that lists all the "special" decoding modes of a bridge: ISA, subtractive, and VGA. - Add a custom bus_release_resource() method to the PCI bus driver so that it can properly free resources for I/O windows of PCI-PCI bridges. (These resources are not stored in the bridge device's resource list.) PR: misc/179033 MFC after: 2 weeks
2013-07-18 15:17:11 +00:00
int
pci_release_resource(device_t dev, device_t child, int type, int rid,
struct resource *r)
{
struct pci_devinfo *dinfo;
struct resource_list *rl;
pcicfgregs *cfg;
if (device_get_parent(child) != dev)
return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
type, rid, r));
dinfo = device_get_ivars(child);
cfg = &dinfo->cfg;
Allocate PCI I/O memory spaces for VFs When creating VFs, we must size each SR-IOV BAR on the PF and allocate a configuous I/O memory window large enough for every VF. However, the window only needs to be aligned to a boundary equal to the size of the window for a single VF. When a VF attempts to allocate an I/O memory resource, we must intercept the request in the pci driver and pass it off to the SR-IOV code, which will allocate the correct window from the pre-allocated memory space for the PF. Inform the pci driver about the size and address of the BARs on the VF when the VF is created. This is required by pciconf -b and bhyve. Differential Revision: https://reviews.freebsd.org/D78 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:26 +00:00
#ifdef PCI_IOV
if (dinfo->cfg.flags & PCICFG_VF) {
switch (type) {
/* VFs can't have I/O BARs. */
case SYS_RES_IOPORT:
return (EDOOFUS);
case SYS_RES_MEMORY:
return (pci_vf_release_mem_resource(dev, child, rid,
r));
}
/* Fall through for other types of resource allocations. */
}
#endif
Properly handle I/O windows in bridges with the ISA enable bit set. These beasts still exist unfortunately. More details can be found in other references, but the short version is that bridges with this bit set ignore I/O port ranges that alias to valid ISA I/O port ranges. In the driver this requires not allocating these alias regions from the parent device (so they are free to be acquired by ISA devices), and ensuring no child devices use resources from these alias regions. - Change the pcib_window structure to allow for an array of backing resources rather than a single resource and update the existing code to cope with this. Some of the coping requires using the saved base and limit values in pcib_window instead of using rman operations on the backing resource. - Add special handling for allocating and adjusting the I/O port window of an ISA-enabled bridge to only allocate the non-alias ranges and add those to the associated resource manager. - Reject I/O port allocations for a fixed request that conflicts with an ISA alias range. - Remove the "no prefected decode" verbose printf during boot. The absence of a "prefetched decode" line is sufficient. - Replace the "subtractively decoded bridge" verbose printf with a single printf that lists all the "special" decoding modes of a bridge: ISA, subtractive, and VGA. - Add a custom bus_release_resource() method to the PCI bus driver so that it can properly free resources for I/O windows of PCI-PCI bridges. (These resources are not stored in the bridge device's resource list.) PR: misc/179033 MFC after: 2 weeks
2013-07-18 15:17:11 +00:00
#ifdef NEW_PCIB
/*
* PCI-PCI bridge I/O window resources are not BARs. For
* those allocations just pass the request up the tree.
*/
if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE &&
(type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) {
switch (rid) {
case PCIR_IOBASEL_1:
case PCIR_MEMBASE_1:
case PCIR_PMBASEL_1:
return (bus_generic_release_resource(dev, child, type,
rid, r));
}
}
#endif
rl = &dinfo->resources;
return (resource_list_release(rl, dev, child, type, rid, r));
}
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
int
pci_activate_resource(device_t dev, device_t child, int type, int rid,
struct resource *r)
{
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
struct pci_devinfo *dinfo;
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
int error;
error = bus_generic_activate_resource(dev, child, type, rid, r);
if (error)
return (error);
/* Enable decoding in the command register when activating BARs. */
if (device_get_parent(child) == dev) {
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
/* Device ROMs need their decoding explicitly enabled. */
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
dinfo = device_get_ivars(child);
Only check to see if a memory resource is a PCI ROM BAR when activating and deactivating PCI resources. Previously, if a device had more than 48 MSI interrupts, then activating message 48 (which has a rid == PCIR_BIOS) would incorrectly try to enable the PCI ROM BAR. Tested by: Olivier Cinquin ocinquin uci edu MFC after: 3 days
2012-05-23 13:41:12 +00:00
if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
pci_write_bar(child, pci_find_bar(child, rid),
rman_get_start(r) | PCIM_BIOS_ENABLE);
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
switch (type) {
case SYS_RES_IOPORT:
case SYS_RES_MEMORY:
error = PCI_ENABLE_IO(dev, child, type);
break;
}
}
return (error);
}
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
int
pci_deactivate_resource(device_t dev, device_t child, int type,
int rid, struct resource *r)
{
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
struct pci_devinfo *dinfo;
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
int error;
error = bus_generic_deactivate_resource(dev, child, type, rid, r);
if (error)
return (error);
drop a bunch of white space at end of lines and end of files... -x -wb apparently doesn't hide end of file white space changes.. This is to reduce the amount of diff for my PCIe HP changes..
2015-10-18 08:13:51 +00:00
/* Disable decoding for device ROMs. */
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
if (device_get_parent(child) == dev) {
dinfo = device_get_ivars(child);
Only check to see if a memory resource is a PCI ROM BAR when activating and deactivating PCI resources. Previously, if a device had more than 48 MSI interrupts, then activating message 48 (which has a rid == PCIR_BIOS) would incorrectly try to enable the PCI ROM BAR. Tested by: Olivier Cinquin ocinquin uci edu MFC after: 3 days
2012-05-23 13:41:12 +00:00
if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
Explicitly track the state of all known BARs for each PCI device. The PCI bus driver will now remember the size of a BAR obtained during the initial bus scan and use that size when doing lazy resource allocation rather than resizing the BAR. The bus driver will now also report unallocated BARs to userland for display by 'pciconf -lb'. Psuedo-resources that are not BARs (such as the implicit I/O port resources for master/slave ATA controllers) will no longer be listed as BARs in 'pciconf -lb'. During resume, BARs are restored from their new saved state instead of having the raw registers saved and restored across resume. This also fixes restoring BARs at unusual loactions if said BAR has been allocated by a driver. Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and properly handle ROM BIOS BARs in PCI-PCI bridges. The PCI bus now also properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge. Tested by: jkim
2011-03-31 13:22:12 +00:00
pci_write_bar(child, pci_find_bar(child, rid),
rman_get_start(r));
}
Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special handling for the PCIR_BIOS decoding enable bit from the cardbus driver. The PCIR_BIOS BAR does include type bits like other BARs. Instead, it is always a 32-bit non-prefetchable memory BAR where the low bit is used as a flag to enable decoding. Reviewed by: imp
2009-12-30 20:47:14 +00:00
return (0);
}
Move the PCI-specific logic of removing a cardbus device into a pci_delete_child() function called by the cardbus driver. The new function uses resource_list_unreserve() to release the BARs decoded by the device being removed. Reviewed by: imp Tested by: brooks
2010-01-05 20:42:25 +00:00
void
Convert pci_delete_child() to a bus_child_deleted() method. Instead of providing a wrapper around device_delete_child() that the PCI bus and child bus drivers must call explicitly, move the bulk of the logic from pci_delete_child() into a bus_child_deleted() method (pci_child_deleted()). This allows PCI devices to be safely deleted via device_delete_child(). - Add a bus_child_deleted method to the ACPI PCI bus which clears the device_t associated with the corresponding ACPI handle in addition to the normal PCI bus cleanup. - Change cardbus_detach_card to call device_delete_children() and move CardBus-specific delete logic into a new cardbus_child_deleted() method. - Use device_delete_child() instead of pci_delete_child() in the SRIOV code. - Add a bus_child_deleted method to the OpenFirmware PCI bus drivers which frees the OpenFirmware device info for each PCI device. Reviewed by: imp Tested on: amd64 (CardBus and PCI-e hotplug) Differential Revision: https://reviews.freebsd.org/D5831
2016-04-06 04:10:22 +00:00
pci_child_deleted(device_t dev, device_t child)
Move the PCI-specific logic of removing a cardbus device into a pci_delete_child() function called by the cardbus driver. The new function uses resource_list_unreserve() to release the BARs decoded by the device being removed. Reviewed by: imp Tested by: brooks
2010-01-05 20:42:25 +00:00
{
struct resource_list_entry *rle;
struct resource_list *rl;
struct pci_devinfo *dinfo;
dinfo = device_get_ivars(child);
rl = &dinfo->resources;
Update the I/O MMU in bhyve when PCI devices are added and removed. When the I/O MMU is active in bhyve, all PCI devices need valid entries in the DMAR context tables. The I/O MMU code does a single enumeration of the available PCI devices during initialization to add all existing devices to a domain representing the host. The ppt(4) driver then moves pass through devices in and out of domains for virtual machines as needed. However, when new PCI devices were added at runtime either via SR-IOV or HotPlug, the I/O MMU tables were not updated. This change adds a new set of EVENTHANDLERS that are invoked when PCI devices are added and deleted. The I/O MMU driver in bhyve installs handlers for these events which it uses to add and remove devices to the "host" domain. Reviewed by: imp Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D7667
2016-09-06 20:17:54 +00:00
EVENTHANDLER_INVOKE(pci_delete_device, child);
Move the PCI-specific logic of removing a cardbus device into a pci_delete_child() function called by the cardbus driver. The new function uses resource_list_unreserve() to release the BARs decoded by the device being removed. Reviewed by: imp Tested by: brooks
2010-01-05 20:42:25 +00:00
/* Turn off access to resources we're about to free */
Convert pci_delete_child() to a bus_child_deleted() method. Instead of providing a wrapper around device_delete_child() that the PCI bus and child bus drivers must call explicitly, move the bulk of the logic from pci_delete_child() into a bus_child_deleted() method (pci_child_deleted()). This allows PCI devices to be safely deleted via device_delete_child(). - Add a bus_child_deleted method to the ACPI PCI bus which clears the device_t associated with the corresponding ACPI handle in addition to the normal PCI bus cleanup. - Change cardbus_detach_card to call device_delete_children() and move CardBus-specific delete logic into a new cardbus_child_deleted() method. - Use device_delete_child() instead of pci_delete_child() in the SRIOV code. - Add a bus_child_deleted method to the OpenFirmware PCI bus drivers which frees the OpenFirmware device info for each PCI device. Reviewed by: imp Tested on: amd64 (CardBus and PCI-e hotplug) Differential Revision: https://reviews.freebsd.org/D5831
2016-04-06 04:10:22 +00:00
if (bus_child_present(child) != 0) {
pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
pci_disable_busmaster(child);
}
Move the PCI-specific logic of removing a cardbus device into a pci_delete_child() function called by the cardbus driver. The new function uses resource_list_unreserve() to release the BARs decoded by the device being removed. Reviewed by: imp Tested by: brooks
2010-01-05 20:42:25 +00:00
/* Free all allocated resources */
STAILQ_FOREACH(rle, rl, link) {
if (rle->res) {
if (rman_get_flags(rle->res) & RF_ACTIVE ||
resource_list_busy(rl, rle->type, rle->rid)) {
pci_printf(&dinfo->cfg,
"Resource still owned, oops. "
"(type=%d, rid=%d, addr=%lx)\n",
rle->type, rle->rid,
rman_get_start(rle->res));
bus_release_resource(child, rle->type, rle->rid,
rle->res);
}
resource_list_unreserve(rl, dev, child, rle->type,
rle->rid);
}
}
resource_list_free(rl);
pci_freecfg(dinfo);
}
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
void
Reduce code duplication by using the GET_RESOURCE_LIST bus method and related generic resource_list management functions. I'll deal with the EISA bits later. Not objected to by: new-bus
2000-11-28 07:12:12 +00:00
pci_delete_resource(device_t dev, device_t child, int type, int rid)
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
{
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
struct pci_devinfo *dinfo;
struct resource_list *rl;
struct resource_list_entry *rle;
if (device_get_parent(child) != dev)
return;
dinfo = device_get_ivars(child);
rl = &dinfo->resources;
rle = resource_list_find(rl, type, rid);
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
if (rle == NULL)
return;
if (rle->res) {
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
if (rman_get_flags(rle->res) & RF_ACTIVE ||
resource_list_busy(rl, type, rid)) {
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
device_printf(dev, "delete_resource: "
"Resource still owned by child, oops. "
Use uintmax_t (typedef'd to rman_res_t type) for rman ranges. On some architectures, u_long isn't large enough for resource definitions. Particularly, powerpc and arm allow 36-bit (or larger) physical addresses, but type `long' is only 32-bit. This extends rman's resources to uintmax_t. With this change, any resource can feasibly be placed anywhere in physical memory (within the constraints of the driver). Why uintmax_t and not something machine dependent, or uint64_t? Though it's possible for uintmax_t to grow, it's highly unlikely it will become 128-bit on 32-bit architectures. 64-bit architectures should have plenty of RAM to absorb the increase on resource sizes if and when this occurs, and the number of resources on memory-constrained systems should be sufficiently small as to not pose a drastic overhead. That being said, uintmax_t was chosen for source clarity. If it's specified as uint64_t, all printf()-like calls would either need casts to uintmax_t, or be littered with PRI*64 macros. Casts to uintmax_t aren't horrible, but it would also bake into the API for resource_list_print_type() either a hidden assumption that entries get cast to uintmax_t for printing, or these calls would need the PRI*64 macros. Since source code is meant to be read more often than written, I chose the clearest path of simply using uintmax_t. Tested on a PowerPC p5020-based board, which places all device resources in 0xfxxxxxxxx, and has 8GB RAM. Regression tested on qemu-system-i386 Regression tested on qemu-system-mips (malta profile) Tested PAE and devinfo on virtualbox (live CD) Special thanks to bz for his testing on ARM. Reviewed By: bz, jhb (previous) Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D4544
2016-03-18 01:28:41 +00:00
"(type=%d, rid=%d, addr=%jx)\n",
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
type, rid, rman_get_start(rle->res));
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
return;
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
}
For some buses, devices may have active resources assigned even though they are not allocated by the device driver. These resources should still appear allocated from the system's perspective so that their assigned ranges are not reused by other resource requests. The PCI bus driver has used a hack to effect this for a while now where it uses rman_set_device() to assign devices to the PCI bus when they are first encountered and later assigns them to the actual device when a driver allocates a BAR. A few downsides of this approach is that it results in somewhat confusing devinfo -r output as well as not being very easily portable to other bus drivers. This commit adds generic support for "reserved" resources to the resource list API used by many bus drivers to manage the resources of child devices. A resource may be reserved via resource_list_reserve(). This will allocate the resource from the bus' parent without activating it. resource_list_alloc() recognizes an attempt to allocate a reserved resource. When this happens it activates the resource (if requested) and then returns the reserved resource. Similarly, when a reserved resource is released via resource_list_release(), it is deactivated (if it is active) and the resource is then marked reserved again, but is left allocated from the bus' parent. To completely remove a reserved resource, a bus driver may use resource_list_unreserve(). A bus driver may use resource_list_busy() to determine if a reserved resource is allocated by a child device or if it can be unreserved. The PCI bus driver has been changed to use this framework instead of abusing rman_set_device() to keep track of reserved vs allocated resources. Submitted by: imp (an older version many moons ago) MFC after: 1 month
2009-12-09 21:52:53 +00:00
resource_list_unreserve(rl, dev, child, type, rid);
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
}
Further refine the handling of resources for BARs in the PCI bus driver. A while back, Warner changed the PCI bus code to reserve resources when enumerating devices and simply give devices the previously allocated resources when they call bus_alloc_resource(). This ensures that address ranges being decoded by a BAR are always allocated in the nexus0 device (or whatever device the PCI bus gets its address space from) even if a device driver is not attached to the device. This patch extends this behavior further: - To let the PCI bus distinguish between a resource being allocated by a device driver vs. merely being allocated by the bus, use rman_set_device() to assign the device to the bus when it is owned by the bus and to the child device when it is allocated by the child device's driver. We can now prevent a device driver from allocating the same device twice. Doing so could result in odd things like allocating duplicate virtual memory to map the resource on some archs and leaking the original mapping. - When a PCI device driver releases a resource, don't pass the request all the way up the tree and release it in the nexus (or similar device) since the BAR is still active and decoding. Otherwise, another device could later allocate the same range even though it is still in use. Instead, deactivate the resource and assign it back to the PCI bus using rman_set_device(). - pci_delete_resource() will actually completely free a BAR including attemping to disable it. - Disable BAR decoding via the command register when sizing a BAR in pci_alloc_map() which is used to allocate resources for a BAR when the BIOS/firmware did not assign a usable resource range during boot. This mirrors an earlier fix to pci_add_map() which is used when to size BARs during boot. - Move the activation of I/O decoding in the PCI command register into pci_activate_resource() instead of doing it in pci_alloc_resource(). Previously we could actually enable decoding before a BAR was initialized via pci_alloc_map(). Glanced at by: bsdimp
2009-03-03 16:38:59 +00:00
resource_list_delete(rl, type, rid);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
struct resource_list *
Reduce code duplication by using the GET_RESOURCE_LIST bus method and related generic resource_list management functions. I'll deal with the EISA bits later. Not objected to by: new-bus
2000-11-28 07:12:12 +00:00
pci_get_resource_list (device_t dev, device_t child)
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
{
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
struct pci_devinfo *dinfo = device_get_ivars(child);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
return (&dinfo->resources);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Devices behind downstream bridges should still get DMAR protection. Reviewed by: kib Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D19717
2019-04-01 19:08:05 +00:00
#ifdef ACPI_DMAR
Rename dmar_get_dma_tag() to acpi_iommu_get_dma_tag(). This is needed for a new IOMMU controller support. Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D24943
2020-05-26 16:40:40 +00:00
bus_dma_tag_t acpi_iommu_get_dma_tag(device_t dev, device_t child);
Devices behind downstream bridges should still get DMAR protection. Reviewed by: kib Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D19717
2019-04-01 19:08:05 +00:00
bus_dma_tag_t
pci_get_dma_tag(device_t bus, device_t dev)
{
bus_dma_tag_t tag;
struct pci_softc *sc;
if (device_get_parent(dev) == bus) {
Rename dmar_get_dma_tag() to acpi_iommu_get_dma_tag(). This is needed for a new IOMMU controller support. Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D24943
2020-05-26 16:40:40 +00:00
/* try iommu and return if it works */
tag = acpi_iommu_get_dma_tag(bus, dev);
Devices behind downstream bridges should still get DMAR protection. Reviewed by: kib Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D19717
2019-04-01 19:08:05 +00:00
} else
tag = NULL;
if (tag == NULL) {
sc = device_get_softc(bus);
tag = sc->sc_dma_tag;
}
return (tag);
}
#else
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
bus_dma_tag_t
pci_get_dma_tag(device_t bus, device_t dev)
{
struct pci_softc *sc = device_get_softc(bus);
Simplify the PCI bus dma tag code a bit. First, don't create a tag at all for platforms that only have 32-bit bus addresses. Second, remove the 'tag_valid' flag from the softc. Instead, if we don't create a tag in pci_attach_common(), just cache the value of our parent's tag so that we always have a valid tag to return.
2012-03-07 18:50:33 +00:00
return (sc->sc_dma_tag);
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
}
Devices behind downstream bridges should still get DMAR protection. Reviewed by: kib Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D19717
2019-04-01 19:08:05 +00:00
#endif
- Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. The tag enforces a single restriction that all DMA transactions must not cross a 4GB boundary. Note that while this restriction technically only applies to PCI-express, this change applies it to all PCI devices as it is simpler to implement that way and errs on the side of caution. - Add a softc structure for PCI bus devices to hold the bus_dma tag and a new pci_attach_common() routine that performs actions common to the attach phase of all PCI bus drivers. Right now this only consists of a bootverbose printf and the allocate of a bus_dma tag if necessary. - Adjust all PCI bus drivers to allocate a PCI bus softc and to call pci_attach_common() from their attach routines. MFC after: 2 weeks
2012-03-02 20:38:04 +00:00
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint32_t
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
pci_read_config_method(device_t dev, device_t child, int reg, int width)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
Emulate the Device ID and Vendor ID registers for VFs The SR-IOV standard requires VFs to read all-ones when the VID and DID registers are read. The VMM (hypervisor) is required to emulate them instead. Make pci_read_config() do this emulation. Change pci_user.c to use pci_read_config() to read config space registers instead of going directly to the pcib so that the emulated VID/DID registers work correctly on VFs. This is required both for pciconf and bhyve PCI passthrough. Differential Revision: https://reviews.freebsd.org/D77 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
2015-03-01 00:40:19 +00:00
#ifdef PCI_IOV
/*
* SR-IOV VFs don't implement the VID or DID registers, so we have to
* emulate them here.
*/
if (cfg->flags & PCICFG_VF) {
if (reg == PCIR_VENDOR) {
switch (width) {
case 4:
return (cfg->device << 16 | cfg->vendor);
case 2:
return (cfg->vendor);
case 1:
return (cfg->vendor & 0xff);
default:
return (0xffffffff);
}
} else if (reg == PCIR_DEVICE) {
switch (width) {
/* Note that an unaligned 4-byte read is an error. */
case 2:
return (cfg->device);
case 1:
return (cfg->device & 0xff);
default:
return (0xffffffff);
}
}
}
#endif
More style(9) nits
2002-06-01 05:44:45 +00:00
return (PCIB_READ_CONFIG(device_get_parent(dev),
cfg->bus, cfg->slot, cfg->func, reg, width));
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Use the pci.c code wherever possible, rather than copying all the pci code into cardbus and s/pci/cardbus. This exposes a few pci_* functions that are now static. This work is similar to work Justin posted to the mobile list about a year or two ago, which I have neglected since then. This is a subset of his current work with the multiple inheritance newbus architecutre. When completed, that will eliminate the need for pci/pci_private.h. Similar work is needed for the cardbus_cis and pccard_cis code as well.
2002-02-27 05:09:14 +00:00
void
Various whitespace cleanups.
2006-11-07 18:55:51 +00:00
pci_write_config_method(device_t dev, device_t child, int reg,
Prefer the uintXX_t to the u_intXX_t names.
2003-08-22 03:11:53 +00:00
uint32_t val, int width)
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly. With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
PCIB_WRITE_CONFIG(device_get_parent(dev),
Make this file mostly conform to style(9). Approved by: msmith in principle before walkabout
2002-06-01 03:41:02 +00:00
cfg->bus, cfg->slot, cfg->func, reg, val, width);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Move the pnp and location info into the common pci bus. Make all known pci busses implement this. Also minor comment smithing in cardbus. Fix copyright to this year with my name on it since I've been doing a lot to this file. Reviewed by: jhb
2003-02-17 21:20:35 +00:00
int
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
pci_child_location_str_method(device_t dev, device_t child, char *buf,
Move the pnp and location info into the common pci bus. Make all known pci busses implement this. Also minor comment smithing in cardbus. Fix copyright to this year with my name on it since I've been doing a lot to this file. Reviewed by: jhb
2003-02-17 21:20:35 +00:00
size_t buflen)
{
Restore name=value format of PCI location strings. When devctl was added, the location string for PCI devices was changed to use the PCI "selector" that pciconf and devctl accept. However, devd assumes that location strings are formatted as a list of name=value pairs. As a result, devd is no longer parsing any of the values out of PCI device events. Restore the previous format of the PCI location strings to restore the location and slot keywords in case any devd scripts are using this. Add the "selector" as a new 'dbsf' location variable. Reviewed by: imp MFC after: 3 days Differential Revision: https://reviews.freebsd.org/D6253
2016-05-06 23:46:35 +00:00
snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d",
pci_get_slot(child), pci_get_function(child), pci_get_domain(child),
Add a new device control utility for new-bus devices called devctl. This allows the user to request administrative changes to individual devices such as attach or detaching drivers or disabling and re-enabling devices. - Add a new /dev/devctl2 character device which uses ioctls for device requests. The ioctls use a common 'struct devreq' which is somewhat similar to 'struct ifreq'. - The ioctls identify the device to operate on via a string. This string can either by the device's name, or it can be a bus-specific address. (For unattached devices, a bus address is the only way to locate a device.) Bus drivers register an eventhandler to claim unrecognized device names that the driver recognizes as a valid address. Two buses currently support addresses: ACPI recognizes any device in the ACPI namespace via its full path starting with "\" and the PCI bus driver recognizes an address specification of 'pci[<domain>:]<bus>:<slot>:<func>' (identical to the PCI selector strings supported by pciconf). - To make it easier to cut and paste, change the PnP location string in the PCI bus driver to output a full PCI selector string rather than 'slot=<slot> function=<func>'. - Add a devctl(3) interface in libdevctl which provides a wrapper around the ioctls and is the preferred interface for other userland code. - Add a devctl(8) program which is a simple wrapper around the requests supported by devctl(3). - Add a device_is_suspended() function to check DF_SUSPENDED. - Add a resource_unset_value() function that can be used to remove a hint from the kernel environment. This is used to clear a hint.<driver>.<unit>.disabled hint when re-enabling a boot-time disabled device. Reviewed by: imp (parts) Requested by: imp (changing PCI location string) Relnotes: yes
2015-02-06 16:09:01 +00:00
pci_get_bus(child), pci_get_slot(child), pci_get_function(child));
Move the pnp and location info into the common pci bus. Make all known pci busses implement this. Also minor comment smithing in cardbus. Fix copyright to this year with my name on it since I've been doing a lot to this file. Reviewed by: jhb
2003-02-17 21:20:35 +00:00
return (0);
}
int
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
Move the pnp and location info into the common pci bus. Make all known pci busses implement this. Also minor comment smithing in cardbus. Fix copyright to this year with my name on it since I've been doing a lot to this file. Reviewed by: jhb
2003-02-17 21:20:35 +00:00
size_t buflen)
{
struct pci_devinfo *dinfo;
pcicfgregs *cfg;
dinfo = device_get_ivars(child);
cfg = &dinfo->cfg;
snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
Include class designation in pnpinfo for generic driver loading
2003-02-18 03:25:57 +00:00
"subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
cfg->progif);
Move the pnp and location info into the common pci bus. Make all known pci busses implement this. Also minor comment smithing in cardbus. Fix copyright to this year with my name on it since I've been doing a lot to this file. Reviewed by: jhb
2003-02-17 21:20:35 +00:00
return (0);
}
Add a new PCI interface method, assign_interrupt, to determine the interrupt to be used for a device. This is intended solely for internal use of PCI bus implementations, and exists so that PCI bus drivers implementing special interrupt assignment methods which require additional work at the bus level to work right can be easily derived from the generic driver (or any other one) without resorting to hacks. It will be used in the sparc64 ofw_pcibus driver, which will be committed shortly. Make use of this method in the generic implementation, and add it to the method table of bus drivers derived from the PCI one. Reviewed by: imp, -hackers
2003-07-01 14:08:33 +00:00
int
pci_assign_interrupt_method(device_t dev, device_t child)
{
struct pci_devinfo *dinfo = device_get_ivars(child);
pcicfgregs *cfg = &dinfo->cfg;
return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
cfg->intpin));
}
Add a new device control utility for new-bus devices called devctl. This allows the user to request administrative changes to individual devices such as attach or detaching drivers or disabling and re-enabling devices. - Add a new /dev/devctl2 character device which uses ioctls for device requests. The ioctls use a common 'struct devreq' which is somewhat similar to 'struct ifreq'. - The ioctls identify the device to operate on via a string. This string can either by the device's name, or it can be a bus-specific address. (For unattached devices, a bus address is the only way to locate a device.) Bus drivers register an eventhandler to claim unrecognized device names that the driver recognizes as a valid address. Two buses currently support addresses: ACPI recognizes any device in the ACPI namespace via its full path starting with "\" and the PCI bus driver recognizes an address specification of 'pci[<domain>:]<bus>:<slot>:<func>' (identical to the PCI selector strings supported by pciconf). - To make it easier to cut and paste, change the PnP location string in the PCI bus driver to output a full PCI selector string rather than 'slot=<slot> function=<func>'. - Add a devctl(3) interface in libdevctl which provides a wrapper around the ioctls and is the preferred interface for other userland code. - Add a devctl(8) program which is a simple wrapper around the requests supported by devctl(3). - Add a device_is_suspended() function to check DF_SUSPENDED. - Add a resource_unset_value() function that can be used to remove a hint from the kernel environment. This is used to clear a hint.<driver>.<unit>.disabled hint when re-enabling a boot-time disabled device. Reviewed by: imp (parts) Requested by: imp (changing PCI location string) Relnotes: yes
2015-02-06 16:09:01 +00:00
static void
pci_lookup(void *arg, const char *name, device_t *dev)
{
long val;
char *end;
int domain, bus, slot, func;
if (*dev != NULL)
return;
/*
* Accept pciconf-style selectors of either pciD:B:S:F or
* pciB:S:F. In the latter case, the domain is assumed to
* be zero.
*/
if (strncmp(name, "pci", 3) != 0)
return;
val = strtol(name + 3, &end, 10);
if (val < 0 || val > INT_MAX || *end != ':')
return;
domain = val;
val = strtol(end + 1, &end, 10);
if (val < 0 || val > INT_MAX || *end != ':')
return;
bus = val;
val = strtol(end + 1, &end, 10);
if (val < 0 || val > INT_MAX)
return;
slot = val;
if (*end == ':') {
val = strtol(end + 1, &end, 10);
if (val < 0 || val > INT_MAX || *end != '\0')
return;
func = val;
} else if (*end == '\0') {
func = slot;
slot = bus;
bus = domain;
domain = 0;
} else
return;
if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX ||
func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX))
return;
*dev = pci_find_dbsf(domain, bus, slot, func);
}
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
static int
pci_modevent(module_t mod, int what, void *arg)
{
Do the dreaded s/dev_t/struct cdev */ Bump __FreeBSD_version accordingly.
2004-06-16 09:47:26 +00:00
static struct cdev *pci_cdev;
Add a new device control utility for new-bus devices called devctl. This allows the user to request administrative changes to individual devices such as attach or detaching drivers or disabling and re-enabling devices. - Add a new /dev/devctl2 character device which uses ioctls for device requests. The ioctls use a common 'struct devreq' which is somewhat similar to 'struct ifreq'. - The ioctls identify the device to operate on via a string. This string can either by the device's name, or it can be a bus-specific address. (For unattached devices, a bus address is the only way to locate a device.) Bus drivers register an eventhandler to claim unrecognized device names that the driver recognizes as a valid address. Two buses currently support addresses: ACPI recognizes any device in the ACPI namespace via its full path starting with "\" and the PCI bus driver recognizes an address specification of 'pci[<domain>:]<bus>:<slot>:<func>' (identical to the PCI selector strings supported by pciconf). - To make it easier to cut and paste, change the PnP location string in the PCI bus driver to output a full PCI selector string rather than 'slot=<slot> function=<func>'. - Add a devctl(3) interface in libdevctl which provides a wrapper around the ioctls and is the preferred interface for other userland code. - Add a devctl(8) program which is a simple wrapper around the requests supported by devctl(3). - Add a device_is_suspended() function to check DF_SUSPENDED. - Add a resource_unset_value() function that can be used to remove a hint from the kernel environment. This is used to clear a hint.<driver>.<unit>.disabled hint when re-enabling a boot-time disabled device. Reviewed by: imp (parts) Requested by: imp (changing PCI location string) Relnotes: yes
2015-02-06 16:09:01 +00:00
static eventhandler_tag tag;
- Make pci_load_vendor_data() static and do it during MOD_LOAD instead of when the first PCI bus attaches. - Create /dev/pci during MOD_LOAD as well. - Destroy /dev/pci during MOD_UNLOAD (not that you can kldunload pci, but might as well get the code right)
2002-09-04 03:13:16 +00:00
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
switch (what) {
case MOD_LOAD:
Argh, don't clobber the pci device list if there are multiple busses! (An AGP counts as a PCI bus, it seems...) This stopped 'pciconf -l' from working on AGP or PCI->PCI bridge systems.
1999-05-09 15:54:04 +00:00
STAILQ_INIT(&pci_devq);
Next round of PCI subsystem updates: - Break out the /dev/pci driver into a separate file. - Kill the COMPAT_OLDPCI support. - Make the EISA bridge attach a bit more like the old code; explicitly check for the existence of eisa0/isa0 and only attach if they don't already exist. Only make one bus_generic_attach() pass over the bridge, once both busses are attached. Note that the stupid Intel bridge's class is entirely unpredictable. - Add prototypes and re-layout the core PCI modules in line with current coding standards (not a major whitespace change, just moving the module data to the top of the file). - Remove redundant type-2 bridge support from the core PCI code; the PCI-CardBus code does this itself internally. Remove the now entirely redundant header-class-specific support, as well as the secondary and subordinate bus number fields. These are bridge attributes now. - Add support for PCI Extended Capabilities. - Add support for PCI Power Management. The interface currently allows a driver to query and set the power state of a device. - Add helper functions to allow drivers to enable/disable busmastering and the decoding of I/O and memory ranges. - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some places. - Make the PCI-PCI bridge code a little more paranoid about valid I/O and memory decodes. - Add some more PCI register definitions for the command and status registers. Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
pci_generation = 0;
- Make pci_load_vendor_data() static and do it during MOD_LOAD instead of when the first PCI bus attaches. - Create /dev/pci during MOD_LOAD as well. - Destroy /dev/pci during MOD_UNLOAD (not that you can kldunload pci, but might as well get the code right)
2002-09-04 03:13:16 +00:00
pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
"pci");
pci_load_vendor_data();
Add a new device control utility for new-bus devices called devctl. This allows the user to request administrative changes to individual devices such as attach or detaching drivers or disabling and re-enabling devices. - Add a new /dev/devctl2 character device which uses ioctls for device requests. The ioctls use a common 'struct devreq' which is somewhat similar to 'struct ifreq'. - The ioctls identify the device to operate on via a string. This string can either by the device's name, or it can be a bus-specific address. (For unattached devices, a bus address is the only way to locate a device.) Bus drivers register an eventhandler to claim unrecognized device names that the driver recognizes as a valid address. Two buses currently support addresses: ACPI recognizes any device in the ACPI namespace via its full path starting with "\" and the PCI bus driver recognizes an address specification of 'pci[<domain>:]<bus>:<slot>:<func>' (identical to the PCI selector strings supported by pciconf). - To make it easier to cut and paste, change the PnP location string in the PCI bus driver to output a full PCI selector string rather than 'slot=<slot> function=<func>'. - Add a devctl(3) interface in libdevctl which provides a wrapper around the ioctls and is the preferred interface for other userland code. - Add a devctl(8) program which is a simple wrapper around the requests supported by devctl(3). - Add a device_is_suspended() function to check DF_SUSPENDED. - Add a resource_unset_value() function that can be used to remove a hint from the kernel environment. This is used to clear a hint.<driver>.<unit>.disabled hint when re-enabling a boot-time disabled device. Reviewed by: imp (parts) Requested by: imp (changing PCI location string) Relnotes: yes
2015-02-06 16:09:01 +00:00
tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL,
1000);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
break;
case MOD_UNLOAD:
Add a new device control utility for new-bus devices called devctl. This allows the user to request administrative changes to individual devices such as attach or detaching drivers or disabling and re-enabling devices. - Add a new /dev/devctl2 character device which uses ioctls for device requests. The ioctls use a common 'struct devreq' which is somewhat similar to 'struct ifreq'. - The ioctls identify the device to operate on via a string. This string can either by the device's name, or it can be a bus-specific address. (For unattached devices, a bus address is the only way to locate a device.) Bus drivers register an eventhandler to claim unrecognized device names that the driver recognizes as a valid address. Two buses currently support addresses: ACPI recognizes any device in the ACPI namespace via its full path starting with "\" and the PCI bus driver recognizes an address specification of 'pci[<domain>:]<bus>:<slot>:<func>' (identical to the PCI selector strings supported by pciconf). - To make it easier to cut and paste, change the PnP location string in the PCI bus driver to output a full PCI selector string rather than 'slot=<slot> function=<func>'. - Add a devctl(3) interface in libdevctl which provides a wrapper around the ioctls and is the preferred interface for other userland code. - Add a devctl(8) program which is a simple wrapper around the requests supported by devctl(3). - Add a device_is_suspended() function to check DF_SUSPENDED. - Add a resource_unset_value() function that can be used to remove a hint from the kernel environment. This is used to clear a hint.<driver>.<unit>.disabled hint when re-enabling a boot-time disabled device. Reviewed by: imp (parts) Requested by: imp (changing PCI location string) Relnotes: yes
2015-02-06 16:09:01 +00:00
if (tag != NULL)
EVENTHANDLER_DEREGISTER(dev_lookup, tag);
- Make pci_load_vendor_data() static and do it during MOD_LOAD instead of when the first PCI bus attaches. - Create /dev/pci during MOD_LOAD as well. - Destroy /dev/pci during MOD_UNLOAD (not that you can kldunload pci, but might as well get the code right)
2002-09-04 03:13:16 +00:00
destroy_dev(pci_cdev);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
break;
}
More style(9) nits
2002-06-01 05:44:45 +00:00
return (0);
Bring the 'new-bus' to the i386. This extensively changes the way the i386 platform boots, it is no longer ISA-centric, and is fully dynamic. Most old drivers compile and run without modification via 'compatability shims' to enable a smoother transition. eisa, isapnp and pccard* are not yet using the new resource manager. Once fully converted, all drivers will be loadable, including PCI and ISA. (Some other changes appear to have snuck in, including a port of Soren's ATA driver to the Alpha. Soren, back this out if you need to.) This is a checkpoint of work-in-progress, but is quite functional. The bulk of the work was done over the last few years by Doug Rabson and Garrett Wollman. Approved by: core
1999-04-16 21:22:55 +00:00
}
Add pci_resume() to reestablish interrupt routing after suspend/resume. Especially after hibernation, interrupt routing went back to initial status on some machines.
2003-09-17 08:32:44 +00:00
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
static void
pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
{
#define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
struct pcicfg_pcie *cfg;
int version, pos;
cfg = &dinfo->cfg.pcie;
pos = cfg->pcie_location;
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
(cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
(cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
if (version > 1) {
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
}
#undef WREG
}
static void
pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
{
pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
dinfo->cfg.pcix.pcix_command, 2);
}
Expose pci_cfg_safe/restore for subclasses of pci to use.
2005-02-28 01:14:15 +00:00
void
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
Add pci_resume() to reestablish interrupt routing after suspend/resume. Especially after hibernation, interrupt routing went back to initial status on some machines.
2003-09-17 08:32:44 +00:00
{
Add system tunable to turn off power state changes. Default to off until we get the resource allocation stuff hammered out. Fix and off by one error that caused unnecessary filtering of valid BARs for only 4 bytes than ICH3 and other PCI IDE controllers have. Andrew Gallatin submitted this, although it doesn't solve the problems ICH3 controllers have with the new code, it does restore the former resource list on the probe line.
2004-04-11 07:02:49 +00:00
/*
* Restore the device to full power mode. We must do this
* before we restore the registers because moving from D3 to
* D0 will cause the chip's BARs and some other registers to
* be reset to some unknown power on reset values. Cut down
* the noise on boot by doing nothing if we are already in
* state D0.
*/
Remove unnecessary castings and fix couple of style(9) nits.
2010-10-15 21:41:59 +00:00
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
Only print state change message for real state changes. When we set a device in D0 to D0, that's a no-op, however the messages seem to be confusing some people. Eventually, these messages will be parked behind a if (bootverbose). # I don't think this will fix any real bugs...
2004-04-09 20:41:18 +00:00
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
MFp4: o save/restore subvendor, subdevice, vendor, device, baseclass, subclass, progif and revid. While these are typically read only fields, they aren't always read-only. progif is writable for ata devices, for example. It does no harm when they are read only, and helps when they aren't.
2004-05-21 06:36:36 +00:00
pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
Update the pci_cfg_save/restore routines to operate on bridge devices (type 1 and type 2) as well as leaf devices (type 0). In particular, this allows the existing PCI bus logic to save and restore capability registers such as MSI and PCI-express work for bridge devices rather than requiring that code to be duplicated in bridge drivers. It also means that bridge drivers no longer need to save and restore basic registers such as the PCI command register or BARs nor manage powerstates for the bridge device. While here, pci_setup_secbus() has been changed to initialize the 'sec' and 'sub' fields in the 'secbus' structure instead of requiring the pcib and pccbb drivers to do this in the NEW_PCIB + PCI_RES_BUS case. Differential Revision: https://reviews.freebsd.org/D2240 Reviewed by: imp, jmg MFC after: 2 weeks
2015-04-22 22:02:27 +00:00
switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
case PCIM_HDRTYPE_NORMAL:
pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
break;
case PCIM_HDRTYPE_BRIDGE:
pci_write_config(dev, PCIR_SECLAT_1,
dinfo->cfg.bridge.br_seclat, 1);
pci_write_config(dev, PCIR_SUBBUS_1,
dinfo->cfg.bridge.br_subbus, 1);
pci_write_config(dev, PCIR_SECBUS_1,
dinfo->cfg.bridge.br_secbus, 1);
pci_write_config(dev, PCIR_PRIBUS_1,
dinfo->cfg.bridge.br_pribus, 1);
pci_write_config(dev, PCIR_BRIDGECTL_1,
dinfo->cfg.bridge.br_control, 2);
break;
case PCIM_HDRTYPE_CARDBUS:
pci_write_config(dev, PCIR_SECLAT_2,
dinfo->cfg.bridge.br_seclat, 1);
pci_write_config(dev, PCIR_SUBBUS_2,
dinfo->cfg.bridge.br_subbus, 1);
pci_write_config(dev, PCIR_SECBUS_2,
dinfo->cfg.bridge.br_secbus, 1);
pci_write_config(dev, PCIR_PRIBUS_2,
dinfo->cfg.bridge.br_pribus, 1);
pci_write_config(dev, PCIR_BRIDGECTL_2,
dinfo->cfg.bridge.br_control, 2);
break;
}
pci_restore_bars(dev);
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
do not enable pci bridge decoding on resume until I/O windows are restored PCI bus driver restores most but not all of a child PCI-PCI bridge configuration. The bridge's I/O windows are restored by pcib driver and that happens later in time. This can be problematic because the Command register is restored before the windows are restored. If the firmware programs the windows incorrectly or even does not program them at all, then the bridge can start claiming I/O cycles that are not intended for it. This will continue until the correct windows are restored. I have observed this problem with a buggy BIOS where after resuming from S3 an I/O port window of a PCI-PCI bridge was configured with zero base and limit causing the bridge to claim 0x0 - 0xFFF port range. That interfered with ACPI port access including ACPI PM Timer at port 0x808, thus wreaking havoc in the time keeping. The solution is to restore the Command register of PCI-PCI bridges after the windows are restored in pcib driver. While here, I decided that for other PCI device types (normal and cardbus) it's better to restore the Command register after their BARs are restored. To do: per jhb's suggestion, move the window handling to pci driver. Reviewed by: imp, jhb, kib MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D25028
2020-05-29 07:50:55 +00:00
if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE)
pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
/*
* Restore extended capabilities for PCI-Express and PCI-X
*/
if (dinfo->cfg.pcie.pcie_location != 0)
pci_cfg_restore_pcie(dev, dinfo);
if (dinfo->cfg.pcix.pcix_location != 0)
pci_cfg_restore_pcix(dev, dinfo);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
/* Restore MSI and MSI-X configurations if they are present. */
First cut at MI support for PCI Message Signalled Interrupts (MSI): - Add 3 new functions to the pci_if interface along with suitable wrappers to provide the device driver visible API: - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count' here is an in and out parameter. The driver stores the desired number of messages in '*count' before calling the function. On success, '*count' holds the number of messages allocated to the device. Also on success, the driver can access the messages as SYS_RES_IRQ resources starting at rid 1. Note that the legacy INTx interrupt resource will not be available when using MSI. Note that this function will allocate either MSI or MSI-X messages depending on the devices capabilities and the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note that the driver should activate the memory resource that holds the MSI-X table and pending bit array (PBA) before calling this function if the device supports MSI-X. - pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function releases the messages allocated for this device. All of the SYS_RES_IRQ resources need to be released for this function to succeed. - pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns the maximum number of MSI or MSI-X messages supported by this device. MSI-X is preferred if present, but this function will honor the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function should return the largest value that pci_alloc_msi() can return (assuming the MD code is able to allocate sufficient backing resources for all of the messages). - Add default implementations for these 3 methods to the pci_driver generic PCI bus driver. (The various other PCI bus drivers such as for ACPI and OFW will inherit these default implementations.) This default implementation depends on 4 new pcib_if methods that bubble up through the PCI bridges to the MD code to allocate IRQ values and perform any needed MD setup code needed: - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages. - PCIB_RELEASE_MSI() releases a group of MSI messages. - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message. - PCIB_RELEASE_MSIX() releases a single MSI-X message. - Add default implementations for these 4 methods that just pass the request up to the parent bus's parent bridge driver and use the default implementation in the various MI PCI bridge drivers. - Add MI functions for use by MD code when managing MSI and MSI-X interrupts: - pci_enable_msi(dev, address, data) programs the MSI capability address and data registers for a group of MSI messages - pci_enable_msix(dev, index, address, data) initializes a single MSI-X message in the MSI-X table - pci_mask_msix(dev, index) masks a single MSI-X message - pci_unmask_msix(dev, index) unmasks a single MSI-X message - pci_pending_msix(dev, index) returns true if the specified MSI-X message is currently pending - Save the MSI capability address and data registers in the pci_cfgreg block in a PCI devices ivars and restore the values when a device is resumed. Note that the MSI-X table is not currently restored during resume. - Add constants for MSI-X register offsets and fields. - Record interesting data about any MSI-X capability blocks we come across in the pci_cfgreg block in the ivars for PCI devices. Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X) Reviewed by: scottl, grehan, jfv MFC after: 2 months
2006-11-13 21:47:30 +00:00
if (dinfo->cfg.msi.msi_location != 0)
pci_resume_msi(dev);
Revamp the MSI/MSI-X code a bit to achieve two main goals: - Simplify the amount of work that has be done for each architecture by pushing more of the truly MI code down into the PCI bus driver. - Don't bind MSI-X indicies to IRQs so that we can allow a driver to map multiple MSI-X messages into a single IRQ when handling a message shortage. The changes include: - Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus to calculate the address and data values for a given MSI/MSI-X IRQ. The x86 nexus drivers map this into a call to a new 'msi_map()' function in msi.c that does the mapping. - Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index' parameter from PCIB_ALLOC_MSIX(). MD code no longer has any knowledge of the MSI-X index for a given MSI-X IRQ. - The PCI bus driver now stores more MSI-X state in a child's ivars. Specifically, it now stores an array of IRQs (called "message vectors" in the code) that have associated address and data values, and a small virtual version of the MSI-X table that specifies the message vector that a given MSI-X table entry uses. Sparse mappings are permitted in the virtual table. - The PCI bus driver now configures the MSI and MSI-X address/data registers directly via custom bus_setup_intr() and bus_teardown_intr() methods. pci_setup_intr() invokes PCIB_MAP_MSI() to determine the address and data values for a given message as needed. The MD code no longer has to call back down into the PCI bus code to set these values from the nexus' bus_setup_intr() handler. - The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get new values of the address and data fields for a given IRQ. The x86 MSI code uses this when an MSI IRQ is moved to a different CPU, requiring a new value of the 'address' field. - The x86 MSI psuedo-driver loses a lot of code, and in fact the separate MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver since the only remaining diff between the two is a substring in a bootverbose printf. - The PCI bus driver will now restore MSI-X state (including programming entries in the MSI-X table) on device resume. - The interface for pci_remap_msix() has changed. Instead of accepting indices for the allocated vectors, it accepts a mini-virtual table (with a new length parameter). This table is an array of u_ints, where each value specifies which allocated message vector to use for the corresponding MSI-X message. A vector of 0 forces a message to not have an associated IRQ. The device may choose to only use some of the IRQs assigned, in which case the unused IRQs must be at the "end" and will be released back to the system. This allows a driver to use the same remap table for different shortage values. For example, if a driver wants 4 messages, it can use the same remap table (which only uses the first two messages) for the cases when it only gets 2 or 3 messages and in the latter case the PCI bus will release the 3rd IRQ back to the system. MFC after: 1 month
2007-05-02 17:50:36 +00:00
if (dinfo->cfg.msix.msix_location != 0)
pci_resume_msix(dev);
Save and restore SRIOV-related config registers. Save the value of the IOV control and page size registers and restore them (along with the VF count) in pci_cfg_save/pci_cfg_restore. This ensures ARI remains enabled if a PF driver resets itself during the PCI_IOV_INIT callback. This might also properly restore SRIOV state across suspend/resume. Reviewed by: rstone, vangyzen Differential Revision: https://reviews.freebsd.org/D6192
2016-05-03 19:45:24 +00:00
Fix build without "options PCI_IOV".
2016-05-04 06:22:41 +00:00
#ifdef PCI_IOV
Save and restore SRIOV-related config registers. Save the value of the IOV control and page size registers and restore them (along with the VF count) in pci_cfg_save/pci_cfg_restore. This ensures ARI remains enabled if a PF driver resets itself during the PCI_IOV_INIT callback. This might also properly restore SRIOV state across suspend/resume. Reviewed by: rstone, vangyzen Differential Revision: https://reviews.freebsd.org/D6192
2016-05-03 19:45:24 +00:00
if (dinfo->cfg.iov != NULL)
pci_iov_cfg_restore(dev, dinfo);
Fix build without "options PCI_IOV".
2016-05-04 06:22:41 +00:00
#endif
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
}
Add pci_resume() to reestablish interrupt routing after suspend/resume. Especially after hibernation, interrupt routing went back to initial status on some machines.
2003-09-17 08:32:44 +00:00
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
static void
pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
{
#define RREG(n) pci_read_config(dev, pos + (n), 2)
struct pcicfg_pcie *cfg;
int version, pos;
cfg = &dinfo->cfg.pcie;
pos = cfg->pcie_location;
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
cfg->pcie_flags = RREG(PCIER_FLAGS);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
(cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
(cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
if (version > 1) {
Align the PCI Express #defines with the style used for the PCI-X #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week
2012-09-18 22:04:59 +00:00
cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
}
#undef RREG
}
static void
pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
{
dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
}
Expose pci_cfg_safe/restore for subclasses of pci to use.
2005-02-28 01:14:15 +00:00
void
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
{
uint32_t cls;
Add system tunable to turn off power state changes. Default to off until we get the resource allocation stuff hammered out. Fix and off by one error that caused unnecessary filtering of valid BARs for only 4 bytes than ICH3 and other PCI IDE controllers have. Andrew Gallatin submitted this, although it doesn't solve the problems ICH3 controllers have with the new code, it does restore the former resource list on the probe line.
2004-04-11 07:02:49 +00:00
int ps;
Add pci_resume() to reestablish interrupt routing after suspend/resume. Especially after hibernation, interrupt routing went back to initial status on some machines.
2003-09-17 08:32:44 +00:00
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
/*
Fix comments to match last commit, and minor reformatting...
2004-12-08 04:35:19 +00:00
* Some drivers apparently write to these registers w/o updating our
Fix typo.
2005-01-29 19:45:31 +00:00
* cached copy. No harm happens if we update the copy, so do so here
Fix comments to match last commit, and minor reformatting...
2004-12-08 04:35:19 +00:00
* so we can restore them. The COMMAND register is modified by the
* bus w/o updating the cache. This should represent the normally
Update the pci_cfg_save/restore routines to operate on bridge devices (type 1 and type 2) as well as leaf devices (type 0). In particular, this allows the existing PCI bus logic to save and restore capability registers such as MSI and PCI-express work for bridge devices rather than requiring that code to be duplicated in bridge drivers. It also means that bridge drivers no longer need to save and restore basic registers such as the PCI command register or BARs nor manage powerstates for the bridge device. While here, pci_setup_secbus() has been changed to initialize the 'sec' and 'sub' fields in the 'secbus' structure instead of requiring the pcib and pccbb drivers to do this in the NEW_PCIB + PCI_RES_BUS case. Differential Revision: https://reviews.freebsd.org/D2240 Reviewed by: imp, jmg MFC after: 2 weeks
2015-04-22 22:02:27 +00:00
* writable portion of the 'defined' part of type 0/1/2 headers.
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
*/
MFp4: o save/restore subvendor, subdevice, vendor, device, baseclass, subclass, progif and revid. While these are typically read only fields, they aren't always read-only. progif is writable for ata devices, for example. It does no harm when they are read only, and helps when they aren't.
2004-05-21 06:36:36 +00:00
dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
MFp4: o save/restore subvendor, subdevice, vendor, device, baseclass, subclass, progif and revid. While these are typically read only fields, they aren't always read-only. progif is writable for ata devices, for example. It does no harm when they are read only, and helps when they aren't.
2004-05-21 06:36:36 +00:00
dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
Update the pci_cfg_save/restore routines to operate on bridge devices (type 1 and type 2) as well as leaf devices (type 0). In particular, this allows the existing PCI bus logic to save and restore capability registers such as MSI and PCI-express work for bridge devices rather than requiring that code to be duplicated in bridge drivers. It also means that bridge drivers no longer need to save and restore basic registers such as the PCI command register or BARs nor manage powerstates for the bridge device. While here, pci_setup_secbus() has been changed to initialize the 'sec' and 'sub' fields in the 'secbus' structure instead of requiring the pcib and pccbb drivers to do this in the NEW_PCIB + PCI_RES_BUS case. Differential Revision: https://reviews.freebsd.org/D2240 Reviewed by: imp, jmg MFC after: 2 weeks
2015-04-22 22:02:27 +00:00
switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
case PCIM_HDRTYPE_NORMAL:
dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
break;
case PCIM_HDRTYPE_BRIDGE:
dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
PCIR_SECLAT_1, 1);
dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
PCIR_SUBBUS_1, 1);
dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
PCIR_SECBUS_1, 1);
dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
PCIR_PRIBUS_1, 1);
dinfo->cfg.bridge.br_control = pci_read_config(dev,
PCIR_BRIDGECTL_1, 2);
break;
case PCIM_HDRTYPE_CARDBUS:
dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
PCIR_SECLAT_2, 1);
dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
PCIR_SUBBUS_2, 1);
dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
PCIR_SECBUS_2, 1);
dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
PCIR_PRIBUS_2, 1);
dinfo->cfg.bridge.br_control = pci_read_config(dev,
PCIR_BRIDGECTL_2, 2);
dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2);
dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2);
break;
}
Add pci_resume() to reestablish interrupt routing after suspend/resume. Especially after hibernation, interrupt routing went back to initial status on some machines.
2003-09-17 08:32:44 +00:00
Save more of config space for PCI Express and PCI-X devices. Expand pci_save_state and pci_restore_state to save more of the config state for PCI Express and PCI-X devices. Various writable control registers are present in PCI Express that can potentially be lost over suspend/resume cycle. This change is modeled after similar functionality in Linux. Reviewed by: wlosh,jhb MFC after: 1 month
2012-03-08 21:09:34 +00:00
if (dinfo->cfg.pcie.pcie_location != 0)
pci_cfg_save_pcie(dev, dinfo);
if (dinfo->cfg.pcix.pcix_location != 0)
pci_cfg_save_pcix(dev, dinfo);
Fix build without "options PCI_IOV".
2016-05-04 06:22:41 +00:00
#ifdef PCI_IOV
Save and restore SRIOV-related config registers. Save the value of the IOV control and page size registers and restore them (along with the VF count) in pci_cfg_save/pci_cfg_restore. This ensures ARI remains enabled if a PF driver resets itself during the PCI_IOV_INIT callback. This might also properly restore SRIOV state across suspend/resume. Reviewed by: rstone, vangyzen Differential Revision: https://reviews.freebsd.org/D6192
2016-05-03 19:45:24 +00:00
if (dinfo->cfg.iov != NULL)
pci_iov_cfg_save(dev, dinfo);
Fix build without "options PCI_IOV".
2016-05-04 06:22:41 +00:00
#endif
Save and restore SRIOV-related config registers. Save the value of the IOV control and page size registers and restore them (along with the VF count) in pci_cfg_save/pci_cfg_restore. This ensures ARI remains enabled if a PF driver resets itself during the PCI_IOV_INIT callback. This might also properly restore SRIOV state across suspend/resume. Reviewed by: rstone, vangyzen Differential Revision: https://reviews.freebsd.org/D6192
2016-05-03 19:45:24 +00:00
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
/*
Fix comments to match last commit, and minor reformatting...
2004-12-08 04:35:19 +00:00
* don't set the state for display devices, base peripherals and
* memory devices since bad things happen when they are powered down.
* We should (a) have drivers that can easily detach and (b) use
* generic drivers for these devices so that some device actually
* attaches. We need to make sure that when we implement (a) we don't
* power the device down on a reattach.
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
*/
cls = pci_get_class(dev);
Change hw.pci.do_powerstate from a boolean to a range. 0 means the same as today: do no power management. 1 means be conservative about what you power down (any device class that has caused problems gets added here). 2 means be agressive about what gets powered down (any device class that's fundamental to the system is here). 3 means power them all down, reguardless. The default is 1. The effect in the default system is to add mass storage devices to the list that we don't power down. From all the pciconf -l lists that I've seen for the aac and amr issue, the bad device has been a mass storage device class. This is an attempt at a compromise between the very small number of systems that have extreme issues with powerdown, and the very large number of systems that gain real benefits from powerdown (I get about 20% more battery life when I attach a minimal set of drivers on my Sony). Hopefully it will strike the proper balance. MFC After: 3 days (before next beta)
2005-09-11 04:09:44 +00:00
if (!setstate)
return;
Split power state control into two variables. hw.pci.do_powerstate has been removed. It has been replaced by hw.pci.do_power_nodriver and hw.pci.do_power_resume. The former defaults to 0 while the latter defaults to 1. When do_powerstate was set to 0, it broke suspend/resume for a lot of people as an unintended consequence. This change will only affect the areas that were intended to affect. This change will have no effect on servers, but will help laptops quite a bit. MFC After: 3 days.
2005-09-21 19:47:00 +00:00
switch (pci_do_power_nodriver)
Change hw.pci.do_powerstate from a boolean to a range. 0 means the same as today: do no power management. 1 means be conservative about what you power down (any device class that has caused problems gets added here). 2 means be agressive about what gets powered down (any device class that's fundamental to the system is here). 3 means power them all down, reguardless. The default is 1. The effect in the default system is to add mass storage devices to the list that we don't power down. From all the pciconf -l lists that I've seen for the aac and amr issue, the bad device has been a mass storage device class. This is an attempt at a compromise between the very small number of systems that have extreme issues with powerdown, and the very large number of systems that gain real benefits from powerdown (I get about 20% more battery life when I attach a minimal set of drivers on my Sony). Hopefully it will strike the proper balance. MFC After: 3 days (before next beta)
2005-09-11 04:09:44 +00:00
{
case 0: /* NO powerdown at all */
return;
case 1: /* Conservative about what to power down */
if (cls == PCIC_STORAGE)
return;
/*FALLTHROUGH*/
sys/dev: minor spelling fixes. Most affect comments, very few have user-visible effects.
2016-05-03 03:41:25 +00:00
case 2: /* Aggressive about what to power down */
Change hw.pci.do_powerstate from a boolean to a range. 0 means the same as today: do no power management. 1 means be conservative about what you power down (any device class that has caused problems gets added here). 2 means be agressive about what gets powered down (any device class that's fundamental to the system is here). 3 means power them all down, reguardless. The default is 1. The effect in the default system is to add mass storage devices to the list that we don't power down. From all the pciconf -l lists that I've seen for the aac and amr issue, the bad device has been a mass storage device class. This is an attempt at a compromise between the very small number of systems that have extreme issues with powerdown, and the very large number of systems that gain real benefits from powerdown (I get about 20% more battery life when I attach a minimal set of drivers on my Sony). Hopefully it will strike the proper balance. MFC After: 3 days (before next beta)
2005-09-11 04:09:44 +00:00
if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
cls == PCIC_BASEPERIPH)
return;
/*FALLTHROUGH*/
case 3: /* Power down everything */
break;
Omnibus PCI commit: o Save and restore bars for suspend/resume as well as for D3->D0 transitions. o preallocate resources that the PCI devices use to avoid resource conflicts o lazy allocation of resources not allocated by the BIOS. o set unattached drivers to state D3. Set power state to D0 before probe/attach. Right now there's two special cases for this (display and memory devices) that need work in other areas of the tree. Please report any bugs to me.
2004-04-09 15:44:34 +00:00
}
Change hw.pci.do_powerstate from a boolean to a range. 0 means the same as today: do no power management. 1 means be conservative about what you power down (any device class that has caused problems gets added here). 2 means be agressive about what gets powered down (any device class that's fundamental to the system is here). 3 means power them all down, reguardless. The default is 1. The effect in the default system is to add mass storage devices to the list that we don't power down. From all the pciconf -l lists that I've seen for the aac and amr issue, the bad device has been a mass storage device class. This is an attempt at a compromise between the very small number of systems that have extreme issues with powerdown, and the very large number of systems that gain real benefits from powerdown (I get about 20% more battery life when I attach a minimal set of drivers on my Sony). Hopefully it will strike the proper balance. MFC After: 3 days (before next beta)
2005-09-11 04:09:44 +00:00
/*
* PCI spec says we can only go into D3 state from D0 state.
* Transition from D[12] into D0 before going to D3 state.
*/
ps = pci_get_powerstate(dev);
if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
pci_set_powerstate(dev, PCI_POWERSTATE_D3);
Add pci_resume() to reestablish interrupt routing after suspend/resume. Especially after hibernation, interrupt routing went back to initial status on some machines.
2003-09-17 08:32:44 +00:00
}
Add pci_save_state() and pci_restore_state() wrappers around pci_cfg_save() and pci_cfg_restore() for device drivers to use when saving and restoring state (e.g. to handle device-specific resets). Reviewed by: imp MFC after: 2 weeks
2012-03-01 20:20:55 +00:00
/* Wrapper APIs suitable for device driver use. */
void
pci_save_state(device_t dev)
{
struct pci_devinfo *dinfo;
dinfo = device_get_ivars(dev);
pci_cfg_save(dev, dinfo, 0);
}
void
pci_restore_state(device_t dev)
{
struct pci_devinfo *dinfo;
dinfo = device_get_ivars(dev);
pci_cfg_restore(dev, dinfo);
}
Add a method to get the PCI RID for a device. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 15:47:24 +00:00
Re-commit r299467 having fixed the build: Add a new get_id interface to pci and pcib. This will allow us to both detect failures, and get different PCI IDs. For the former the interface returns an int to signal an error. The ID is returned at a uintptr_t * argument. For the latter there is a type argument that allows selecting the ID type. This only specifies a single type, however a MSI type will be added to handle the need to find the ID the hardware passes to the ARM GICv3 interrupt controller. A follow up commit will be made to remove pci_get_rid. Reviewed by: jhb, rstone (previous version) Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D6239
2016-05-16 09:15:50 +00:00
static int
pci_get_id_method(device_t dev, device_t child, enum pci_id_type type,
uintptr_t *id)
Add a method to get the PCI RID for a device. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 15:47:24 +00:00
{
Re-commit r299467 having fixed the build: Add a new get_id interface to pci and pcib. This will allow us to both detect failures, and get different PCI IDs. For the former the interface returns an int to signal an error. The ID is returned at a uintptr_t * argument. For the latter there is a type argument that allows selecting the ID type. This only specifies a single type, however a MSI type will be added to handle the need to find the ID the hardware passes to the ARM GICv3 interrupt controller. A follow up commit will be made to remove pci_get_rid. Reviewed by: jhb, rstone (previous version) Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D6239
2016-05-16 09:15:50 +00:00
return (PCIB_GET_ID(device_get_parent(dev), child, type, id));
Add a method to get the PCI RID for a device. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc.
2014-04-01 15:47:24 +00:00
}
Add a new helper function for PCI devices to locate the upstream PCI-express root port of a given PCI device. Reviewed by: kib, imp MFC after: 1 week Sponsored by: Chelsio Differential Revision: https://reviews.freebsd.org/D4089
2015-11-05 21:27:25 +00:00
/* Find the upstream port of a given PCI device in a root complex. */
device_t
pci_find_pcie_root_port(device_t dev)
{
struct pci_devinfo *dinfo;
devclass_t pci_class;
device_t pcib, bus;
pci_class = devclass_find("pci");
KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class,
("%s: non-pci device %s", __func__, device_get_nameunit(dev)));
/*
* Walk the bridge hierarchy until we find a PCI-e root
* port or a non-PCI device.
*/
for (;;) {
bus = device_get_parent(dev);
KASSERT(bus != NULL, ("%s: null parent of %s", __func__,
device_get_nameunit(dev)));
pcib = device_get_parent(bus);
KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__,
device_get_nameunit(bus)));
/*
* pcib's parent must be a PCI bus for this to be a
* PCI-PCI bridge.
*/
if (device_get_devclass(device_get_parent(pcib)) != pci_class)
return (NULL);
dinfo = device_get_ivars(pcib);
if (dinfo->cfg.pcie.pcie_location != 0 &&
dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)
return (pcib);
dev = pcib;
}
}
Reset PCI pass through devices via PCI-e FLR during VM start and end. Add routines to trigger a function level reset (FLR) of a PCI-express device via the PCI-express device control register. This also includes support routines to wait for pending transactions to complete as well as calculating the maximum completion timeout permitted by a device. Change the ppt(4) driver to reset pass through devices before attaching to a VM during startup and before detaching from a VM during shutdown. Reviewed by: imp, wblock (earlier version) MFC after: 1 month Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D7751
2016-09-06 21:15:35 +00:00
/*
* Wait for pending transactions to complete on a PCI-express function.
*
* The maximum delay is specified in milliseconds in max_delay. Note
* that this function may sleep.
*
* Returns true if the function is idle and false if the timeout is
* exceeded. If dev is not a PCI-express function, this returns true.
*/
bool
pcie_wait_for_pending_transactions(device_t dev, u_int max_delay)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
uint16_t sta;
int cap;
cap = dinfo->cfg.pcie.pcie_location;
if (cap == 0)
return (true);
sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
while (sta & PCIEM_STA_TRANSACTION_PND) {
if (max_delay == 0)
return (false);
/* Poll once every 100 milliseconds up to the timeout. */
if (max_delay > 100) {
pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK);
max_delay -= 100;
} else {
pause_sbt("pcietp", max_delay * SBT_1MS, 0,
C_HARDCLOCK);
max_delay = 0;
}
sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
}
return (true);
}
/*
* Determine the maximum Completion Timeout in microseconds.
*
* For non-PCI-express functions this returns 0.
*/
int
pcie_get_max_completion_timeout(device_t dev)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
int cap;
cap = dinfo->cfg.pcie.pcie_location;
if (cap == 0)
return (0);
/*
* Functions using the 1.x spec use the default timeout range of
* 50 microseconds to 50 milliseconds. Functions that do not
* support programmable timeouts also use this range.
*/
if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 ||
(pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) &
PCIEM_CAP2_COMP_TIMO_RANGES) == 0)
return (50 * 1000);
switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) &
PCIEM_CTL2_COMP_TIMO_VAL) {
case PCIEM_CTL2_COMP_TIMO_100US:
return (100);
case PCIEM_CTL2_COMP_TIMO_10MS:
return (10 * 1000);
case PCIEM_CTL2_COMP_TIMO_55MS:
return (55 * 1000);
case PCIEM_CTL2_COMP_TIMO_210MS:
return (210 * 1000);
case PCIEM_CTL2_COMP_TIMO_900MS:
return (900 * 1000);
case PCIEM_CTL2_COMP_TIMO_3500MS:
return (3500 * 1000);
case PCIEM_CTL2_COMP_TIMO_13S:
return (13 * 1000 * 1000);
case PCIEM_CTL2_COMP_TIMO_64S:
return (64 * 1000 * 1000);
default:
return (50 * 1000);
}
}
/*
* Perform a Function Level Reset (FLR) on a device.
*
* This function first waits for any pending transactions to complete
* within the timeout specified by max_delay. If transactions are
* still pending, the function will return false without attempting a
* reset.
*
* If dev is not a PCI-express function or does not support FLR, this
* function returns false.
*
* Note that no registers are saved or restored. The caller is
* responsible for saving and restoring any registers including
* PCI-standard registers via pci_save_state() and
* pci_restore_state().
*/
bool
pcie_flr(device_t dev, u_int max_delay, bool force)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
uint16_t cmd, ctl;
int compl_delay;
int cap;
cap = dinfo->cfg.pcie.pcie_location;
if (cap == 0)
return (false);
if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR))
return (false);
/*
* Disable busmastering to prevent generation of new
* transactions while waiting for the device to go idle. If
* the idle timeout fails, the command register is restored
* which will re-enable busmastering.
*/
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2);
if (!pcie_wait_for_pending_transactions(dev, max_delay)) {
if (!force) {
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
return (false);
}
pci_printf(&dinfo->cfg,
"Resetting with transactions pending after %d ms\n",
max_delay);
/*
* Extend the post-FLR delay to cover the maximum
* Completion Timeout delay of anything in flight
* during the FLR delay. Enforce a minimum delay of
* at least 10ms.
*/
compl_delay = pcie_get_max_completion_timeout(dev) / 1000;
if (compl_delay < 10)
compl_delay = 10;
} else
compl_delay = 0;
/* Initiate the reset. */
ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl |
PCIEM_CTL_INITIATE_FLR, 2);
/* Wait for 100ms. */
pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK);
if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) &
PCIEM_STA_TRANSACTION_PND)
pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n");
return (true);
}
Create PCI_MATCH and pci_match_device Create a covenience function to match PCI device IDs. It's about 15 years overdue. Differential Revision: https://reviews.freebsd.org/D15999
2018-07-07 15:25:11 +00:00
Give new home to the comment from ppt_pci_reset(), explaining a nuance of power reset. Noted by: soralx@cydem.org Sponsored by: Mellanox Technologies MFC after: 12 days
2019-04-07 08:58:09 +00:00
/*
* Attempt a power-management reset by cycling the device in/out of D3
* state. PCI spec says we can only go into D3 state from D0 state.
* Transition from D[12] into D0 before going to D3 state.
*/
Implement resets for PCI buses and PCIe bridges. For PCI device (i.e. child of a PCI bus), reset tries FLR if implemented and worked, and falls to power reset otherwise. For PCIe bus (child of a PCIe bridge or root port), reset disables PCIe link and then re-trains it, performing what is known as link-level reset. Reviewed by: imp (previous version), jhb (previous version) Sponsored by: Mellanox Technologies MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D19646
2019-04-05 19:25:26 +00:00
int
pci_power_reset(device_t dev)
{
int ps;
ps = pci_get_powerstate(dev);
if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
pci_set_powerstate(dev, PCI_POWERSTATE_D3);
pci_set_powerstate(dev, ps);
return (0);
}
/*
* Try link drop and retrain of the downstream port of upstream
* switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must
* cause Conventional Hot reset of the device in the slot.
* Alternative, for PCIe, could be the secondary bus reset initiatied
* on the upstream switch PCIR_BRIDGECTL_1, bit 6.
*/
int
pcie_link_reset(device_t port, int pcie_location)
{
uint16_t v;
v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2);
v |= PCIEM_LINK_CTL_LINK_DIS;
pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
pause_sbt("pcier1", mstosbt(20), 0, 0);
v &= ~PCIEM_LINK_CTL_LINK_DIS;
v |= PCIEM_LINK_CTL_RETRAIN_LINK;
pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2);
pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */
v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2);
return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0);
}
static int
pci_reset_post(device_t dev, device_t child)
{
if (dev == device_get_parent(child))
pci_restore_state(child);
return (0);
}
static int
pci_reset_prepare(device_t dev, device_t child)
{
if (dev == device_get_parent(child))
pci_save_state(child);
return (0);
}
static int
pci_reset_child(device_t dev, device_t child, int flags)
{
int error;
if (dev == NULL || device_get_parent(child) != dev)
return (0);
if ((flags & DEVF_RESET_DETACH) != 0) {
error = device_get_state(child) == DS_ATTACHED ?
device_detach(child) : 0;
} else {
error = BUS_SUSPEND_CHILD(dev, child);
}
if (error == 0) {
if (!pcie_flr(child, 1000, false)) {
error = BUS_RESET_PREPARE(dev, child);
if (error == 0)
pci_power_reset(child);
BUS_RESET_POST(dev, child);
}
if ((flags & DEVF_RESET_DETACH) != 0)
device_probe_and_attach(child);
else
BUS_RESUME_CHILD(dev, child);
}
return (error);
}
Create PCI_MATCH and pci_match_device Create a covenience function to match PCI device IDs. It's about 15 years overdue. Differential Revision: https://reviews.freebsd.org/D15999
2018-07-07 15:25:11 +00:00
const struct pci_device_table *
pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt)
{
bool match;
uint16_t vendor, device, subvendor, subdevice, class, subclass, revid;
vendor = pci_get_vendor(child);
device = pci_get_device(child);
subvendor = pci_get_subvendor(child);
subdevice = pci_get_subdevice(child);
class = pci_get_class(child);
subclass = pci_get_subclass(child);
revid = pci_get_revid(child);
while (nelt-- > 0) {
match = true;
if (id->match_flag_vendor)
match &= vendor == id->vendor;
if (id->match_flag_device)
match &= device == id->device;
if (id->match_flag_subvendor)
match &= subvendor == id->subvendor;
if (id->match_flag_subdevice)
match &= subdevice == id->subdevice;
if (id->match_flag_class)
match &= class == id->class_id;
if (id->match_flag_subclass)
match &= subclass == id->subclass;
if (id->match_flag_revid)
match &= revid == id->revid;
if (match)
return (id);
id++;
}
return (NULL);
}
Rudimentary AER reading code for ddb(4). This is very primitive code to inspect the PCI error state and AER error state, dump the log and clear errors, from ddb. pci_print_faulted_dev() is made external to allow calling it from other places. It was called from NMI handler but this chunk is not included. Also there is a tunable-controlled code to clear AER on device attach, disabled by default. All this code was useful to me when I debugged ACPI_DMAR failures (not faults) long time ago. Reviewed by: cem, imp (previous version) Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D7813
2018-08-18 20:35:19 +00:00
static void
pci_print_faulted_dev_name(const struct pci_devinfo *dinfo)
{
const char *dev_name;
device_t dev;
dev = dinfo->cfg.dev;
printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus,
dinfo->cfg.slot, dinfo->cfg.func);
dev_name = device_get_name(dev);
if (dev_name != NULL)
printf(" (%s%d)", dev_name, device_get_unit(dev));
}
void
pci_print_faulted_dev(void)
{
struct pci_devinfo *dinfo;
device_t dev;
int aer, i;
uint32_t r1, r2;
uint16_t status;
STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
dev = dinfo->cfg.dev;
status = pci_read_config(dev, PCIR_STATUS, 2);
status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT |
PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT |
PCIM_STATUS_SERR | PCIM_STATUS_PERR;
if (status != 0) {
pci_print_faulted_dev_name(dinfo);
printf(" error 0x%04x\n", status);
}
if (dinfo->cfg.pcie.pcie_location != 0) {
status = pci_read_config(dev,
dinfo->cfg.pcie.pcie_location +
PCIER_DEVICE_STA, 2);
if ((status & (PCIEM_STA_CORRECTABLE_ERROR |
PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
PCIEM_STA_UNSUPPORTED_REQ)) != 0) {
pci_print_faulted_dev_name(dinfo);
printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n",
pci_read_config(dev,
dinfo->cfg.pcie.pcie_location +
PCIER_DEVICE_CTL, 2),
status);
}
}
if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
if (r1 != 0 || r2 != 0) {
pci_print_faulted_dev_name(dinfo);
printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n"
" COR 0x%08x Mask 0x%08x Ctl 0x%08x\n",
r1, pci_read_config(dev, aer +
PCIR_AER_UC_MASK, 4),
pci_read_config(dev, aer +
PCIR_AER_UC_SEVERITY, 4),
r2, pci_read_config(dev, aer +
PCIR_AER_COR_MASK, 4),
pci_read_config(dev, aer +
PCIR_AER_CAP_CONTROL, 4));
for (i = 0; i < 4; i++) {
r1 = pci_read_config(dev, aer +
PCIR_AER_HEADER_LOG + i * 4, 4);
printf(" HL%d: 0x%08x\n", i, r1);
}
}
}
}
}
#ifdef DDB
DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db)
{
pci_print_faulted_dev();
}
static void
db_clear_pcie_errors(const struct pci_devinfo *dinfo)
{
device_t dev;
int aer;
uint32_t r;
dev = dinfo->cfg.dev;
r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
PCIER_DEVICE_STA, 2);
pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
PCIER_DEVICE_STA, r, 2);
if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0)
return;
r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
if (r != 0)
pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
if (r != 0)
pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
}
DB_COMMAND(pci_clearerr, db_pci_clearerr)
{
struct pci_devinfo *dinfo;
device_t dev;
uint16_t status, status1;
STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
dev = dinfo->cfg.dev;
status1 = status = pci_read_config(dev, PCIR_STATUS, 2);
status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT |
PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT |
PCIM_STATUS_SERR | PCIM_STATUS_PERR;
if (status1 != 0) {
status &= ~status1;
pci_write_config(dev, PCIR_STATUS, status, 2);
}
if (dinfo->cfg.pcie.pcie_location != 0)
db_clear_pcie_errors(dinfo);
}
}
#endif
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