Commit Graph

108 Commits

Author SHA1 Message Date
Ulrich Spörlein
ef8a3e5cf2 mdoc: remove literal tabs where they don't belong 2010-06-08 16:48:59 +00:00
Fabien Thomas
d66caf62a2 Fix memory leak on error.
Found with:	Coverity Prevent(tm)
MFC after:	1 month
2010-06-05 23:00:02 +00:00
Ulrich Spörlein
e10c1be450 mdoc cleanup
Garbage collect unused sections, macros and arguments. Fix prologue and
remove empty lines.

Found by: mdocml
2010-06-02 10:20:23 +00:00
Ulrich Spörlein
b27f498819 mdoc: Use mdoc macro for the (R) symbol
While here, also drop the unneeded quotes
2010-05-27 13:56:33 +00:00
Ulrich Spörlein
0afc94c17a mdoc: move CAVEATS, BUGS and SECURITY CONSIDERATIONS sections to the
bottom of the manpages and order them consistently.

GNU groff doesn't care about the ordering, and doesn't even mention
CAVEATS and SECURITY CONSIDERATIONS as common sections and where to put
them.

Found by:	mdocml lint run
Reviewed by:	ru
2010-05-13 12:07:55 +00:00
Ryan Stone
aa1b887b41 When configuring hwpmc to use the EXT_SNOOP event, only send a default cachestate qualifier on the Atom processor. Other Intel processors do not accept a cachestate qualifier and currently hwpmc will return EINVAL if you try to use the EXT_SNOOP event on those processors
Approved by:	jkoshy (mentor)
MFC after:	2 weeks
2010-05-01 21:59:06 +00:00
Ulrich Spörlein
aa12cea2cc mdoc: order prologue macros consistently by Dd/Dt/Os
Although groff_mdoc(7) gives another impression, this is the ordering
most widely used and also required by mdocml/mandoc.

Reviewed by:	ru
Approved by:	philip, ed (mentors)
2010-04-14 19:08:06 +00:00
Fabien Thomas
1fa7f10bac - Support for uncore counting events: one fixed PMC with the uncore
domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
  There is some removed events in the documentation, they have been
  kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.

Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
Rui Paulo
ed11e09daf Finish the much belated Intel XScale hwpmc(4) man page. 2010-03-23 11:33:08 +00:00
George V. Neville-Neil
660df75e8b Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.
Add macros for properly accessing coprocessor 0 registers that
support performance counters.

Reviewed by:	jkoshy rpaulo fabien imp
MFC after:	1 month
2010-03-03 15:05:58 +00:00
Joseph Koshy
bc315bbd5a Bug fix: add a missing initializer.
Submitted by:	Luca Pizzamiglio <luca.pizzamiglio at gmail dot com>
PR:		i386/142742
2010-01-12 17:03:55 +00:00
Ed Schouten
daaf575910 Build lib/ with WARNS=6 by default.
Similar to libexec/, do the same with lib/. Make WARNS=6 the norm and
lower it when needed.

I'm setting WARNS?=0 for secure/. It seems secure/ includes the
Makefile.inc provided by lib/. I'm not going to touch that directory.
Most of the code there is contributed anyway.
2010-01-02 09:58:07 +00:00
Rui Paulo
0ce207d2af Intel XScale hwpmc(4) support.
This brings hwpmc(4) support for 2nd and 3rd generation XScale cores.
Right now it's enabled by default to make sure we test this a bit.
When the time comes it can be disabled by default.
Tested on Gateworks boards.

A man page is coming.

Obtained from:	//depot/user/rpaulo/xscalepmc/...
2009-12-23 23:16:54 +00:00
Christian Brueffer
cf6c5eebe7 Use our canonical .Dd format.
Submitted by:	Ulrich Spoerlein
2009-11-02 12:35:38 +00:00
Joseph Koshy
791f5d5ba2 Not all Intel Core (TM) CPUs implement PMC_CLASS_IAF fixed-function
counters.  For such CPUs, use an alternate mapping of convenience
names to events supported by PMC_CLASS_IAP programmable counters.

Testing and review by:	fabient
2009-10-24 04:11:40 +00:00
Rui Paulo
45c6072249 Install x86 related man pages on x86 systems only.
Reviewed by:	jkoshy
2009-10-04 10:54:20 +00:00
Joseph Koshy
dd1259dafb Use a more appropriate choice of words.
Submitted by:	danfe
2009-08-23 14:48:25 +00:00
Joseph Koshy
ef58215868 Use US spellings, fix typos. 2009-08-23 07:32:30 +00:00
Joseph Koshy
cbd3e3c8ad Fix typos. 2009-08-23 07:31:10 +00:00
Joseph Koshy
445f22cfe7 Fix a typo. 2009-08-23 07:30:12 +00:00
Joseph Koshy
a2cd12e7a0 Fix typos, use American English spellings. 2009-08-23 07:29:34 +00:00
Joseph Koshy
7dfdb5c882 Fix typos. 2009-08-23 07:24:39 +00:00
Joseph Koshy
abb0a58ed9 Correct typos. 2009-08-23 06:22:31 +00:00
Joseph Koshy
5dcb8c704e Correct grammar. 2009-08-23 06:19:02 +00:00
Joseph Koshy
b53a052da8 Fix a typo.
Reported by:	John McCullough <jmccullo at cs.ucsd.edu>
2009-08-23 05:49:12 +00:00
Joseph Koshy
f20a61ffe6 Fix typos.
Reported by:	Harald Servat <redcrash at gmail dot com>
2009-08-23 05:47:33 +00:00
Joseph Koshy
5c9306fd41 Document the fact that some Core2 family CPUs lack fixed-function counters. 2009-06-09 06:36:29 +00:00
Joseph Koshy
b47ea38e01 Fix parsing of Core2 event qualifiers.
Submitted by:	Nikola K <laladelausanne at gmail dot com>
2009-06-09 06:34:48 +00:00
Fabien Thomas
c2a3620fc3 Allow compile from c++ for libpmc
Approved by:	jkoshy (mentor)
MFC after:	3 days
2009-03-24 22:35:05 +00:00
Jeff Roberson
597979c4b7 - Add support for nehalem/corei7 cpus. This supports all of the core
counters defined in the reference manual.  It does not support the
   'uncore' events.

Reviewed by:	jkoshy
Sponsored by:	Nokia
2009-01-27 07:29:37 +00:00
Joseph Koshy
3c83ff13e9 Document processor errata that affect performance measurement. 2008-12-08 12:28:48 +00:00
Joseph Koshy
b4d091f3a4 Fixes for Core2 Extreme support.
Submitted by:	 "Artem Belevich" <artemb at gmail dot com>
2008-12-03 17:30:36 +00:00
Joseph Koshy
d95afe050e Update description of an event.
Submitted by:	"Verplanke, Edwin" <edwin dot verplanke at intel dot com>
2008-11-27 09:21:37 +00:00
Joseph Koshy
0cfab8ddc1 - Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo
and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and
  model 0x1C (Atom).

  In these CPUs, the actual numbers, kinds and widths of PMCs present
  need to queried at run time.  Support for specific "architectural"
  events also needs to be queried at run time.

  Model 0xE CPUs support programmable PMCs, subsequent CPUs
  additionally support "fixed-function" counters.

- Use event names that are close to vendor documentation, taking in
  account that:
  - events with identical semantics on two or more CPUs in this family
    can have differing names in vendor documentation,
  - identical vendor event names may map to differing events across
    CPUs,
  - each type of CPU supports a different subset of measurable
    events.

  Fixed-function and programmable counters both use the same vendor
  names for events.  The use of a class name prefix ("iaf-" or
  "iap-" respectively) permits these to be distinguished.

- In libpmc, refactor pmc_name_of_event() into a public interface
  and an internal helper function, for use by log handling code.

- Minor code tweaks: staticize a global, freshen a few comments.

Tested by:	gnn
2008-11-27 09:00:47 +00:00
Joseph Koshy
d5ec7b69ec Fix buglets. 2008-11-26 03:48:20 +00:00
Joseph Koshy
ebf07c3e19 Correction: these PMCs do not support a "umask" modifier. 2008-11-24 08:14:01 +00:00
Joseph Koshy
0f7668cbae - Document the rules used to determine when spellings of events
are equivalent.
- Reorder text to make the manual page more coherent.
2008-11-24 08:11:33 +00:00
Joseph Koshy
944e20faf5 - Document the class name prefix for these PMCs.
- Document the "anythread" qualifier, available on Atom CPUs.
- Add examples.
2008-11-15 11:34:30 +00:00
Joseph Koshy
0b4dcce33e Tweak -mdoc usage. 2008-11-13 16:32:20 +00:00
Joseph Koshy
9275b7fce8 Document UMASK values, fix errors. 2008-11-13 10:40:13 +00:00
Joseph Koshy
f21fb297ad Fix typos, document UMASK values. 2008-11-13 10:21:56 +00:00
Joseph Koshy
63653d3956 Remove duplicates, fix errors and document UMASK values. 2008-11-13 09:53:53 +00:00
Joseph Koshy
6c292c4db6 Document the alternate event names supported for "architectural" PMC events. 2008-11-12 17:43:37 +00:00
Joseph Koshy
06209c4453 Use spellings that are close to vendor documentation. 2008-11-12 17:38:23 +00:00
Joseph Koshy
789140c0e7 - Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to
reduce ABI disruptions when new cpu types and new PMC events are added
  in the future.
- Support alternate spellings for PMC events.  Derive the canonical
  spelling of an event name from its enumeration name in 'enum pmc_event'.
- Provide a way for users to disambiguate between identically named events
  supported by multiple classes of PMCs in a CPU.
- Change libpmc's machine-dependent event specifier parsing code to
  better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
Joseph Koshy
8fb796642a Correct a typo. 2008-10-06 10:34:44 +00:00
Joseph Koshy
243e1539f3 - Add cross-references.
- Tweak -mdoc use.
2008-10-04 12:54:25 +00:00
Joseph Koshy
2eca5e0f76 Add cross-references. 2008-10-04 12:53:08 +00:00
Joseph Koshy
8c3af4f2c2 Cross-reference new manual pages. 2008-10-04 12:44:05 +00:00
Joseph Koshy
72cf78b859 - Cross-reference new manual pages.
- Spell new PMC class names correctly.
2008-10-04 12:35:02 +00:00