Commit Graph

68 Commits

Author SHA1 Message Date
Ruslan Bukin
57b28934e9 Add receiver timeout interrupt enable bit implemented in some
system on chips.

Submitted by:	kan
Sponsored by:	DARPA, AFRL
2016-11-19 16:00:05 +00:00
Ruslan Bukin
b192bae67e Add support for UART found in the Ingenic XBurst system on chips.
These CPUs has non-standard UART enable bit hidden in the UART FIFO
Control Register.

Sponsored by:	DARPA, AFRL
2016-11-17 14:41:22 +00:00
Pedro F. Giffuni
453130d9bf sys/dev: minor spelling fixes.
Most affect comments, very few have user-visible effects.
2016-05-03 03:41:25 +00:00
Marius Strobl
3deebd539b - Add support for Advantech PCI-1602 Rev. B1 and PCI-1603 cards. [1]
- Add a description of Advantech PCI-1602 Rev. A boards. [1]
- Properly set up REG_ACR also for PCI-1602 Rev. A based on what the
  Advantech-supplied Linux driver does.
- Additionally use the macros of <dev/ic/ns16550.h> to replace existing
  magic values and get rid of trivial comments.
- Fix the style of some comments.

PR:		205359 [1]
Submitted by:	Jan Mikkelsen (original patch) [1]
2016-01-10 18:11:23 +00:00
Warner Losh
80bd9c9682 This should have been GC'd 6 years ago when ar(4) was removed. 2015-02-17 05:07:38 +00:00
Zbigniew Bodek
49e368ac48 Wait for DesignWare UART transfers completion before accessing line control
When using DW UART with BUSY detection it is necessary to wait
until all serial transfers are finished before manipulating the
line control. LCR will not be affected when UART is busy.
In addition, if Divisor Latch Access Bit is being set in order to
modify UART divisors:
1. We will get BUSY interrupt if interrupts are enabled.
2. Because LCR will not be affected the THR and (even worse) IER
   contents will be corrupted. This will lead to console hang.

Approved by:	cognet (mentor)
2013-10-26 17:24:59 +00:00
Ganbold Tsagaankhuu
ac4adddf04 Add support for A10 uart.
A10 uart is derived from Synopsys DesignWare uart and requires
to read Uart Status Register when IIR_BUSY has detected.
Also this change includes FDT check, where it checks device
specific properties defined in dts and sets the busy_detect variable.
broken_txfifo is also needed to be set in order to make it work for
A10 uart case.

Reviewed by: marcel@
Approved by: gonzo@
2013-03-01 01:42:31 +00:00
Warner Losh
18f323353c Merge from projects/mips to head by hand:
Defintions for cavium uart (do they belong here?)
2010-01-11 04:13:06 +00:00
Sam Leffler
04ddfac339 add %b formats for various registers 2009-06-21 19:17:22 +00:00
Yoshihiro Takahashi
ebd2b74476 - Cleanup i8251 related defines.
- Move i8255 related defines into a separate file.
2008-09-07 04:35:04 +00:00
Yoshihiro Takahashi
5798cf97e9 unifdef PC98 2008-08-29 12:25:58 +00:00
Rafal Jaworowski
e1ef781113 Support for Freescale QUad Integrated Communications Controller.
The QUICC engine is found on various Freescale parts including MPC85xx, and
provides multiple generic time-division serial channel resources, which are in
turn muxed/demuxed by the Serial Communications Controller (SCC).

Along with core QUICC/SCC functionality a uart(4)-compliant device driver is
provided which allows for serial ports over QUICC/SCC.

Approved by:	cognet (mentor)
Obtained from:	Juniper
MFp4:		e500
2008-03-03 18:20:17 +00:00
Jung-uk Kim
0da90eb878 Fix style nits. No md5 changes in .o's. ;-) 2006-09-08 21:46:01 +00:00
Jung-uk Kim
50d99d1a52 Enhanced floppy controllers have Data Rate Select Register (DSR) at 0x3f4.
Use it to reset controller and to select data rate.  According to Intel
80277AA datasheet, software reset behaves the same as DOR reset except
that it is self clearing.  National Semiconductor PC8477B datasheet says
the same.  As a side effect, we no longer use Configuration Control
Register (CCR) at 0x3f7 for these controllers, which is often missing
in modern hardware.
2006-07-06 21:12:18 +00:00
Benno Rice
58957d8717 Allow uart(4)'s ns8250 driver to work with devices whose regshift is > 0.
- Rename REG_DL to REG_DLL and REG_DLH.
- Always treat DLL and DLH as two separate 8-bit registers instead of one
  16-bit register.

Additionally, remove the probe for the high 4 bits of IER being 0 and don't
assume we can always read/write 0 to/from those bits.

These changes allow uart(4) to drive the UARTs on the Intel XScale PXA255.

Reviewed by:	marcel
2006-05-23 00:41:12 +00:00
Marcel Moolenaar
1ba1685b25 MFp4:
Add CHAN_A & CHAN_B for channel register offsets.
While here, fix a comment.
2006-02-24 02:03:35 +00:00
Peter Grehan
e2b03d4d48 Register definitions for the ancient via6522. This 20+ year-old chip
still exists as a cell in the Macio asic on Apples, and is used to communicate
through the shift register with the external PMU microcontroller.
2005-12-02 22:36:14 +00:00
Gleb Smirnoff
21314694fb Typo.
PR:		misc/87679
Submitted by:	Alan Amesbury <amesbury umn.edu>
2005-10-23 09:05:51 +00:00
Yoshihiro Takahashi
dfe1941a9c cosmetic change. 2005-05-14 10:26:31 +00:00
Yoshihiro Takahashi
b22bf66063 - Move bus dependent defines to {isa,cbus}_dmareg.h.
- Use isa/isareg.h rather than <arch>/isa/isa.h.

Tested on: i386, pc98
2005-05-14 10:14:56 +00:00
Yoshihiro Takahashi
24072ca35b - Move timerreg.h to <arch>/include and split i8253 specific defines into
i8253reg.h, and add some defines to control a speaker.
- Move PPI related defines from i386/isa/spkr.c into ppireg.h and use them.
- Move IO_{PPI,TIMER} defines into ppireg.h and timerreg.h respectively.
- Use isa/isareg.h rather than <arch>/isa/isa.h.

Tested on: i386, pc98
2005-05-14 09:10:02 +00:00
Poul-Henning Kamp
0c3c54da63 Since we are quite unlikely to ever face another platform which
uses the i8237 without trying to emulate the PC architecture move
the register definitions for the i8237 chip into the central include
file for the chip, except for the PC98 case which is magic.

Add new isa_dmatc() function which tells us as cheaply as possible
if the terminal count has been reached for a given channel.
2005-02-06 13:46:39 +00:00
Warner Losh
098ca2bda9 Start each of the license/copyright comments with /*-, minor shuffle of lines 2005-01-06 01:43:34 +00:00
Marcel Moolenaar
43f0d5705e This file was repocopied from sys/dev/uart/uart_dev_z8530.h. 2004-11-21 01:34:15 +00:00
Marcel Moolenaar
caf45b058e This file was repocopied from sys/dev/uart/uart_dev_sab82532.h. 2004-11-21 01:33:39 +00:00
Marcel Moolenaar
4f5d62fbc6 o Remove the com_thr, com_rhr, com_isr and com_lctl defines. They are
not used and aliases for other defines.
o  Add REG_DATA as an alias for com_data. Likewise for other register
   defines.
o  Add LCR_SBREAK and make CFCR_SBREAK an alias for it. Likewise for
   the other LCR register bits that are known with the CFCR prefix.
o  Add MCR_IE and make MCR_IENABLE an alias for it.
o  Add LSR_TEMT and make LSR_TSRE an alias for it.
o  Add LSR_THRE and make LSR_TXRDY as alias for it.
o  Add FCR_ENABLE and make FIFO_ENABLE as alias for it. Likewise for
   the other FCR register bits that are known with the FIFO prefix.
o  Add EFR_CTS and make EFR_AUTOCTS an alias for it.
o  Add EFR_RTS and make EFR_AUTORTS an alias for it.

This is a first step in cleaning up the definitions in this file.
2004-11-20 23:19:42 +00:00
Warner Losh
f36cfd49ad Remove advertising clause from University of California Regent's
license, per letter dated July 22, 1999 and email from Peter Wemm,
Alan Cox and Robert Watson.

Approved by: core, peter, alc, rwatson
2004-04-07 20:46:16 +00:00
John Baldwin
b733b2545b Add a header for the i8259A register definitions. This is based on
additions to sys/amd64/isa/icu.h from PIIX4 and other datasheets.  I
tweaked a few comments based on the NetBSD header of the same name when I
merged the constants to sys/i386/isa/icu.h, but the vast majority of this
file was created independently by Peter and not taken from any existing
files.

Submitted by:	peter
2004-01-06 18:59:37 +00:00
Bruce Evans
efcfe95173 Added definitions of most of the interesting 16950 register numbers
and some of their bits (i.e., fifo trigger levels, frequency multipliers
and divisors, and bits to select the registers for these).  This
attempts to completely describe the 16950's complicated register selects
for 16950-specific registers only.
2003-09-16 14:21:17 +00:00
Bruce Evans
fec27f507c Added definitions for some 16650 features (mostly misfeatures). This
completes defining the 16650 register numbers but not all of their bits.
2003-09-16 14:08:54 +00:00
Bruce Evans
2b843bc94b Fixed a minor error in the description of the EFR and a major error in
the description of the data latch registers (they were described as
readonly).

Added some better and worse aliases for standard registers, mostly taken
from the 16950 data sheet.  Define deprecated aliases in terms of the
preferred one.

Don't define com_efr in terms of com_fifo.  It is unrelated (in a
different bank).
2003-09-16 13:52:01 +00:00
Bruce Evans
74814b322a Sorted register numbers together with the correspoding register bits.
Merged comments to match (put them at the right of the #defines instead
of duplicating them).

Sorted the resulting sections on UART type and register bank.  Added a
comment for each bank.
2003-09-16 11:54:29 +00:00
Bruce Evans
86fe87393a Moved the definitions of the bits in the ns*50 registers from sioreg.h
to ns16550.h.  The organization of these files was sort of backwards.
The bits in the registers have no driver or bus dependencies but they
but the offsets of the registers in bus space are very bus-dependent.
However, it does no harm to keep the definitions of the register offsets
in ns16550.h provided they are thought of as internal ns*50 offsets.
2003-09-16 08:08:08 +00:00
Marcel Moolenaar
27d5dc189c The uart(4) driver is an universal driver for various UART hardware.
It improves on sio(4) in the following areas:
o  Fully newbusified to allow for memory mapped I/O. This is a must
   for ia64 and sparc64,
o  Machine dependent code to take full advantage of machine and firm-
   ware specific ways to define serial consoles and/or debug ports.
o  Hardware abstraction layer to allow the driver to be used with
   various UARTs, such as the well-known ns8250 family of UARTs, the
   Siemens sab82532 or the Zilog Z8530. This is especially important
   for pc98 and sparc64 where it's common to have different UARTs,
o  The notion of system devices to unkludge low-level consoles and
   remote gdb ports and provides the mechanics necessary to support
   the keyboard on sparc64 (which is UART based).
o  The notion of a kernel interface so that a UART can be tied to
   something other than the well-known TTY interface. This is needed
   on sparc64 to present the user with a device and ioctl handling
   suitable for a keyboard, but also allows us to cleanly hide an
   UART when used as a debug port.

Following is a list of features and bugs/flaws specific to the ns8250
family of UARTs as compared to their support in sio(4):
o  The uart(4) driver determines the FIFO size and automaticly takes
   advantages of larger FIFOs and/or additional features. Note that
   since I don't have sufficient access to 16[679]5x UARTs, hardware
   flow control has not been enabled. This is almost trivial to do,
   provided one can test. The downside of this is that broken UARTs
   are more likely to not work correctly with uart(4). The need for
   tunables or knobs may be large enough to warrant their creation.
o  The uart(4) driver does not share the same bumpy history as sio(4)
   and will therefore not provide the necessary hooks, tweaks, quirks
   or work-arounds to deal with once common hardware. To that extend,
   uart(4) supports a subset of the UARTs that sio(4) supports. The
   question before us is whether the subset is sufficient for current
   hardware.
o  There is no support for multiport UARTs in uart(4). The decision
   behind this is that uart(4) deals with one EIA RS232-C interface.
   Packaging of multiple interfaces in a single chip or on a single
   expansion board is beyond the scope of uart(4) and is now mostly
   left for puc(4) to deal with. Lack of hardware made it impossible
   to actually implement such a dependency other than is present for
   the dual channel SAB82532 and Z8350 SCCs.

The current list of missing features is:
o  No configuration capabilities. A set of tunables and sysctls is
   being worked out. There are likely not going to be any or much
   compile-time knobs. Such configuration does not fit well with
   current hardware.
o  No support for the PPS API. This is partly dependent on the
   ability to configure uart(4) and partly dependent on having
   sufficient information to implement it properly.

As usual, the manpage is present but lacks the attention the
software has gotten.
2003-09-06 23:13:47 +00:00
Matthew N. Dodd
0e91b7d532 - Clean up function calling conventions.
- Be consistent about what we call our softc.
- Minor formatting.
- Add some register definitions gleaned from NetBSD/Linux.
2003-03-28 06:27:08 +00:00
Poul-Henning Kamp
c8423e9702 Move the com_scr register address definition over with the other seven.
Approved by:	bde
2002-09-22 08:51:31 +00:00
Joerg Wunsch
94896f7b05 Oops, forgot to commit one file in the fd driver mega update. Here it
is, some more constants for NE765 & Co.

Pointed out by: silby, Dave Cornejo <dave@dogwood.com>
2001-12-16 07:52:13 +00:00
Yoshihiro Takahashi
38b70454e3 Moved the wd33c93 specific file to sys/dev/ic. 2001-06-14 11:05:48 +00:00
Yoshihiro Takahashi
50cece92e1 Move the files from i386/isa/ic/ to dev/ic/. 2001-06-10 04:28:39 +00:00
Yoshihiro Takahashi
94a503c92d Added ESP98 specific register (merged from i386/isa/ic/esp.h). 2001-06-10 04:20:37 +00:00
Yoshihiro Takahashi
da0f982b48 Removed unneeded pc98 code (merged from i386/isa/ic/ns16550.h). 2001-06-10 04:18:19 +00:00
Peter Wemm
365c5db0a7 Add $FreeBSD$ 2000-05-01 20:32:07 +00:00
Peter Wemm
c3aac50f28 $Id$ -> $FreeBSD$ 1999-08-28 01:08:13 +00:00
Bruce Evans
c151de316a Fixed 10 out of 40 lines of -Wcast-qual warnings/errors. 3 lines were
for old confusion of `volatile char *' with `volatile caddr_t'.  7 lines
were for not being careful about aligning pointers to volatiles.
1999-05-13 12:21:41 +00:00
Bruce Evans
657365cdd7 Implemented sending of BREAKs. This is quite complicated because the
hardware is interrupt-driven to a fault and sending a BREAK requires
mode switching.  Always running in the BREAK-capable mode as in PR 8318
would double the overhead for sending \0's.

Reminded by:	PR 8318
1998-12-17 17:40:13 +00:00
Bruce Evans
b97fc94873 Use [u]intptr_t instead of [unsigned] long to convert and/or represent
pointers.

This finishes fixing conversions between pointers and integers of
possibly different sizes in GENERIC.
1998-08-10 17:21:49 +00:00
Bruce Evans
c1087c1324 Support compiling with `gcc -ansi'. 1998-04-15 17:47:40 +00:00
Tor Egge
d66c374f58 Enable the FIFO on enhanced floppy controllers. This reduces the
number of dma overruns/underruns for systems under heavy dma load.
As a side effect, broken enhanced floppy controllers that sometimes
don't detect dma overruns/underruns will give less errors.

Reviewed by:	j@uriah.heep.sax.de (J Wunsch)
1997-09-17 20:16:17 +00:00
Peter Wemm
6875d25465 Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not
ready for it yet.
1997-02-22 09:48:43 +00:00
Jordan K. Hubbard
1130b656e5 Make the long-awaited change from $Id$ to $FreeBSD$
This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.

Boy, I'm glad we're not using sup anymore.  This update would have been
insane otherwise.
1997-01-14 07:20:47 +00:00