Introduce common library for IDPF (Infrastructure Data
Path Function) PMD.
Add base code and OS specific implementation first.
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
This commit adds verification option for elliptic curve
points when used along ECDH algorithm.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
All pointers passed to functions that are not supposed
to have its data changed should be marked as constant.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
Add support to generate ipad and opad for MD5.
Skip the call to additional command WRITE_SA during SA creation.
Instead use the software defined function to generate opad and ipad.
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Read slice configuration of QAT capabilities.
This will allow to recognize if specific hw function
is available on particular generation of device.
Added function pointers for each QAT generations.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
The variable mlx5_config may be used by other mlx5 drivers
and should be always initialized.
By moving its initialization (with configuration file generation),
it is made consistent for Linux and Windows builds.
And the check of mlx5_config in net/mlx5 is moved at the top of
net/mlx5/hws/meson.build so HWS requirements are in the right context.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Tested-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Alex Vesker <valex@nvidia.com>
As per recent change in Linux-5.4.x AF driver, mailbox is updated to
configure mapping between channel and BPID.
Due to mbox mismatch, PFC was broken. Patch syncs mailbox definition
for the same. Also fixes the PFC configuration issues.
Fixes: ff1400aa9d ("net/cnxk: add receive channel backpressure for SDP")
Cc: stable@dpdk.org
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Sync nix_hw_info structure with kernel.
Maintain default RR_QUANTUM for VF TL2 same as kernel to make
equal distribution among all VFs.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Each TX schedule config mail box supports a maximum 20 register updates.
This patch will send node weight updates in multiple mailboxes when
TM is created with more than 20 scheduler nodes.
Fixes: 464c9f9193 ("common/cnxk: support NIX TM dynamic update")
Cc: stable@dpdk.org
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
RQ mask config needs to enable SPB_ENA in order for zero for
being able to override it with meta AURA.
Also fix flow control config to catch invalid rxchan config
errors.
Fixes: ddf955d391 ("common/cnxk: support CPT second pass")
Fixes: da57d4589a ("common/cnxk: support NIX flow control")
Cc: stable@dpdk.org
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
In outbound inline case, use NIX Tx offset instead of
NIX Tx address for cn10kb as per new instruction format.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to override soft expiry poll frequency via devargs.
Also provide helper API to indicate reassembly support on a chip
and documentation for devargs that are already present.
Fixes: 780b9c8924 ("net/cnxk: support zero AURA for inline meta")
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Set maximum frame size on SDP NIX side to 16KB for CN93 A0 and B0,
CNF95N A0 and CNF95O A0 SOC type. Rest of the SoCs SDP NIX to 64KB.
Signed-off-by: Sathesh Edara <sedara@marvell.com>
The common MLX5 probe function parses first the devargs and save them in
a dictionary.
It gets structure called "devargs" as a member of EAL device containing
all needed information.
When "devargs" structure is invalid, the function avoids parsing it.
However, when it valid but its field "args" is invalid, the function
tries to parse it and dereference to NULL pointer.
This patch adds check to avoid this NULL dereferencing.
Fixes: a729d2f093 ("common/mlx5: refactor devargs management")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit adds HW steering counter action support.
The pool mechanism is the basic data structure for the HW steering
counter.
The HW steering's counter pool is based on the rte_ring of zero-copy
variation.
There are two global rte_rings:
1. free_list:
Store the counters indexes, which are ready for use.
2. wait_reset_list:
Store the counters indexes, which are just freed from the user and
need to query the hardware counter to get the reset value before
this counter can be reused again.
The counter pool also supports cache per HW steering's queues, which are
also based on the rte_ring of zero-copy variation.
The cache can be configured in size, preload, threshold, and fetch size,
they are all exposed via device args.
The main operations of the counter pool are as follows:
- Get one counter from the pool:
1. The user call _get_* API.
2. If the cache is enabled, dequeue one counter index from the local
cache:
2. A: if the dequeued one from the local cache is still in reset
status (counter's query_gen_when_free is equal to pool's query
gen):
I. Flush all counters in the local cache back to global
wait_reset_list.
II. Fetch _fetch_sz_ counters into the cache from the global
free list.
III. Fetch one counter from the cache.
3. If the cache is empty, fetch _fetch_sz_ counters from the global
free list into the cache and fetch one counter from the cache.
- Free one counter into the pool:
1. The user calls _put_* API.
2. Put the counter into the local cache.
3. If the local cache is full:
A: Write back all counters above _threshold_ into the global
wait_reset_list.
B: Also, write back this counter into the global wait_reset_list.
When the local cache is disabled, _get_/_put_ cache directly from/into
global list.
Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This patch introduces support for modify_field rte_flow actions in HWS
mode that includes:
- Ingress and egress domains,
- SET and ADD operations,
- usage of arbitrary bit offsets and widths for packet and metadata
fields.
This is implemented in two phases:
1. On flow table creation the hardware commands are generated, based
on rte_flow action templates, and stored alongside action template.
2. On flow rule creation/queueing the hardware commands are updated with
values provided by the user. Any masks over immediate values, provided
in action templates, are applied to these values before enqueueing rules
for creation.
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
HWS matcher resides under the table object, each table can
have multiple chained matches with different attributes.
Each matcher represents a combination of match and action templates,
and can contain multiple configurations based on the templates.
Packets are steered from the table to the matcher and from there to
other objects.
The matcher allows efficient HW packet field matching and action
execution based on the configuration done to it.
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
This adds the command layer which is used to communicate with
the FW, to query capabilities and allocate FW resources needed
for HWS.
Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Signed-off-by: Alex Vesker <valex@nvidia.com>
Add missing glue support for the HWS mlx5dr layer.
The new glue functions are needed for mlx5dv to create
matcher and action, which are used as the kernel root
table as well as for capabilities query like device
name and port info.
Signed-off-by: Alex Vesker <valex@nvidia.com>
Add new fields to flow table capabilities to query the capabilities to
set, add, and copy to REG_C_x.
The set capability is queried and saved for future usage.
Signed-off-by: Bing Zhao <bingz@nvidia.com>
This patchset bumps the minimum meson version from 0.49.2 to 0.53.2.
Ideally, the minimum version should be 0.53 without a point release, but
some DPDK builds (mingw) are broken with 0.53.0 due to issue[1], fixed
by commit[2] in 0.53.1. Therefore we use the latest point release from
0.53 branch i.e. 0.53.2.
Some new features of interest which can now be used in DPDK with this
new minimum meson version:
* can do header-file checks directly inside find_library calls, rather
than needing a separate check.[v0.50].
* can pass multiple cross-files at the same time when cross-compiling
[v0.51].
* "alias_target" function, to allow use to give better/shorter names
for particular build objects [v0.52].
* auto-generation of clang-format [v0.50] and clang-tidy[v0.52] targets
when those tools are present and config dotfiles are present.
Similarly ctags and cscope are added as targets when those tools are
present [v0.53]
* meson module for filesystem operations, so meson can now check for the
presence of particular files or directories [v0.53].
* "summary" function to provide a configuration summary at the end of
the meson run [v0.53].
Plus many other features. See [3] for full details of each version.
[1] https://github.com/mesonbuild/meson/issues/6442
[2] https://github.com/mesonbuild/meson/pull/6457/commits/8e7a7c36b579
[3] https://mesonbuild.com/Release-notes.html
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: David Marchand <david.marchand@redhat.com>
The `mp_cb_registered` flag shared between all processes
was used to ensure that for any IB device (MLX5 common device)
mempool event callback was registered only once
and mempools that had been existing before the device start
were traversed only once to register them.
Since mempool callback registrations have become process-private,
callback registration must be done by every process.
The flag can no longer reflect the state for any single process.
Replace it with a registration counter to track
when no more callbacks are registered for the device in any process.
It is sufficient to only register pre-existing mempools
in the primary process because it is the one that starts the device.
Fixes: 690b2a88c2 ("common/mlx5: add mempool registration facilities")
Cc: stable@dpdk.org
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Add fixed point multiplication for EC curve in CNXK.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Enabled the flag pmd_supports_disable_iova_as_pa in cnxk driver build
files as they work with IOVA as VA. Updated cn9k and cn10k soc build
configurations to disable the IOVA as PA build by default.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
This patch adds new HCA capability related to hairpin RQs. This new
capability, hairpin_data_buffer_locked, indicates whether HCA supports
locking data buffer of hairpin RQ in ICMC (Interconnect Context Memory
Cache).
Struct used to define RQ configuration (RQ context) is extended with
hairpin_data_buffer_type field, which configures data buffer for hairpin
RQ. It can take the following values:
- MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER - hairpin
RQ's data buffer is stored in unlocked memory in ICMC.
- MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER - hairpin
RQ's data buffer is stored in locked memory in ICMC.
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This patch extends HCA_CAP and SQ Context structs available in PRM. This
fields allow checking if NIC supports storing hairpin SQ's WQ buffer in
host memory and configuring such memory placement.
HCA capabilities are extended with the following fields:
- hairpin_sq_wq_in_host_mem - If set, then NIC supports using host
memory as a backing storage for hairpin SQ's WQ buffer.
- hairpin_sq_wqe_bb_size - Indicates the required size of SQ WQE basic
block.
SQ Context is extended with hairpin_wq_buffer_type which informs
NIC where SQ's WQ buffer will be stored. This field can take the
following values:
- MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER - WQ buffer will be
stored in unlocked device memory.
- MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY - WQ buffer will be stored
in host memory. Buffer is provided by PMD.
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Change cidx and pidx definition to mean used queue and avail
queue index respectively.
Signed-off-by: Abhimanyu Saini <absaini@amd.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Pickup new FW interface definitions for avail and used indexes.
Signed-off-by: Abhimanyu Saini <absaini@amd.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
The used/avail queue indexes are not bound by queue size,
because HW calculates descriptor entry index by performing
a simple modulo between queue index and queue_size.
So, do not check initial used and avail queue indexes
against queue size because it is possible for these
indexes to be greater than queue size in the
following cases:
1) The queue is created to be migrated into, or
2) The client issues a qstop/qstart after running datapath
Fixes: 4dda72dbde ("common/sfc_efx/base: add base virtio support for vDPA")
Cc: stable@dpdk.org
Signed-off-by: Abhimanyu Saini <absaini@amd.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Added support for CN10K SoC DMA engine to dmadev.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Such information is useful to client drivers which deal with
large Rx pool buffers (16-bit wide data count) and thus need
to avoid overflow when setting EF10's 14-bit wide data count.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Maximum data count of a Tx descriptor is advertised to users,
however, this value is mistakenly derived from the Rx define.
Use the Tx one instead. The resulting value will be the same.
Fixes: 1e43fe3cb4 ("net/sfc/base: separate limitations on Tx DMA descriptors")
Cc: stable@dpdk.org
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Added changes to base rule install mechanism.
If action type is IPsec and multi channel is set,
then base rule will not be merged.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Reviewed-by: Satheesh Paul <psatheesh@marvell.com>
Current PMD logs all DevX errors at error level.
DevX interface can fail queue counters allocation on some hardware
types. That is a known issue.
PMD fallbacks to Verbs API to allocate queue counters
when it detects the fault.
That DevX failure should not be logged as PMD error.
The patch provides DevX with flexible API that selects log level.
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
VF is able to subscribe a flow from PF by VIRTCHNL_FLOW_SUBSCRIBE.
PF is expected to offload a rule to hardware which will redirect
the packet that matching the required pattern to this VF.
Only a flow with dst mac address as PF's mac address can be subscribed.
VIRTCHNL_VF_OFFLOAD_FSUB_PF is used for Flow subscription capability
negotiation and only a trusted VF can be granted with this capability.
A flow can be unsubscribed by VIRTCHNL_FLOW_UNSUBSCRIBE.
Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
If cmd_details are defined or async flag is set,
don't copy the desc/buff back to temp.
Fixes: e5b2a9e957 ("net/avf/base: add base code for avf PMD")
Cc: stable@dpdk.org
Signed-off-by: Steven Zou <steven.zou@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Disable timer resolution estimation, read TIM LF clock registers
to get the current running clock counter as estimating causes
time drift.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Removed support to limit XAQ from devargs. If XAQ is limited, new add
works could run out of XAQ entries and disable the queue.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Add support for offloading RTE_CRYPTO_CIPHER_AES_DOCSISBPI and
RTE_CRYPTO_CIPHER_DES_DOCSISBPI algorithms to symmetric crypto session.
Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Errors in crypto adapter datapath can be handled gracefully. So the
error print can be moved under debug.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
