According to the datasheet, TX_DESC_CTL is cleared when whole frame is transmitted or all
data in the current descriptor's buffer are transmitted.
When the mbuf and mapping are stored in the first segment and in a scenario where a tx
completion interrupt arrives for a frame and only the start of the next frame was transmitted,
at the time of interrupt processing the mbuf and mapping will be freed when processing the
first segment of the next frame but the other untrasmitted segments still need to use them.
Submitted by: Guy Yur <guyyur@gmail.com>
Differential Revision: https://reviews.freebsd.org/D13031
In a multi segment frame, if the first tx descriptor is marked with TX_DESC_CTL
but not all tx descriptors for the other segments in the frame are set up,
the TX DMA may transmit an incomplete frame.
To prevent this, set TX_DESC_CTL for the first tx descriptor only when done
with all the other segments.
Also, don't bother cleaning transmitted tx descriptors since TX_DESC_CTL
is cleared for them by the hardware and they will be reprogrammed before
TX_DESC_CTL is reenabled for them.
Submitted by: Guy Yur <guyyur@gmail.com>
Differential Revision: https://reviews.freebsd.org/D13030
The hardware will not issue a completion interrupt for a descriptor
with TX_INT_CTL set if it doesn't also have TX_LAST_DESC set.
Submitted by: Guy Yur <guyyur_gmail.com>
Differential Revision: https://reviews.freebsd.org/D13029
DTS files switch from clocks under /clocks to a ccu (Clock Controller Unit)
a while ago.
Restore A13 functionality by adding a clock driver for it.
Almost every clocks are handled, the missing ones are mostly video related
clocks.
Tested On: A13 Olinuxino
Under certain traffic pattern awg driver does not recover from TX queue
full condition. The actual source of the problem is not identified yet
but jmcneill@ agreed that bumping TX_MAX_SEGS to 20 is OK as a workaround
for the problem (NetBSD has it set to 128).
Also add some diagnostic printfs to prevent silent failure of bus_dma
functions in the future
PR will be kept open until root cause of the issue is identified and fixed
PR: 219927
Submitted by: Tom Vijlbrief <tvijlbrief@gmail.com>
Approved by: jmcneill
MFC after: 2 weeks
It doesn't seems to be needed anymore and this make ehci working again
on the Pine64.
Thanks to jmcneill@ for the help.
Tested on: Pine64 (A64), OrangePi One (H3), BananapiM2 (A31s)
SUN8I and SUN50I (H3, H5, A83T and A64) have a second clock controller
unit. It controls the clocks for the second gpio controller, the IR
controller etc ...
Support for A83T is not supported.
Tested On: OrangePi One, Pine64
Transition all boards that support arm cortex CPUs to armv7. This
leaves two armv6 kernels in the tree. RPI-B, which uses the BCM2835
which has a ARM1176 core, and VERSATILEPB, which is a qemu board setup
around the time RPI-B went in. Copy std.armv6 to std.armv7, even
though that duplicates a lot of stuff. More work needs to be done to
sort out the duplication.
Differential Revision: https://reviews.freebsd.org/D12027
ccu_h3.c is also used on ARM64 as it provides clocks for the H5 SoC.
Since ARM64 doesn't have sys/gun/dts/include in it's include path, use
the full name for the sun8i-h3-ccu.h include.
Reported by: andreast
Do not redefines resets and clocks ID which are already in the
dt-bindings include directory. Those files are under dual licenced
under GPL2/MIT so use them directly.
Do not redefines resets and clocks ID which are already in the
dt-bindings include directory. Those files are under dual licenced
under GPL2/MIT so use them directly.
Do not redefines resets and clocks ID which are already in the
dt-bindings include directory. Those files are under dual licence
GPL2/MIT so use them directly.
attachment code for various SOCs and busses. Remove all the static and
should-have-been-static and named-differently instances of it.
This should eliminate the recently-grown build warnings about multiple
definitions when building arm kernels.
Some SoC require a write to a unknown register to work corectly.
This write should be in the pmu region not in the phy ctrl one.
Reported by: Mark Millard (markmi@dsl-only.net)
The usbphy node for allwinner have two kind of resources, one for the
phy_ctrl and one per phy. Instead of blindy allocating resources, alloc
the phy_ctrl and pmu ones separately.
Also add a configuration struct for all different phy that hold the difference
between them (number of phys, unknow needed register write etc ...).
While here remove A83T code as upstream and FreeBSD dts don't have
nodes for USB.
This (plus 323640) re-enable OHCI on Pine64 on the bottom USB port.
The top USB port is routed to the OHCI0/EHCI0 which is by default in OTG mode.
While the phy code can handle the re-route to standard OHCI/EHCI we still need
a driver for musb to probe and configure it in host mode.
EHCI is still buggy on Pine64 (hang the board) so do not enable it for now.
Tested On: Bananapi (A20), BananapiM2 (A31S), OrangePi One (H3) Pine64 (A64)
r323392 introduce gpio_pin_get/gpio_pin_set for a10_gpio driver.
When called via gpio method they must aquire the device lock while
when they are called via gpio_pin_configure the lock is already aquire.
Introduce a10_gpio_pin_{s,g}et_locked and call them in pin_gpio_configure
instead.
Tested On: BananaPi (A20)
Reported by: Richard Puga richard@puga.net
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
If we cannot get a phy, do not detach the driver, some boards have phy
always enabled and not exposed.
While here do not release the clocks if we fails as we release them
in a10_ehci_detach.
Tested-on: OrangePi-One
Upstream DTS for A64 SoC doesn't provide a /clocks node as Linux switched
to ccu-ng
This commit adds the necessary bits to boot on pine64 with latest DTS from
upstream.
USB is not working for now and some node aren't present in the DTS (like the
PMU, Power Management Unit).
Tested on: Pine64
H2+ SoC is a stripped down version of H3 without gigabit ethernet and 4K HDMI.
Also add sun8i-h2-plus-orangepi-zero.dts to the build as we run on this board.
Starting with DTS from Linux 4.11, the pins list, function, drive and pull
are no longer prefixed with "allwinner,".
Allow the pinctrl driver to handle both case.
as kernel drivers and their dependency onto mmc(4); this allows for
incrementing the mmc(4) module version but also for entire omission
of these bridge declarations for mmccam(4) in a single place, i. e.
in dev/mmc/bridge.h.
comments, marking unused parameters as such, style(9), whitespace,
etc.
o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
- Remove redundant assignments of the default bus_generic_print_child
device method (I've whipped these out of the tree as part of r227843
once, but they keep coming back ...),
- use DEVMETHOD_END,
- use NULL instead of 0 for pointers.
o Trim/adjust includes.
This adds clocks support for the aw_ccung on the A31 SoC.
Newer DTS files require this.
All the clocks except two CSI are defined and exported on the clock domain.
The PLL_DDR clock have an update bit which need to be set after changing
the value, add the possibility to define one for NKMP clocks.
This allow us to add the missing clocks.
We now have the full list of clocks created under the clock domain.
Since Linux 4.9-4.10 DTS doesn't have clocks under /clocks but only a ccu node.
Currently only H3 is supported with almost the same state as HEAD.
(video pll aren't supported for now but we don't support video).
This driver and clocks will also be used for other SoC (A64, A31, H5, H2 etc ...)
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D9517
- Use new option SMP_ON_UP instead of (mis)using specific CPU type.
By this, any SMP kernel can be compiled with SMP_ON_UP support.
- Enable runtime detection of CPU multiprocessor extensions only
if SMP_ON_UP option is used. In other cases (pure SMP or UP),
statically compile only required variant.
- Don't leak multiprocessor instructions to UP kernel.
- Correctly handle data cache write back to point of unification.
DCCMVAU is supported on all armv7 cpus.
- For SMP_ON_UP kernels, detect proper TTB flags on runtime.
Differential Revision: https://reviews.freebsd.org/D9133
Add basic support for A33/R16 that is enough to boot a kernel.
This adds the platform code, padconf data and the new clocks strings.
MFC after: 2 weeks
file and add a generic DT binding that takes advantage of the extres
framework for setting up clocks.
Reviewed by: gonzo
Differential Revision: https://reviews.freebsd.org/D8826
Replace them with a default handler that returns devmap_lastaddr.
Reviewed by: mmel
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D8806
can be selected for it. If the desired frequency is one of those two, use
this mode instead of the integer one.
When calculating the PLL3 freq for the dotclock, check if it is a multiple
of the fracional frequencies.
MFC after: 2 weeks
The audio controller in the H3 is more or less the same as A10/A20 except
some registers are shuffled around. The mixer interface, however, is
completely different between SoCs. Separate a10_mixer_class and
h3_mixer_class implementations are now made available. This will also make
adding support for other SoCs easier in the future.
Reviewed by: andrew, ganbold
Relnotes: yes
Differential Revision: https://reviews.freebsd.org/D8425
PLL1 is used by the cpu core, allowing changing freq is needed for cpufreq.
The factors table contains all the frequencies in the operating point table
present in the DTS.
MFC after: 1 week
Push-Pull Two Wire interface is a almost compatible iic like bus used
in sun6i SoC. It's only use is to communicate with the power management IC.
Reviewed by: jmcneill
MFC after: 1 week
Relnotes: yes
prevent overheating.
When sensor 0's alarm interrupt is fired, set a throttle flag. Further
requests to set CPU frequency will be rejected until sensor 0's temperature
returns to a level below the hot temperature threshold.
Relnotes: yes
When detaching device trees parent devices must be detached prior to
detaching its children. This is because parent devices can have
pointers to the child devices in their softcs which are not
invalidated by device_delete_child(). This can cause use after free
issues and panic().
Device drivers implementing trees, must ensure its detach function
detaches or deletes all its children before returning.
While at it remove now redundant device_detach() calls before
device_delete_child() and device_delete_children(), mostly in
the USB controller drivers.
Tested by: Jan Henrik Sylvester <me@janh.de>
Reviewed by: jhb
Differential Revision: https://reviews.freebsd.org/D8070
MFC after: 2 weeks
for later Cortex-A CPUs that support the Multiprocessor Extensions. This
will be needed to support both in a single GENERIC kernel while still
being able to only build for a single SoC.
Reviewed by: mmel
Relnotes: yes
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D8138
Rename registers as in the manual.
Do a hard reset of the controller before a soft one.
Since DMA is always used remove dependancy on allwinner_soc_family, it was used
to differentiate SoC as the fdt compatible string were the same.
Tested on A10, A20, H3 and A64.
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D6868
The thermal sensor lives in the touch screen controller. Touch screen part
isn't done for now.
Temperature is read every ~2 seconds and exposed via sysctl.
to generate one. This is was U-Boot does to generate a random MAC so we end
up with the same MAC address as if U-Boot did generate it.
MFC after: 1 week
Allwinner Uniprocessor SoC.
As of now it works with A10 and A13 (and possibly R8 as it is the same as the A13).
Move files.a10 into a1o subdirectory as it should be.
Rename std.a10 into std.allwinner_up
This removes the need to set the MMC pins with pullups in our DTS.
Thanks to jmcneill@ for spotting this.
Tested on Orange Pi One (Allwinner H3).
MFC after: 1 week
GPIO_INPUT/GPIO_OUTPUT.
a10_gpio_get_pud now returns the whole pud not only PULLDOWN/PULLUP.
Add a10_gpio_get_drv to get the current drive strenght.
During fdt pin configure, avoid setting function/drive/pud if it's already in
the correct value.
Tested on Allwinner H3 and A20
MFC after: 1 week
The rootkey is burnt at production and can't be changed, thus is can be used
as a device unique ID or to generate a MAC address (This is was u-boot does).
The rootkey is exposed as a sysctl (dev.aw_sid.<unit>.rootkey).
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D6383
H3 EMAC is the same as A83T/A64 except the SoC includes an (optional)
internal 10/100 PHY. Both internal and external PHYs are supported on H3
with this driver.
- Support DEVICE_POLLING
- Increase TX descriptors to 1024
- Add support for passing a chain of mbufs to if_input, reducing the
number of calls to mtx_unlock/mtx_lock under load.
- Remove duplicate byteswap when setting TX_INT_CTL in TX descriptor.
- Set undocumented "TX_NEXT_FRAME" bit in TX control 1 register.
According to the A83T BSP, setting this bit allows the DMA engine to
operate on a packet while receiving another.
Tested on A83T (1000Mbps PHY) and H3 (100Mbps PHY).
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D7031
on arm64 and all SoCs using the old FIFO register location are 32-bit only,
so unconditionally use the new location for arm64.
Reviewed by: andrew, manu
In some cases, the driver must handle given properties located in
specific OF subnode. Instead of creating duplicate set of function, add
'node' as argument to existing functions, defaulting it to device OF node.
MFC after: 3 weeks
Pressing the PEK (power enable key) will shutdown the board.
Some events are reported to devd via system "PMU" and subsystem
"Battery", "AC" and "USB" such as connected/disconnected.
Some sensors values (power source voltage/current) are reported via
sysctl (dev.axp209_pmu.X.)
It also expose a gpioc node usable in kernel and userland. Only 3 of
the 4 GPIO are exposed (The GPIO3 is different and mostly unused on
boards). Most popular boards uses GPIO1 as a sense pin for OTG power.
Add a dtsi file that adds gpio-controller capability to the device as
upstream doesn't defined it and include it in our custom DTS.
Reviewed by: jmcneill
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D6135
Previously the USB PHY driver would enable all regulators at attach time.
This prevented boards from booting when powered by the USB OTG port, as
it didn't take VBUS presence into consideration.
After r285994, sysctl(8) was fixed to use 273.15 instead of 273.20 as 0C
reference and as result, the temperature read in sysctl(8) now exibits a
+0.1C difference.
This commit fix the kernel references to match the reference value used in
sysctl(8) after r285994.
Sponsored by: Rubicon Communications (Netgate)
needed in later changes where we may not be able to lock the pic list lock
to perform a lookup, e.g. from within interrupt context.
Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation
If platform support EXT_RESOURCES, clocks and resets are handled out of
the box.
If not driver can be subclassed using the generic_usb interface.
generic_usb name was choosed because at one point I'll add generic-ehci
FDT driver.
Reviewed by: jmcneill, hselasky
Approved by: andrew (mentor)
Differential Revision: https://reviews.freebsd.org/D5481
The A83T thermal sensor controller has three sensors. Sensor 0 corresponds
to CPU cluster 0, sensor 1 to CPU cluster 1, and sensor 2 to the GPU. This
driver exports the temperature sensor readings via sysctl.
Calibration data is obtained from SRAM found in the Secure ID module.
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D6378
The RSB controller speaks a simplified two wire protocol at speeds up to
20MHz. It is used on sun8i and sun9i family SoCs to communicate with
power management ICs.
RSB isn't really I2C or SMBus, but the driver exposes an iicbus interface
to simplify power management IC drivers (which may need to support both
RSB and I2C connectivity).
This function works with all smp non-multicluster allwinner SoC (A20, A31, A31S and H3).
Approved by: cognet (mentor)
Differential Revision: https://reviews.freebsd.org/D6269
struct associated with some type defined in enum intr_map_data_type
must have struct intr_map_data on the top of its own definition now.
When such structs are used, correct type and size must be filled in.
There are three such structs defined in sys/intr.h now. Their
definitions should be moved to corresponding headers by follow-up
commits.
While this change was propagated to all INTRNG like PICs,
pic_map_intr() method implementations were corrected on some places.
For this specific method, it's ensured by a caller that the 'data'
argument passed to this method is never NULL. Also, the return error
values were standardized there.
Clocks, GPIO, UART, SD card / eMMC, USB, watchdog, and ethernet are
supported. Note that the A83T contains two clusters of four Cortex-A7
CPUs, and only CPUs in first cluster are started for now.
Tested on a Sinovoip Banana Pi BPI-M3.
The datasheets refer to this controller as EMAC, not to be confused with
the fast ethernet controller (also named EMAC) found in A10/A20 SoCs.
Tested on a BananaPi M3 (A83T), which uses an external RGMII PHY (RTL8211E).
Reviewed by: adrian
Differential Revision: https://reviews.freebsd.org/D6169
implementations. Early in the boot the kernel will use an approximate,
however after the timer has been probed it will switch to a more accurate
implementation.
Reviewed by: manu
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5762
Set MMC_CAP_4_BIT_DATA and MMC_CAP_8_BIT_DATA based on the "bus-width"
DT property and reduce maximum bus frequency from 52MHz to 50MHz to match
the capabilities of the clock provider.
Tested on a BananaPi BPI-M3 (A83T).
a DRIVER_MODULE() referencing mmc_driver has a MODULE_DEPEND() on mmc. This
is because the kernel linker only searches for symbols in dependent modules,
so loading sdhci_pci (and other bus-flavors of sdhci) would fail when mmc
was not compiled into the kernel (even if you hand-loaded mmc first).
(Thanks to jilles@ for providing the vital clue about the kernel linker.)
code for the A20 to use the new PLATFORM_SMP interface, and extends it to
add support for the new SoCs allowing for both to coexist within the same
kernel.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D5342
adds a lock to ensure only a single device is accessing the hardware. A
reference count is added to only enable when we start to use the clock,
and to disable after we have finished needing the clock.
This was extracted from a larger review to add OHCI support to the
Allwinner SoCs.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: jmcneill
X-Differential Revision: https://reviews.freebsd.org/D5481
Very similar to the A10 RTC controller with a few register offsets changed
and a different location for the LOSC switch status.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: jmcneill
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D5500
Newer Allwinner MMC implementations use a different FIFO register offset
(0x200 instead of 0x100). Since the FDT uses the same compat string for
both cases, base the decision on which FIFO offset to use on the Allwinner
SoC family.
Reviewed by: Emmanuel Vadot <manu@bidouilliste.com>
Approved by: gonzo (mentor)
Differential Revision: https://reviews.freebsd.org/D5468
intr_pic_init_secondary. Replace them with a direct call. On BCM2836
and ARMADA XP we need to add this function, but it can be empty.
Reviewed by: ian, imp
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5460
slightly wrong on the others. We should just check if mp_ncpus is set to
more than one CPU as we may wish to run on a single core even when SMP is
available.
Reviewed by: ian
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5458
support for the i2c, mmc, and gmac clocks. Further clocks can be added as
needed.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Reviewed by: jmcneill
Differential Revision: https://reviews.freebsd.org/D5339
The HDMI driver will attach a framebuffer device when a display is
connected. If the EDID can be read and contains a preferred mode, it
will be used. Otherwise the framebuffer will default to 800x600.
In addition, if the EDID contains a CEA-861 extension block and the
"basic audio" flag is set, audio playback at 48kHz 16-bit stereo is
enabled on the controller.
Reviewed by: andrew
Approved by: gonzo (mentor)
Differential Revision: https://reviews.freebsd.org/D5383
driver. This mostly involves selecting the register offsets to use at
runtime based on the hardware we are talking to.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D5327
will be needed when we bring in further support for these SoCs.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D5340
For sources and destinations marked "noincr", the previous code was
incorrectly programming the dedicated DMA channel control register
using bit definitions for normal DMA channels. This code path is not
currently used, but will be used by the HDMI audio driver in review.
Reviewed by: andrew
Approved by: gonzo (mentor)
Differential Revision: https://reviews.freebsd.org/D5382
Only L2 PIPT cache is supported for __ARM_ARCH >= 6.
In fact, this is just a pure proclamation as this option is used
only in armv4 specific files now.
FDT platform code to detect when we are booting on one of these SoCs. The
driver changes will be added shortly.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D5338
configuration from the FDT data, then set the pins into the requested
state. As part of this the gpio controller now reports the correct number
of pins instead of returning the number of bank * 32.
To allow for a future consolidated kernel we add the SOC_ALLWINNER_A10 and
SOC_ALLWINNER_A20 kernel options. These need to be set as appropriate for
the SoC the kernel will boot on.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D5177
A10/A20 SoC. Based loosely on the submitters NetBSD driver, tested on
Cubieboard 2. Playback and capture are supported.
Submitted by: Jared McNeill <jmcneill@invisible.ca>
Differential Revision: https://reviews.freebsd.org/D5202
least the audio codec driver currently in review.
Submitted by: Jared McNeill <jmcneill@invisible.ca>
Differential Revision: https://reviews.freebsd.org/D5050
with this and an Allwinner SoC to power off.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D4954
Marvell twsi part, however uses different register locations, as such split
the existing driver into Marvell and Allwinner attachments.
While here clean a few style issues.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D4846
* Use the Linux compat string
* Use EARLY_DRIVER_MODULE to attach at the right time
* Add a generic A10 kernel config file
* A20 now use generic_timer
* Add two new dts files for Olimex boards
* Update our custom DTS file for A10 and A20 to use the same compatible
property names as the vendor ones.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D4792
* Use the ARM PLATFORM framework
* Use ARM_INTRNG on teh A20 as it has a GICv2
* Add a method to find which Allwinner SoC we are running on
Differential Revision: https://reviews.freebsd.org/D5059
The ci20 port (by kan@) is going to reuse almost all of the intrng code
since the SoC in question looks suspiciously like someone took an ARM
SoC design and replaced the ARM core with a MIPS core.
* migrate out the code;
* rename ARM_ -> INTR_;
* rename arm_ -> intr_;
* move the interrupt flush routine from intr.c / intrng.c into
arm/machdep_intr.c - removing the code duplication and removing
the ARM specific bits from here.
Thanks to the Star Wars: The Force Awakens premiere line for allowing
me a couple hours of quiet time to finish the universe builds.
Tested:
* make universe
TODO:
* The structure definitions in subr_intr.c still includes machine/intr.h
which requires one duplicates all of the intrng definitions in
the platform code (which kan has done, and I think we don't have to.)
Instead I should break out the generic things (function declarations,
common intr structures, etc) into a separate header.
* Kan has requested I make the PIC based IPI stuff optional.
the name the function will have when the new ARM_INTRNG code is integrated,
and doing this rename first will make it easier to toggle the new interrupt
handling code on/off with a config option for debugging.
This code initializes the GMAC clock and sets the pin mux to rgmii.
It also override the if_dwc defaults to set the alternate descriptor type
and MII clock used on A20.
Tested on cubieboard2 and banana pi.
pins, they specify the bank and the pin in two separated cells.
This allow the use of vendor's DTS definitions by adding a gpio map
routine that copes with that.
o Return the real hardware state in gpio_pin_getflags() instead of keep
the last state in an internal table. Now the driver returns the real
state of pins (input/output and pull-up/pull-down) at all times.
o Use a spin mutex. This is required by interrupts and the 1-wire code.
o Use better variable names and place parentheses around them in MACROS.
o Do not lock the driver when returning static data.
Tested with gpioled(4) and DS1820 (1-wire) sensors on banana pi.
change to GMAC easier on A20 SoCs.
On A10 only the EMAC controller is available (fast ethernet), but on A20
there is also GMAC a high (or better) performant controller (gigabit
ethernet).
On A20 the both controllers uses the same pins to talk to the ethernet PHY
(MII or RGMII) and they can be selected by the GPIO pin mux.
There is work in progress to bring in GMAC support.
The Allwinner SoC has an AHCI device on its internal main bus rather
than the PCI bus. This SoC is somewhat underdocumented, and its SATA
controller is no exception. The methods to support this chip were
harvested from the Linux Allwinner SDK, and then constants invented to
describe what's going on based on low-level constants contained in the
SATA standard and guess work.
This SoC requires a specific AHCI channel setup in order to start the
operations on the channel properly.
Clock setup and AHCI channel setup idea came from NetBSD.
Tested on Cubieboard 2 and Banana pi (and attachment on Cubieboard by
Pratik Singhal).
Differential Revision: https://reviews.freebsd.org/D737
Submitted by: imp
Reviewed by: imp, ganbold, mav, andrew
DMA handles all data transfers up to 128K or 16 segments and fallback to
pio mode when DMA requirements are not met.
The read performance has improved greatly while the write performance also
showed some improvement but seems limited by the card type and quality.
Submitted by: Pratik Singhal <pratiksinghal@freebsd.org>
Sponsored by: Google Summer of Code 2015
Tested on: A10 (cubieboard) and A20 (cubieboard 2 and banana pi)
This is based on the patch sent by Alexander Fedorov with the following
fixes/improvements:
- Better error handling;
- Clock is derived from PLL6 (obtained from netbsd);
- No more unnecessary busy loops on interrupt handler;
- style(9) fixes and code cleanup.
I also want to thanks Martin Galvan who has sent an alternative
implementation with some interesting fixes.
Tested on CubieBoard2, Banana-Pi (thanks to netgate!) and Cubieboard1
(Pratik Singhal).
This is intended to pave the way for the upcoming GSoC work (and make
easier the build of images for the supported boards).
PR: 196081
Submitted by: Alexander Fedorov <alexander.fedorov@rtlservice.com>
